1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/accel.h" 15 #include "sysemu/replay.h" 16 #include "hw/boards.h" 17 #include "hw/loader.h" 18 #include "qapi/error.h" 19 #include "qapi/qapi-visit-machine.h" 20 #include "qom/object_interfaces.h" 21 #include "sysemu/cpus.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/reset.h" 24 #include "sysemu/runstate.h" 25 #include "sysemu/xen.h" 26 #include "sysemu/qtest.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "hw/mem/nvdimm.h" 29 #include "migration/global_state.h" 30 #include "exec/confidential-guest-support.h" 31 #include "hw/virtio/virtio-pci.h" 32 #include "hw/virtio/virtio-net.h" 33 #include "hw/virtio/virtio-iommu.h" 34 #include "audio/audio.h" 35 36 GlobalProperty hw_compat_9_0[] = {}; 37 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); 38 39 GlobalProperty hw_compat_8_2[] = { 40 { "migration", "zero-page-detection", "legacy"}, 41 { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, 42 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" }, 43 }; 44 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2); 45 46 GlobalProperty hw_compat_8_1[] = { 47 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, 48 { "ramfb", "x-migrate", "off" }, 49 { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, 50 { "igb", "x-pcie-flr-init", "off" }, 51 }; 52 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 53 54 GlobalProperty hw_compat_8_0[] = { 55 { "migration", "multifd-flush-after-each-section", "on"}, 56 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 57 { TYPE_VIRTIO_NET, "host_uso", "off"}, 58 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 59 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 60 }; 61 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 62 63 GlobalProperty hw_compat_7_2[] = { 64 { "e1000e", "migrate-timadj", "off" }, 65 { "virtio-mem", "x-early-migration", "false" }, 66 { "migration", "x-preempt-pre-7-2", "true" }, 67 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 68 }; 69 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 70 71 GlobalProperty hw_compat_7_1[] = { 72 { "virtio-device", "queue_reset", "false" }, 73 { "virtio-rng-pci", "vectors", "0" }, 74 { "virtio-rng-pci-transitional", "vectors", "0" }, 75 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 76 }; 77 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 78 79 GlobalProperty hw_compat_7_0[] = { 80 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 81 { "nvme-ns", "eui64-default", "on"}, 82 }; 83 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 84 85 GlobalProperty hw_compat_6_2[] = { 86 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 87 }; 88 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 89 90 GlobalProperty hw_compat_6_1[] = { 91 { "vhost-user-vsock-device", "seqpacket", "off" }, 92 { "nvme-ns", "shared", "off" }, 93 }; 94 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 95 96 GlobalProperty hw_compat_6_0[] = { 97 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 98 { "i8042", "extended-state", "false"}, 99 { "nvme-ns", "eui64-default", "off"}, 100 { "e1000", "init-vet", "off" }, 101 { "e1000e", "init-vet", "off" }, 102 { "vhost-vsock-device", "seqpacket", "off" }, 103 }; 104 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 105 106 GlobalProperty hw_compat_5_2[] = { 107 { "ICH9-LPC", "smm-compat", "on"}, 108 { "PIIX4_PM", "smm-compat", "on"}, 109 { "virtio-blk-device", "report-discard-granularity", "off" }, 110 { "virtio-net-pci-base", "vectors", "3"}, 111 { "nvme", "msix-exclusive-bar", "on"}, 112 }; 113 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 114 115 GlobalProperty hw_compat_5_1[] = { 116 { "vhost-scsi", "num_queues", "1"}, 117 { "vhost-user-blk", "num-queues", "1"}, 118 { "vhost-user-scsi", "num_queues", "1"}, 119 { "virtio-blk-device", "num-queues", "1"}, 120 { "virtio-scsi-device", "num_queues", "1"}, 121 { "nvme", "use-intel-id", "on"}, 122 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 123 { "pl011", "migrate-clk", "off" }, 124 { "virtio-pci", "x-ats-page-aligned", "off"}, 125 }; 126 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 127 128 GlobalProperty hw_compat_5_0[] = { 129 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 130 { "virtio-balloon-device", "page-poison", "false" }, 131 { "vmport", "x-read-set-eax", "off" }, 132 { "vmport", "x-signal-unsupported-cmd", "off" }, 133 { "vmport", "x-report-vmx-type", "off" }, 134 { "vmport", "x-cmds-v2", "off" }, 135 { "virtio-device", "x-disable-legacy-check", "true" }, 136 }; 137 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 138 139 GlobalProperty hw_compat_4_2[] = { 140 { "virtio-blk-device", "queue-size", "128"}, 141 { "virtio-scsi-device", "virtqueue_size", "128"}, 142 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 143 { "virtio-blk-device", "seg-max-adjust", "off"}, 144 { "virtio-scsi-device", "seg_max_adjust", "off"}, 145 { "vhost-blk-device", "seg_max_adjust", "off"}, 146 { "usb-host", "suppress-remote-wake", "off" }, 147 { "usb-redir", "suppress-remote-wake", "off" }, 148 { "qxl", "revision", "4" }, 149 { "qxl-vga", "revision", "4" }, 150 { "fw_cfg", "acpi-mr-restore", "false" }, 151 { "virtio-device", "use-disabled-flag", "false" }, 152 }; 153 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 154 155 GlobalProperty hw_compat_4_1[] = { 156 { "virtio-pci", "x-pcie-flr-init", "off" }, 157 }; 158 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 159 160 GlobalProperty hw_compat_4_0[] = { 161 { "VGA", "edid", "false" }, 162 { "secondary-vga", "edid", "false" }, 163 { "bochs-display", "edid", "false" }, 164 { "virtio-vga", "edid", "false" }, 165 { "virtio-gpu-device", "edid", "false" }, 166 { "virtio-device", "use-started", "false" }, 167 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 168 { "pl031", "migrate-tick-offset", "false" }, 169 }; 170 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 171 172 GlobalProperty hw_compat_3_1[] = { 173 { "pcie-root-port", "x-speed", "2_5" }, 174 { "pcie-root-port", "x-width", "1" }, 175 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 176 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 177 { "tpm-crb", "ppi", "false" }, 178 { "tpm-tis", "ppi", "false" }, 179 { "usb-kbd", "serial", "42" }, 180 { "usb-mouse", "serial", "42" }, 181 { "usb-tablet", "serial", "42" }, 182 { "virtio-blk-device", "discard", "false" }, 183 { "virtio-blk-device", "write-zeroes", "false" }, 184 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 185 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 186 }; 187 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 188 189 GlobalProperty hw_compat_3_0[] = {}; 190 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 191 192 GlobalProperty hw_compat_2_12[] = { 193 { "migration", "decompress-error-check", "off" }, 194 { "hda-audio", "use-timer", "false" }, 195 { "cirrus-vga", "global-vmstate", "true" }, 196 { "VGA", "global-vmstate", "true" }, 197 { "vmware-svga", "global-vmstate", "true" }, 198 { "qxl-vga", "global-vmstate", "true" }, 199 }; 200 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 201 202 GlobalProperty hw_compat_2_11[] = { 203 { "hpet", "hpet-offset-saved", "false" }, 204 { "virtio-blk-pci", "vectors", "2" }, 205 { "vhost-user-blk-pci", "vectors", "2" }, 206 { "e1000", "migrate_tso_props", "off" }, 207 }; 208 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 209 210 GlobalProperty hw_compat_2_10[] = { 211 { "virtio-mouse-device", "wheel-axis", "false" }, 212 { "virtio-tablet-device", "wheel-axis", "false" }, 213 }; 214 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 215 216 GlobalProperty hw_compat_2_9[] = { 217 { "pci-bridge", "shpc", "off" }, 218 { "intel-iommu", "pt", "off" }, 219 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 220 { "pcie-root-port", "x-migrate-msix", "false" }, 221 }; 222 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 223 224 GlobalProperty hw_compat_2_8[] = { 225 { "fw_cfg_mem", "x-file-slots", "0x10" }, 226 { "fw_cfg_io", "x-file-slots", "0x10" }, 227 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 228 { "pci-bridge", "shpc", "on" }, 229 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 230 { "virtio-pci", "x-pcie-deverr-init", "off" }, 231 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 232 { "virtio-pci", "x-pcie-pm-init", "off" }, 233 { "cirrus-vga", "vgamem_mb", "8" }, 234 { "isa-cirrus-vga", "vgamem_mb", "8" }, 235 }; 236 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 237 238 GlobalProperty hw_compat_2_7[] = { 239 { "virtio-pci", "page-per-vq", "on" }, 240 { "virtio-serial-device", "emergency-write", "off" }, 241 { "ioapic", "version", "0x11" }, 242 { "intel-iommu", "x-buggy-eim", "true" }, 243 { "virtio-pci", "x-ignore-backend-features", "on" }, 244 }; 245 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 246 247 GlobalProperty hw_compat_2_6[] = { 248 { "virtio-mmio", "format_transport_address", "off" }, 249 /* Optional because not all virtio-pci devices support legacy mode */ 250 { "virtio-pci", "disable-modern", "on", .optional = true }, 251 { "virtio-pci", "disable-legacy", "off", .optional = true }, 252 }; 253 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 254 255 GlobalProperty hw_compat_2_5[] = { 256 { "isa-fdc", "fallback", "144" }, 257 { "pvscsi", "x-old-pci-configuration", "on" }, 258 { "pvscsi", "x-disable-pcie", "on" }, 259 { "vmxnet3", "x-old-msi-offsets", "on" }, 260 { "vmxnet3", "x-disable-pcie", "on" }, 261 }; 262 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 263 264 GlobalProperty hw_compat_2_4[] = { 265 /* Optional because the 'scsi' property is Linux-only */ 266 { "virtio-blk-device", "scsi", "true", .optional = true }, 267 { "e1000", "extra_mac_registers", "off" }, 268 { "virtio-pci", "x-disable-pcie", "on" }, 269 { "virtio-pci", "migrate-extra", "off" }, 270 { "fw_cfg_mem", "dma_enabled", "off" }, 271 { "fw_cfg_io", "dma_enabled", "off" } 272 }; 273 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 274 275 GlobalProperty hw_compat_2_3[] = { 276 { "virtio-blk-pci", "any_layout", "off" }, 277 { "virtio-balloon-pci", "any_layout", "off" }, 278 { "virtio-serial-pci", "any_layout", "off" }, 279 { "virtio-9p-pci", "any_layout", "off" }, 280 { "virtio-rng-pci", "any_layout", "off" }, 281 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 282 { "migration", "send-configuration", "off" }, 283 { "migration", "send-section-footer", "off" }, 284 { "migration", "store-global-state", "off" }, 285 }; 286 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 287 288 GlobalProperty hw_compat_2_2[] = {}; 289 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 290 291 GlobalProperty hw_compat_2_1[] = { 292 { "intel-hda", "old_msi_addr", "on" }, 293 { "VGA", "qemu-extended-regs", "off" }, 294 { "secondary-vga", "qemu-extended-regs", "off" }, 295 { "virtio-scsi-pci", "any_layout", "off" }, 296 { "usb-mouse", "usb_version", "1" }, 297 { "usb-kbd", "usb_version", "1" }, 298 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 299 }; 300 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 301 302 MachineState *current_machine; 303 304 static char *machine_get_kernel(Object *obj, Error **errp) 305 { 306 MachineState *ms = MACHINE(obj); 307 308 return g_strdup(ms->kernel_filename); 309 } 310 311 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 312 { 313 MachineState *ms = MACHINE(obj); 314 315 g_free(ms->kernel_filename); 316 ms->kernel_filename = g_strdup(value); 317 } 318 319 static char *machine_get_initrd(Object *obj, Error **errp) 320 { 321 MachineState *ms = MACHINE(obj); 322 323 return g_strdup(ms->initrd_filename); 324 } 325 326 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 327 { 328 MachineState *ms = MACHINE(obj); 329 330 g_free(ms->initrd_filename); 331 ms->initrd_filename = g_strdup(value); 332 } 333 334 static char *machine_get_append(Object *obj, Error **errp) 335 { 336 MachineState *ms = MACHINE(obj); 337 338 return g_strdup(ms->kernel_cmdline); 339 } 340 341 static void machine_set_append(Object *obj, const char *value, Error **errp) 342 { 343 MachineState *ms = MACHINE(obj); 344 345 g_free(ms->kernel_cmdline); 346 ms->kernel_cmdline = g_strdup(value); 347 } 348 349 static char *machine_get_dtb(Object *obj, Error **errp) 350 { 351 MachineState *ms = MACHINE(obj); 352 353 return g_strdup(ms->dtb); 354 } 355 356 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 357 { 358 MachineState *ms = MACHINE(obj); 359 360 g_free(ms->dtb); 361 ms->dtb = g_strdup(value); 362 } 363 364 static char *machine_get_dumpdtb(Object *obj, Error **errp) 365 { 366 MachineState *ms = MACHINE(obj); 367 368 return g_strdup(ms->dumpdtb); 369 } 370 371 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 372 { 373 MachineState *ms = MACHINE(obj); 374 375 g_free(ms->dumpdtb); 376 ms->dumpdtb = g_strdup(value); 377 } 378 379 static void machine_get_phandle_start(Object *obj, Visitor *v, 380 const char *name, void *opaque, 381 Error **errp) 382 { 383 MachineState *ms = MACHINE(obj); 384 int64_t value = ms->phandle_start; 385 386 visit_type_int(v, name, &value, errp); 387 } 388 389 static void machine_set_phandle_start(Object *obj, Visitor *v, 390 const char *name, void *opaque, 391 Error **errp) 392 { 393 MachineState *ms = MACHINE(obj); 394 int64_t value; 395 396 if (!visit_type_int(v, name, &value, errp)) { 397 return; 398 } 399 400 ms->phandle_start = value; 401 } 402 403 static char *machine_get_dt_compatible(Object *obj, Error **errp) 404 { 405 MachineState *ms = MACHINE(obj); 406 407 return g_strdup(ms->dt_compatible); 408 } 409 410 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 411 { 412 MachineState *ms = MACHINE(obj); 413 414 g_free(ms->dt_compatible); 415 ms->dt_compatible = g_strdup(value); 416 } 417 418 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 419 { 420 MachineState *ms = MACHINE(obj); 421 422 return ms->dump_guest_core; 423 } 424 425 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 426 { 427 MachineState *ms = MACHINE(obj); 428 429 ms->dump_guest_core = value; 430 } 431 432 static bool machine_get_mem_merge(Object *obj, Error **errp) 433 { 434 MachineState *ms = MACHINE(obj); 435 436 return ms->mem_merge; 437 } 438 439 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 440 { 441 MachineState *ms = MACHINE(obj); 442 443 ms->mem_merge = value; 444 } 445 446 static bool machine_get_usb(Object *obj, Error **errp) 447 { 448 MachineState *ms = MACHINE(obj); 449 450 return ms->usb; 451 } 452 453 static void machine_set_usb(Object *obj, bool value, Error **errp) 454 { 455 MachineState *ms = MACHINE(obj); 456 457 ms->usb = value; 458 ms->usb_disabled = !value; 459 } 460 461 static bool machine_get_graphics(Object *obj, Error **errp) 462 { 463 MachineState *ms = MACHINE(obj); 464 465 return ms->enable_graphics; 466 } 467 468 static void machine_set_graphics(Object *obj, bool value, Error **errp) 469 { 470 MachineState *ms = MACHINE(obj); 471 472 ms->enable_graphics = value; 473 } 474 475 static char *machine_get_firmware(Object *obj, Error **errp) 476 { 477 MachineState *ms = MACHINE(obj); 478 479 return g_strdup(ms->firmware); 480 } 481 482 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 483 { 484 MachineState *ms = MACHINE(obj); 485 486 g_free(ms->firmware); 487 ms->firmware = g_strdup(value); 488 } 489 490 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 491 { 492 MachineState *ms = MACHINE(obj); 493 494 ms->suppress_vmdesc = value; 495 } 496 497 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 498 { 499 MachineState *ms = MACHINE(obj); 500 501 return ms->suppress_vmdesc; 502 } 503 504 static char *machine_get_memory_encryption(Object *obj, Error **errp) 505 { 506 MachineState *ms = MACHINE(obj); 507 508 if (ms->cgs) { 509 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 510 } 511 512 return NULL; 513 } 514 515 static void machine_set_memory_encryption(Object *obj, const char *value, 516 Error **errp) 517 { 518 Object *cgs = 519 object_resolve_path_component(object_get_objects_root(), value); 520 521 if (!cgs) { 522 error_setg(errp, "No such memory encryption object '%s'", value); 523 return; 524 } 525 526 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 527 } 528 529 static void machine_check_confidential_guest_support(const Object *obj, 530 const char *name, 531 Object *new_target, 532 Error **errp) 533 { 534 /* 535 * So far the only constraint is that the target has the 536 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 537 * by the QOM core 538 */ 539 } 540 541 static bool machine_get_nvdimm(Object *obj, Error **errp) 542 { 543 MachineState *ms = MACHINE(obj); 544 545 return ms->nvdimms_state->is_enabled; 546 } 547 548 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 549 { 550 MachineState *ms = MACHINE(obj); 551 552 ms->nvdimms_state->is_enabled = value; 553 } 554 555 static bool machine_get_hmat(Object *obj, Error **errp) 556 { 557 MachineState *ms = MACHINE(obj); 558 559 return ms->numa_state->hmat_enabled; 560 } 561 562 static void machine_set_hmat(Object *obj, bool value, Error **errp) 563 { 564 MachineState *ms = MACHINE(obj); 565 566 ms->numa_state->hmat_enabled = value; 567 } 568 569 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 570 void *opaque, Error **errp) 571 { 572 MachineState *ms = MACHINE(obj); 573 MemorySizeConfiguration mem = { 574 .has_size = true, 575 .size = ms->ram_size, 576 .has_max_size = !!ms->ram_slots, 577 .max_size = ms->maxram_size, 578 .has_slots = !!ms->ram_slots, 579 .slots = ms->ram_slots, 580 }; 581 MemorySizeConfiguration *p_mem = &mem; 582 583 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 584 } 585 586 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 587 void *opaque, Error **errp) 588 { 589 ERRP_GUARD(); 590 MachineState *ms = MACHINE(obj); 591 MachineClass *mc = MACHINE_GET_CLASS(obj); 592 MemorySizeConfiguration *mem; 593 594 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 595 return; 596 } 597 598 if (!mem->has_size) { 599 mem->has_size = true; 600 mem->size = mc->default_ram_size; 601 } 602 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 603 if (mc->fixup_ram_size) { 604 mem->size = mc->fixup_ram_size(mem->size); 605 } 606 if ((ram_addr_t)mem->size != mem->size) { 607 error_setg(errp, "ram size too large"); 608 goto out_free; 609 } 610 611 if (mem->has_max_size) { 612 if (mem->max_size < mem->size) { 613 error_setg(errp, "invalid value of maxmem: " 614 "maximum memory size (0x%" PRIx64 ") must be at least " 615 "the initial memory size (0x%" PRIx64 ")", 616 mem->max_size, mem->size); 617 goto out_free; 618 } 619 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 620 error_setg(errp, "invalid value of maxmem: " 621 "memory slots were specified but maximum memory size " 622 "(0x%" PRIx64 ") is equal to the initial memory size " 623 "(0x%" PRIx64 ")", mem->max_size, mem->size); 624 goto out_free; 625 } 626 ms->maxram_size = mem->max_size; 627 } else { 628 if (mem->has_slots) { 629 error_setg(errp, "slots specified but no max-size"); 630 goto out_free; 631 } 632 ms->maxram_size = mem->size; 633 } 634 ms->ram_size = mem->size; 635 ms->ram_slots = mem->has_slots ? mem->slots : 0; 636 out_free: 637 qapi_free_MemorySizeConfiguration(mem); 638 } 639 640 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 641 { 642 MachineState *ms = MACHINE(obj); 643 644 return g_strdup(ms->nvdimms_state->persistence_string); 645 } 646 647 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 648 Error **errp) 649 { 650 MachineState *ms = MACHINE(obj); 651 NVDIMMState *nvdimms_state = ms->nvdimms_state; 652 653 if (strcmp(value, "cpu") == 0) { 654 nvdimms_state->persistence = 3; 655 } else if (strcmp(value, "mem-ctrl") == 0) { 656 nvdimms_state->persistence = 2; 657 } else { 658 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 659 value); 660 return; 661 } 662 663 g_free(nvdimms_state->persistence_string); 664 nvdimms_state->persistence_string = g_strdup(value); 665 } 666 667 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 668 { 669 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 670 } 671 672 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 673 { 674 Object *obj = OBJECT(dev); 675 676 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 677 return false; 678 } 679 680 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 681 } 682 683 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 684 { 685 bool allowed = false; 686 strList *wl; 687 ObjectClass *klass = object_class_by_name(type); 688 689 for (wl = mc->allowed_dynamic_sysbus_devices; 690 !allowed && wl; 691 wl = wl->next) { 692 allowed |= !!object_class_dynamic_cast(klass, wl->value); 693 } 694 695 return allowed; 696 } 697 698 static char *machine_get_audiodev(Object *obj, Error **errp) 699 { 700 MachineState *ms = MACHINE(obj); 701 702 return g_strdup(ms->audiodev); 703 } 704 705 static void machine_set_audiodev(Object *obj, const char *value, 706 Error **errp) 707 { 708 MachineState *ms = MACHINE(obj); 709 710 if (!audio_state_by_name(value, errp)) { 711 return; 712 } 713 714 g_free(ms->audiodev); 715 ms->audiodev = g_strdup(value); 716 } 717 718 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 719 { 720 int i; 721 HotpluggableCPUList *head = NULL; 722 MachineClass *mc = MACHINE_GET_CLASS(machine); 723 724 /* force board to initialize possible_cpus if it hasn't been done yet */ 725 mc->possible_cpu_arch_ids(machine); 726 727 for (i = 0; i < machine->possible_cpus->len; i++) { 728 CPUState *cpu; 729 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 730 731 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 732 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 733 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 734 sizeof(*cpu_item->props)); 735 736 cpu = machine->possible_cpus->cpus[i].cpu; 737 if (cpu) { 738 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 739 } 740 QAPI_LIST_PREPEND(head, cpu_item); 741 } 742 return head; 743 } 744 745 /** 746 * machine_set_cpu_numa_node: 747 * @machine: machine object to modify 748 * @props: specifies which cpu objects to assign to 749 * numa node specified by @props.node_id 750 * @errp: if an error occurs, a pointer to an area to store the error 751 * 752 * Associate NUMA node specified by @props.node_id with cpu slots that 753 * match socket/core/thread-ids specified by @props. It's recommended to use 754 * query-hotpluggable-cpus.props values to specify affected cpu slots, 755 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 756 * 757 * However for CLI convenience it's possible to pass in subset of properties, 758 * which would affect all cpu slots that match it. 759 * Ex for pc machine: 760 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 761 * -numa cpu,node-id=0,socket_id=0 \ 762 * -numa cpu,node-id=1,socket_id=1 763 * will assign all child cores of socket 0 to node 0 and 764 * of socket 1 to node 1. 765 * 766 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 767 * return error. 768 * Empty subset is disallowed and function will return with error in this case. 769 */ 770 void machine_set_cpu_numa_node(MachineState *machine, 771 const CpuInstanceProperties *props, Error **errp) 772 { 773 MachineClass *mc = MACHINE_GET_CLASS(machine); 774 NodeInfo *numa_info = machine->numa_state->nodes; 775 bool match = false; 776 int i; 777 778 if (!mc->possible_cpu_arch_ids) { 779 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 780 return; 781 } 782 783 /* disabling node mapping is not supported, forbid it */ 784 assert(props->has_node_id); 785 786 /* force board to initialize possible_cpus if it hasn't been done yet */ 787 mc->possible_cpu_arch_ids(machine); 788 789 for (i = 0; i < machine->possible_cpus->len; i++) { 790 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 791 792 /* reject unsupported by board properties */ 793 if (props->has_thread_id && !slot->props.has_thread_id) { 794 error_setg(errp, "thread-id is not supported"); 795 return; 796 } 797 798 if (props->has_core_id && !slot->props.has_core_id) { 799 error_setg(errp, "core-id is not supported"); 800 return; 801 } 802 803 if (props->has_cluster_id && !slot->props.has_cluster_id) { 804 error_setg(errp, "cluster-id is not supported"); 805 return; 806 } 807 808 if (props->has_socket_id && !slot->props.has_socket_id) { 809 error_setg(errp, "socket-id is not supported"); 810 return; 811 } 812 813 if (props->has_die_id && !slot->props.has_die_id) { 814 error_setg(errp, "die-id is not supported"); 815 return; 816 } 817 818 /* skip slots with explicit mismatch */ 819 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 820 continue; 821 } 822 823 if (props->has_core_id && props->core_id != slot->props.core_id) { 824 continue; 825 } 826 827 if (props->has_cluster_id && 828 props->cluster_id != slot->props.cluster_id) { 829 continue; 830 } 831 832 if (props->has_die_id && props->die_id != slot->props.die_id) { 833 continue; 834 } 835 836 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 837 continue; 838 } 839 840 /* reject assignment if slot is already assigned, for compatibility 841 * of legacy cpu_index mapping with SPAPR core based mapping do not 842 * error out if cpu thread and matched core have the same node-id */ 843 if (slot->props.has_node_id && 844 slot->props.node_id != props->node_id) { 845 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 846 slot->props.node_id); 847 return; 848 } 849 850 /* assign slot to node as it's matched '-numa cpu' key */ 851 match = true; 852 slot->props.node_id = props->node_id; 853 slot->props.has_node_id = props->has_node_id; 854 855 if (machine->numa_state->hmat_enabled) { 856 if ((numa_info[props->node_id].initiator < MAX_NODES) && 857 (props->node_id != numa_info[props->node_id].initiator)) { 858 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 859 " should be itself (got %" PRIu16 ")", 860 props->node_id, numa_info[props->node_id].initiator); 861 return; 862 } 863 numa_info[props->node_id].has_cpu = true; 864 numa_info[props->node_id].initiator = props->node_id; 865 } 866 } 867 868 if (!match) { 869 error_setg(errp, "no match found"); 870 } 871 } 872 873 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 874 void *opaque, Error **errp) 875 { 876 MachineState *ms = MACHINE(obj); 877 SMPConfiguration *config = &(SMPConfiguration){ 878 .has_cpus = true, .cpus = ms->smp.cpus, 879 .has_drawers = true, .drawers = ms->smp.drawers, 880 .has_books = true, .books = ms->smp.books, 881 .has_sockets = true, .sockets = ms->smp.sockets, 882 .has_dies = true, .dies = ms->smp.dies, 883 .has_clusters = true, .clusters = ms->smp.clusters, 884 .has_modules = true, .modules = ms->smp.modules, 885 .has_cores = true, .cores = ms->smp.cores, 886 .has_threads = true, .threads = ms->smp.threads, 887 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 888 }; 889 890 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 891 return; 892 } 893 } 894 895 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 896 void *opaque, Error **errp) 897 { 898 MachineState *ms = MACHINE(obj); 899 g_autoptr(SMPConfiguration) config = NULL; 900 901 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 902 return; 903 } 904 905 machine_parse_smp_config(ms, config, errp); 906 } 907 908 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 909 void *opaque, Error **errp) 910 { 911 MachineState *ms = MACHINE(obj); 912 BootConfiguration *config = &ms->boot_config; 913 visit_type_BootConfiguration(v, name, &config, &error_abort); 914 } 915 916 static void machine_free_boot_config(MachineState *ms) 917 { 918 g_free(ms->boot_config.order); 919 g_free(ms->boot_config.once); 920 g_free(ms->boot_config.splash); 921 } 922 923 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 924 { 925 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 926 927 machine_free_boot_config(ms); 928 ms->boot_config = *config; 929 if (!config->order) { 930 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 931 } 932 } 933 934 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 935 void *opaque, Error **errp) 936 { 937 ERRP_GUARD(); 938 MachineState *ms = MACHINE(obj); 939 BootConfiguration *config = NULL; 940 941 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 942 return; 943 } 944 if (config->order) { 945 validate_bootdevices(config->order, errp); 946 if (*errp) { 947 goto out_free; 948 } 949 } 950 if (config->once) { 951 validate_bootdevices(config->once, errp); 952 if (*errp) { 953 goto out_free; 954 } 955 } 956 957 machine_copy_boot_config(ms, config); 958 /* Strings live in ms->boot_config. */ 959 free(config); 960 return; 961 962 out_free: 963 qapi_free_BootConfiguration(config); 964 } 965 966 void machine_add_audiodev_property(MachineClass *mc) 967 { 968 ObjectClass *oc = OBJECT_CLASS(mc); 969 970 object_class_property_add_str(oc, "audiodev", 971 machine_get_audiodev, 972 machine_set_audiodev); 973 object_class_property_set_description(oc, "audiodev", 974 "Audiodev to use for default machine devices"); 975 } 976 977 static void machine_class_init(ObjectClass *oc, void *data) 978 { 979 MachineClass *mc = MACHINE_CLASS(oc); 980 981 /* Default 128 MB as guest ram size */ 982 mc->default_ram_size = 128 * MiB; 983 mc->rom_file_has_mr = true; 984 985 /* numa node memory size aligned on 8MB by default. 986 * On Linux, each node's border has to be 8MB aligned 987 */ 988 mc->numa_mem_align_shift = 23; 989 990 object_class_property_add_str(oc, "kernel", 991 machine_get_kernel, machine_set_kernel); 992 object_class_property_set_description(oc, "kernel", 993 "Linux kernel image file"); 994 995 object_class_property_add_str(oc, "initrd", 996 machine_get_initrd, machine_set_initrd); 997 object_class_property_set_description(oc, "initrd", 998 "Linux initial ramdisk file"); 999 1000 object_class_property_add_str(oc, "append", 1001 machine_get_append, machine_set_append); 1002 object_class_property_set_description(oc, "append", 1003 "Linux kernel command line"); 1004 1005 object_class_property_add_str(oc, "dtb", 1006 machine_get_dtb, machine_set_dtb); 1007 object_class_property_set_description(oc, "dtb", 1008 "Linux kernel device tree file"); 1009 1010 object_class_property_add_str(oc, "dumpdtb", 1011 machine_get_dumpdtb, machine_set_dumpdtb); 1012 object_class_property_set_description(oc, "dumpdtb", 1013 "Dump current dtb to a file and quit"); 1014 1015 object_class_property_add(oc, "boot", "BootConfiguration", 1016 machine_get_boot, machine_set_boot, 1017 NULL, NULL); 1018 object_class_property_set_description(oc, "boot", 1019 "Boot configuration"); 1020 1021 object_class_property_add(oc, "smp", "SMPConfiguration", 1022 machine_get_smp, machine_set_smp, 1023 NULL, NULL); 1024 object_class_property_set_description(oc, "smp", 1025 "CPU topology"); 1026 1027 object_class_property_add(oc, "phandle-start", "int", 1028 machine_get_phandle_start, machine_set_phandle_start, 1029 NULL, NULL); 1030 object_class_property_set_description(oc, "phandle-start", 1031 "The first phandle ID we may generate dynamically"); 1032 1033 object_class_property_add_str(oc, "dt-compatible", 1034 machine_get_dt_compatible, machine_set_dt_compatible); 1035 object_class_property_set_description(oc, "dt-compatible", 1036 "Overrides the \"compatible\" property of the dt root node"); 1037 1038 object_class_property_add_bool(oc, "dump-guest-core", 1039 machine_get_dump_guest_core, machine_set_dump_guest_core); 1040 object_class_property_set_description(oc, "dump-guest-core", 1041 "Include guest memory in a core dump"); 1042 1043 object_class_property_add_bool(oc, "mem-merge", 1044 machine_get_mem_merge, machine_set_mem_merge); 1045 object_class_property_set_description(oc, "mem-merge", 1046 "Enable/disable memory merge support"); 1047 1048 object_class_property_add_bool(oc, "usb", 1049 machine_get_usb, machine_set_usb); 1050 object_class_property_set_description(oc, "usb", 1051 "Set on/off to enable/disable usb"); 1052 1053 object_class_property_add_bool(oc, "graphics", 1054 machine_get_graphics, machine_set_graphics); 1055 object_class_property_set_description(oc, "graphics", 1056 "Set on/off to enable/disable graphics emulation"); 1057 1058 object_class_property_add_str(oc, "firmware", 1059 machine_get_firmware, machine_set_firmware); 1060 object_class_property_set_description(oc, "firmware", 1061 "Firmware image"); 1062 1063 object_class_property_add_bool(oc, "suppress-vmdesc", 1064 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1065 object_class_property_set_description(oc, "suppress-vmdesc", 1066 "Set on to disable self-describing migration"); 1067 1068 object_class_property_add_link(oc, "confidential-guest-support", 1069 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1070 offsetof(MachineState, cgs), 1071 machine_check_confidential_guest_support, 1072 OBJ_PROP_LINK_STRONG); 1073 object_class_property_set_description(oc, "confidential-guest-support", 1074 "Set confidential guest scheme to support"); 1075 1076 /* For compatibility */ 1077 object_class_property_add_str(oc, "memory-encryption", 1078 machine_get_memory_encryption, machine_set_memory_encryption); 1079 object_class_property_set_description(oc, "memory-encryption", 1080 "Set memory encryption object to use"); 1081 1082 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1083 offsetof(MachineState, memdev), object_property_allow_set_link, 1084 OBJ_PROP_LINK_STRONG); 1085 object_class_property_set_description(oc, "memory-backend", 1086 "Set RAM backend" 1087 "Valid value is ID of hostmem based backend"); 1088 1089 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1090 machine_get_mem, machine_set_mem, 1091 NULL, NULL); 1092 object_class_property_set_description(oc, "memory", 1093 "Memory size configuration"); 1094 } 1095 1096 static void machine_class_base_init(ObjectClass *oc, void *data) 1097 { 1098 MachineClass *mc = MACHINE_CLASS(oc); 1099 mc->max_cpus = mc->max_cpus ?: 1; 1100 mc->min_cpus = mc->min_cpus ?: 1; 1101 mc->default_cpus = mc->default_cpus ?: 1; 1102 1103 if (!object_class_is_abstract(oc)) { 1104 const char *cname = object_class_get_name(oc); 1105 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1106 mc->name = g_strndup(cname, 1107 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1108 mc->compat_props = g_ptr_array_new(); 1109 } 1110 } 1111 1112 static void machine_initfn(Object *obj) 1113 { 1114 MachineState *ms = MACHINE(obj); 1115 MachineClass *mc = MACHINE_GET_CLASS(obj); 1116 1117 container_get(obj, "/peripheral"); 1118 container_get(obj, "/peripheral-anon"); 1119 1120 ms->dump_guest_core = true; 1121 ms->mem_merge = true; 1122 ms->enable_graphics = true; 1123 ms->kernel_cmdline = g_strdup(""); 1124 ms->ram_size = mc->default_ram_size; 1125 ms->maxram_size = mc->default_ram_size; 1126 1127 if (mc->nvdimm_supported) { 1128 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1129 object_property_add_bool(obj, "nvdimm", 1130 machine_get_nvdimm, machine_set_nvdimm); 1131 object_property_set_description(obj, "nvdimm", 1132 "Set on/off to enable/disable " 1133 "NVDIMM instantiation"); 1134 1135 object_property_add_str(obj, "nvdimm-persistence", 1136 machine_get_nvdimm_persistence, 1137 machine_set_nvdimm_persistence); 1138 object_property_set_description(obj, "nvdimm-persistence", 1139 "Set NVDIMM persistence" 1140 "Valid values are cpu, mem-ctrl"); 1141 } 1142 1143 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1144 ms->numa_state = g_new0(NumaState, 1); 1145 object_property_add_bool(obj, "hmat", 1146 machine_get_hmat, machine_set_hmat); 1147 object_property_set_description(obj, "hmat", 1148 "Set on/off to enable/disable " 1149 "ACPI Heterogeneous Memory Attribute " 1150 "Table (HMAT)"); 1151 } 1152 1153 /* default to mc->default_cpus */ 1154 ms->smp.cpus = mc->default_cpus; 1155 ms->smp.max_cpus = mc->default_cpus; 1156 ms->smp.drawers = 1; 1157 ms->smp.books = 1; 1158 ms->smp.sockets = 1; 1159 ms->smp.dies = 1; 1160 ms->smp.clusters = 1; 1161 ms->smp.modules = 1; 1162 ms->smp.cores = 1; 1163 ms->smp.threads = 1; 1164 1165 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1166 } 1167 1168 static void machine_finalize(Object *obj) 1169 { 1170 MachineState *ms = MACHINE(obj); 1171 1172 machine_free_boot_config(ms); 1173 g_free(ms->kernel_filename); 1174 g_free(ms->initrd_filename); 1175 g_free(ms->kernel_cmdline); 1176 g_free(ms->dtb); 1177 g_free(ms->dumpdtb); 1178 g_free(ms->dt_compatible); 1179 g_free(ms->firmware); 1180 g_free(ms->device_memory); 1181 g_free(ms->nvdimms_state); 1182 g_free(ms->numa_state); 1183 g_free(ms->audiodev); 1184 } 1185 1186 bool machine_usb(MachineState *machine) 1187 { 1188 return machine->usb; 1189 } 1190 1191 int machine_phandle_start(MachineState *machine) 1192 { 1193 return machine->phandle_start; 1194 } 1195 1196 bool machine_dump_guest_core(MachineState *machine) 1197 { 1198 return machine->dump_guest_core; 1199 } 1200 1201 bool machine_mem_merge(MachineState *machine) 1202 { 1203 return machine->mem_merge; 1204 } 1205 1206 bool machine_require_guest_memfd(MachineState *machine) 1207 { 1208 return machine->require_guest_memfd; 1209 } 1210 1211 static char *cpu_slot_to_string(const CPUArchId *cpu) 1212 { 1213 GString *s = g_string_new(NULL); 1214 if (cpu->props.has_socket_id) { 1215 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1216 } 1217 if (cpu->props.has_die_id) { 1218 if (s->len) { 1219 g_string_append_printf(s, ", "); 1220 } 1221 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1222 } 1223 if (cpu->props.has_cluster_id) { 1224 if (s->len) { 1225 g_string_append_printf(s, ", "); 1226 } 1227 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1228 } 1229 if (cpu->props.has_core_id) { 1230 if (s->len) { 1231 g_string_append_printf(s, ", "); 1232 } 1233 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1234 } 1235 if (cpu->props.has_thread_id) { 1236 if (s->len) { 1237 g_string_append_printf(s, ", "); 1238 } 1239 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1240 } 1241 return g_string_free(s, false); 1242 } 1243 1244 static void numa_validate_initiator(NumaState *numa_state) 1245 { 1246 int i; 1247 NodeInfo *numa_info = numa_state->nodes; 1248 1249 for (i = 0; i < numa_state->num_nodes; i++) { 1250 if (numa_info[i].initiator == MAX_NODES) { 1251 continue; 1252 } 1253 1254 if (!numa_info[numa_info[i].initiator].present) { 1255 error_report("NUMA node %" PRIu16 " is missing, use " 1256 "'-numa node' option to declare it first", 1257 numa_info[i].initiator); 1258 exit(1); 1259 } 1260 1261 if (!numa_info[numa_info[i].initiator].has_cpu) { 1262 error_report("The initiator of NUMA node %d is invalid", i); 1263 exit(1); 1264 } 1265 } 1266 } 1267 1268 static void machine_numa_finish_cpu_init(MachineState *machine) 1269 { 1270 int i; 1271 bool default_mapping; 1272 GString *s = g_string_new(NULL); 1273 MachineClass *mc = MACHINE_GET_CLASS(machine); 1274 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1275 1276 assert(machine->numa_state->num_nodes); 1277 for (i = 0; i < possible_cpus->len; i++) { 1278 if (possible_cpus->cpus[i].props.has_node_id) { 1279 break; 1280 } 1281 } 1282 default_mapping = (i == possible_cpus->len); 1283 1284 for (i = 0; i < possible_cpus->len; i++) { 1285 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1286 1287 if (!cpu_slot->props.has_node_id) { 1288 /* fetch default mapping from board and enable it */ 1289 CpuInstanceProperties props = cpu_slot->props; 1290 1291 props.node_id = mc->get_default_cpu_node_id(machine, i); 1292 if (!default_mapping) { 1293 /* record slots with not set mapping, 1294 * TODO: make it hard error in future */ 1295 char *cpu_str = cpu_slot_to_string(cpu_slot); 1296 g_string_append_printf(s, "%sCPU %d [%s]", 1297 s->len ? ", " : "", i, cpu_str); 1298 g_free(cpu_str); 1299 1300 /* non mapped cpus used to fallback to node 0 */ 1301 props.node_id = 0; 1302 } 1303 1304 props.has_node_id = true; 1305 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1306 } 1307 } 1308 1309 if (machine->numa_state->hmat_enabled) { 1310 numa_validate_initiator(machine->numa_state); 1311 } 1312 1313 if (s->len && !qtest_enabled()) { 1314 warn_report("CPU(s) not present in any NUMA nodes: %s", 1315 s->str); 1316 warn_report("All CPU(s) up to maxcpus should be described " 1317 "in NUMA config, ability to start up with partial NUMA " 1318 "mappings is obsoleted and will be removed in future"); 1319 } 1320 g_string_free(s, true); 1321 } 1322 1323 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1324 { 1325 MachineClass *mc = MACHINE_GET_CLASS(ms); 1326 NumaState *state = ms->numa_state; 1327 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1328 const CPUArchId *cpus = possible_cpus->cpus; 1329 int i, j; 1330 1331 if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) { 1332 return; 1333 } 1334 1335 /* 1336 * The Linux scheduling domain can't be parsed when the multiple CPUs 1337 * in one cluster have been associated with different NUMA nodes. However, 1338 * it's fine to associate one NUMA node with CPUs in different clusters. 1339 */ 1340 for (i = 0; i < possible_cpus->len; i++) { 1341 for (j = i + 1; j < possible_cpus->len; j++) { 1342 if (cpus[i].props.has_socket_id && 1343 cpus[i].props.has_cluster_id && 1344 cpus[i].props.has_node_id && 1345 cpus[j].props.has_socket_id && 1346 cpus[j].props.has_cluster_id && 1347 cpus[j].props.has_node_id && 1348 cpus[i].props.socket_id == cpus[j].props.socket_id && 1349 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1350 cpus[i].props.node_id != cpus[j].props.node_id) { 1351 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1352 " have been associated with node-%" PRId64 " and node-%" PRId64 1353 " respectively. It can cause OSes like Linux to" 1354 " misbehave", i, j, cpus[i].props.socket_id, 1355 cpus[i].props.cluster_id, cpus[i].props.node_id, 1356 cpus[j].props.node_id); 1357 } 1358 } 1359 } 1360 } 1361 1362 MemoryRegion *machine_consume_memdev(MachineState *machine, 1363 HostMemoryBackend *backend) 1364 { 1365 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1366 1367 if (host_memory_backend_is_mapped(backend)) { 1368 error_report("memory backend %s can't be used multiple times.", 1369 object_get_canonical_path_component(OBJECT(backend))); 1370 exit(EXIT_FAILURE); 1371 } 1372 host_memory_backend_set_mapped(backend, true); 1373 vmstate_register_ram_global(ret); 1374 return ret; 1375 } 1376 1377 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1378 { 1379 Object *obj; 1380 MachineClass *mc = MACHINE_GET_CLASS(ms); 1381 bool r = false; 1382 1383 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1384 if (path) { 1385 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1386 goto out; 1387 } 1388 } 1389 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1390 goto out; 1391 } 1392 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1393 obj); 1394 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1395 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1396 false, errp)) { 1397 goto out; 1398 } 1399 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1400 goto out; 1401 } 1402 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1403 1404 out: 1405 object_unref(obj); 1406 return r; 1407 } 1408 1409 const char *machine_class_default_cpu_type(MachineClass *mc) 1410 { 1411 if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) { 1412 /* Only a single CPU type allowed: use it as default. */ 1413 return mc->valid_cpu_types[0]; 1414 } 1415 return mc->default_cpu_type; 1416 } 1417 1418 static bool is_cpu_type_supported(const MachineState *machine, Error **errp) 1419 { 1420 MachineClass *mc = MACHINE_GET_CLASS(machine); 1421 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1422 CPUClass *cc; 1423 int i; 1424 1425 /* 1426 * Check if the user specified CPU type is supported when the valid 1427 * CPU types have been determined. Note that the user specified CPU 1428 * type is provided through '-cpu' option. 1429 */ 1430 if (mc->valid_cpu_types) { 1431 assert(mc->valid_cpu_types[0] != NULL); 1432 for (i = 0; mc->valid_cpu_types[i]; i++) { 1433 if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { 1434 break; 1435 } 1436 } 1437 1438 /* The user specified CPU type isn't valid */ 1439 if (!mc->valid_cpu_types[i]) { 1440 g_autofree char *requested = cpu_model_from_type(machine->cpu_type); 1441 error_setg(errp, "Invalid CPU model: %s", requested); 1442 if (!mc->valid_cpu_types[1]) { 1443 g_autofree char *model = cpu_model_from_type( 1444 mc->valid_cpu_types[0]); 1445 error_append_hint(errp, "The only valid type is: %s\n", model); 1446 } else { 1447 error_append_hint(errp, "The valid models are: "); 1448 for (i = 0; mc->valid_cpu_types[i]; i++) { 1449 g_autofree char *model = cpu_model_from_type( 1450 mc->valid_cpu_types[i]); 1451 error_append_hint(errp, "%s%s", 1452 model, 1453 mc->valid_cpu_types[i + 1] ? ", " : ""); 1454 } 1455 error_append_hint(errp, "\n"); 1456 } 1457 1458 return false; 1459 } 1460 } 1461 1462 /* Check if CPU type is deprecated and warn if so */ 1463 cc = CPU_CLASS(oc); 1464 assert(cc != NULL); 1465 if (cc->deprecation_note) { 1466 warn_report("CPU model %s is deprecated -- %s", 1467 machine->cpu_type, cc->deprecation_note); 1468 } 1469 1470 return true; 1471 } 1472 1473 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1474 { 1475 ERRP_GUARD(); 1476 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1477 1478 /* This checkpoint is required by replay to separate prior clock 1479 reading from the other reads, because timer polling functions query 1480 clock values from the log. */ 1481 replay_checkpoint(CHECKPOINT_INIT); 1482 1483 if (!xen_enabled()) { 1484 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1485 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1486 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1487 return; 1488 } 1489 } 1490 1491 if (machine->memdev) { 1492 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1493 "size", &error_abort); 1494 if (backend_size != machine->ram_size) { 1495 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1496 return; 1497 } 1498 } else if (machine_class->default_ram_id && machine->ram_size && 1499 numa_uses_legacy_mem()) { 1500 if (object_property_find(object_get_objects_root(), 1501 machine_class->default_ram_id)) { 1502 error_setg(errp, "object's id '%s' is reserved for the default" 1503 " RAM backend, it can't be used for any other purposes", 1504 machine_class->default_ram_id); 1505 error_append_hint(errp, 1506 "Change the object's 'id' to something else or disable" 1507 " automatic creation of the default RAM backend by setting" 1508 " 'memory-backend=%s' with '-machine'.\n", 1509 machine_class->default_ram_id); 1510 return; 1511 } 1512 if (!create_default_memdev(current_machine, mem_path, errp)) { 1513 return; 1514 } 1515 } 1516 1517 if (machine->numa_state) { 1518 numa_complete_configuration(machine); 1519 if (machine->numa_state->num_nodes) { 1520 machine_numa_finish_cpu_init(machine); 1521 if (machine_class->cpu_cluster_has_numa_boundary) { 1522 validate_cpu_cluster_to_numa_boundary(machine); 1523 } 1524 } 1525 } 1526 1527 if (!machine->ram && machine->memdev) { 1528 machine->ram = machine_consume_memdev(machine, machine->memdev); 1529 } 1530 1531 /* Check if the CPU type is supported */ 1532 if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) { 1533 return; 1534 } 1535 1536 if (machine->cgs) { 1537 /* 1538 * With confidential guests, the host can't see the real 1539 * contents of RAM, so there's no point in it trying to merge 1540 * areas. 1541 */ 1542 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1543 1544 /* 1545 * Virtio devices can't count on directly accessing guest 1546 * memory, so they need iommu_platform=on to use normal DMA 1547 * mechanisms. That requires also disabling legacy virtio 1548 * support for those virtio pci devices which allow it. 1549 */ 1550 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1551 "on", true); 1552 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1553 "on", false); 1554 } 1555 1556 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1557 machine_class->init(machine); 1558 phase_advance(PHASE_MACHINE_INITIALIZED); 1559 } 1560 1561 static NotifierList machine_init_done_notifiers = 1562 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1563 1564 void qemu_add_machine_init_done_notifier(Notifier *notify) 1565 { 1566 notifier_list_add(&machine_init_done_notifiers, notify); 1567 if (phase_check(PHASE_MACHINE_READY)) { 1568 notify->notify(notify, NULL); 1569 } 1570 } 1571 1572 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1573 { 1574 notifier_remove(notify); 1575 } 1576 1577 void qdev_machine_creation_done(void) 1578 { 1579 cpu_synchronize_all_post_init(); 1580 1581 if (current_machine->boot_config.once) { 1582 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1583 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1584 } 1585 1586 /* 1587 * ok, initial machine setup is done, starting from now we can 1588 * only create hotpluggable devices 1589 */ 1590 phase_advance(PHASE_MACHINE_READY); 1591 qdev_assert_realized_properly(); 1592 1593 /* TODO: once all bus devices are qdevified, this should be done 1594 * when bus is created by qdev.c */ 1595 /* 1596 * This is where we arrange for the sysbus to be reset when the 1597 * whole simulation is reset. In turn, resetting the sysbus will cause 1598 * all devices hanging off it (and all their child buses, recursively) 1599 * to be reset. Note that this will *not* reset any Device objects 1600 * which are not attached to some part of the qbus tree! 1601 */ 1602 qemu_register_resettable(OBJECT(sysbus_get_default())); 1603 1604 notifier_list_notify(&machine_init_done_notifiers, NULL); 1605 1606 if (rom_check_and_register_reset() != 0) { 1607 exit(1); 1608 } 1609 1610 replay_start(); 1611 1612 /* This checkpoint is required by replay to separate prior clock 1613 reading from the other reads, because timer polling functions query 1614 clock values from the log. */ 1615 replay_checkpoint(CHECKPOINT_RESET); 1616 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1617 register_global_state(); 1618 } 1619 1620 static const TypeInfo machine_info = { 1621 .name = TYPE_MACHINE, 1622 .parent = TYPE_OBJECT, 1623 .abstract = true, 1624 .class_size = sizeof(MachineClass), 1625 .class_init = machine_class_init, 1626 .class_base_init = machine_class_base_init, 1627 .instance_size = sizeof(MachineState), 1628 .instance_init = machine_initfn, 1629 .instance_finalize = machine_finalize, 1630 }; 1631 1632 static void machine_register_types(void) 1633 { 1634 type_register_static(&machine_info); 1635 } 1636 1637 type_init(machine_register_types) 1638