1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/option.h" 15 #include "qapi/qmp/qerror.h" 16 #include "sysemu/replay.h" 17 #include "qemu/units.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-common.h" 22 #include "qapi/visitor.h" 23 #include "hw/sysbus.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/numa.h" 29 #include "qemu/error-report.h" 30 #include "sysemu/qtest.h" 31 #include "hw/pci/pci.h" 32 #include "hw/mem/nvdimm.h" 33 #include "migration/global_state.h" 34 #include "migration/vmstate.h" 35 #include "exec/confidential-guest-support.h" 36 #include "hw/virtio/virtio.h" 37 #include "hw/virtio/virtio-pci.h" 38 39 GlobalProperty hw_compat_6_0[] = { 40 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 41 { "i8042", "extended-state", "false"}, 42 }; 43 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 44 45 GlobalProperty hw_compat_5_2[] = { 46 { "ICH9-LPC", "smm-compat", "on"}, 47 { "PIIX4_PM", "smm-compat", "on"}, 48 { "virtio-blk-device", "report-discard-granularity", "off" }, 49 { "virtio-net-pci", "vectors", "3"}, 50 }; 51 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 52 53 GlobalProperty hw_compat_5_1[] = { 54 { "vhost-scsi", "num_queues", "1"}, 55 { "vhost-user-blk", "num-queues", "1"}, 56 { "vhost-user-scsi", "num_queues", "1"}, 57 { "virtio-blk-device", "num-queues", "1"}, 58 { "virtio-scsi-device", "num_queues", "1"}, 59 { "nvme", "use-intel-id", "on"}, 60 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 61 { "pl011", "migrate-clk", "off" }, 62 { "virtio-pci", "x-ats-page-aligned", "off"}, 63 }; 64 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 65 66 GlobalProperty hw_compat_5_0[] = { 67 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 68 { "virtio-balloon-device", "page-poison", "false" }, 69 { "vmport", "x-read-set-eax", "off" }, 70 { "vmport", "x-signal-unsupported-cmd", "off" }, 71 { "vmport", "x-report-vmx-type", "off" }, 72 { "vmport", "x-cmds-v2", "off" }, 73 { "virtio-device", "x-disable-legacy-check", "true" }, 74 }; 75 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 76 77 GlobalProperty hw_compat_4_2[] = { 78 { "virtio-blk-device", "queue-size", "128"}, 79 { "virtio-scsi-device", "virtqueue_size", "128"}, 80 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 81 { "virtio-blk-device", "seg-max-adjust", "off"}, 82 { "virtio-scsi-device", "seg_max_adjust", "off"}, 83 { "vhost-blk-device", "seg_max_adjust", "off"}, 84 { "usb-host", "suppress-remote-wake", "off" }, 85 { "usb-redir", "suppress-remote-wake", "off" }, 86 { "qxl", "revision", "4" }, 87 { "qxl-vga", "revision", "4" }, 88 { "fw_cfg", "acpi-mr-restore", "false" }, 89 { "virtio-device", "use-disabled-flag", "false" }, 90 }; 91 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 92 93 GlobalProperty hw_compat_4_1[] = { 94 { "virtio-pci", "x-pcie-flr-init", "off" }, 95 }; 96 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 97 98 GlobalProperty hw_compat_4_0[] = { 99 { "VGA", "edid", "false" }, 100 { "secondary-vga", "edid", "false" }, 101 { "bochs-display", "edid", "false" }, 102 { "virtio-vga", "edid", "false" }, 103 { "virtio-gpu-device", "edid", "false" }, 104 { "virtio-device", "use-started", "false" }, 105 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 106 { "pl031", "migrate-tick-offset", "false" }, 107 }; 108 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 109 110 GlobalProperty hw_compat_3_1[] = { 111 { "pcie-root-port", "x-speed", "2_5" }, 112 { "pcie-root-port", "x-width", "1" }, 113 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 114 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 115 { "tpm-crb", "ppi", "false" }, 116 { "tpm-tis", "ppi", "false" }, 117 { "usb-kbd", "serial", "42" }, 118 { "usb-mouse", "serial", "42" }, 119 { "usb-tablet", "serial", "42" }, 120 { "virtio-blk-device", "discard", "false" }, 121 { "virtio-blk-device", "write-zeroes", "false" }, 122 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 123 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 124 }; 125 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 126 127 GlobalProperty hw_compat_3_0[] = {}; 128 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 129 130 GlobalProperty hw_compat_2_12[] = { 131 { "migration", "decompress-error-check", "off" }, 132 { "hda-audio", "use-timer", "false" }, 133 { "cirrus-vga", "global-vmstate", "true" }, 134 { "VGA", "global-vmstate", "true" }, 135 { "vmware-svga", "global-vmstate", "true" }, 136 { "qxl-vga", "global-vmstate", "true" }, 137 }; 138 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 139 140 GlobalProperty hw_compat_2_11[] = { 141 { "hpet", "hpet-offset-saved", "false" }, 142 { "virtio-blk-pci", "vectors", "2" }, 143 { "vhost-user-blk-pci", "vectors", "2" }, 144 { "e1000", "migrate_tso_props", "off" }, 145 }; 146 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 147 148 GlobalProperty hw_compat_2_10[] = { 149 { "virtio-mouse-device", "wheel-axis", "false" }, 150 { "virtio-tablet-device", "wheel-axis", "false" }, 151 }; 152 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 153 154 GlobalProperty hw_compat_2_9[] = { 155 { "pci-bridge", "shpc", "off" }, 156 { "intel-iommu", "pt", "off" }, 157 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 158 { "pcie-root-port", "x-migrate-msix", "false" }, 159 }; 160 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 161 162 GlobalProperty hw_compat_2_8[] = { 163 { "fw_cfg_mem", "x-file-slots", "0x10" }, 164 { "fw_cfg_io", "x-file-slots", "0x10" }, 165 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 166 { "pci-bridge", "shpc", "on" }, 167 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 168 { "virtio-pci", "x-pcie-deverr-init", "off" }, 169 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 170 { "virtio-pci", "x-pcie-pm-init", "off" }, 171 { "cirrus-vga", "vgamem_mb", "8" }, 172 { "isa-cirrus-vga", "vgamem_mb", "8" }, 173 }; 174 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 175 176 GlobalProperty hw_compat_2_7[] = { 177 { "virtio-pci", "page-per-vq", "on" }, 178 { "virtio-serial-device", "emergency-write", "off" }, 179 { "ioapic", "version", "0x11" }, 180 { "intel-iommu", "x-buggy-eim", "true" }, 181 { "virtio-pci", "x-ignore-backend-features", "on" }, 182 }; 183 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 184 185 GlobalProperty hw_compat_2_6[] = { 186 { "virtio-mmio", "format_transport_address", "off" }, 187 /* Optional because not all virtio-pci devices support legacy mode */ 188 { "virtio-pci", "disable-modern", "on", .optional = true }, 189 { "virtio-pci", "disable-legacy", "off", .optional = true }, 190 }; 191 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 192 193 GlobalProperty hw_compat_2_5[] = { 194 { "isa-fdc", "fallback", "144" }, 195 { "pvscsi", "x-old-pci-configuration", "on" }, 196 { "pvscsi", "x-disable-pcie", "on" }, 197 { "vmxnet3", "x-old-msi-offsets", "on" }, 198 { "vmxnet3", "x-disable-pcie", "on" }, 199 }; 200 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 201 202 GlobalProperty hw_compat_2_4[] = { 203 /* Optional because the 'scsi' property is Linux-only */ 204 { "virtio-blk-device", "scsi", "true", .optional = true }, 205 { "e1000", "extra_mac_registers", "off" }, 206 { "virtio-pci", "x-disable-pcie", "on" }, 207 { "virtio-pci", "migrate-extra", "off" }, 208 { "fw_cfg_mem", "dma_enabled", "off" }, 209 { "fw_cfg_io", "dma_enabled", "off" } 210 }; 211 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 212 213 GlobalProperty hw_compat_2_3[] = { 214 { "virtio-blk-pci", "any_layout", "off" }, 215 { "virtio-balloon-pci", "any_layout", "off" }, 216 { "virtio-serial-pci", "any_layout", "off" }, 217 { "virtio-9p-pci", "any_layout", "off" }, 218 { "virtio-rng-pci", "any_layout", "off" }, 219 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 220 { "migration", "send-configuration", "off" }, 221 { "migration", "send-section-footer", "off" }, 222 { "migration", "store-global-state", "off" }, 223 }; 224 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 225 226 GlobalProperty hw_compat_2_2[] = {}; 227 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 228 229 GlobalProperty hw_compat_2_1[] = { 230 { "intel-hda", "old_msi_addr", "on" }, 231 { "VGA", "qemu-extended-regs", "off" }, 232 { "secondary-vga", "qemu-extended-regs", "off" }, 233 { "virtio-scsi-pci", "any_layout", "off" }, 234 { "usb-mouse", "usb_version", "1" }, 235 { "usb-kbd", "usb_version", "1" }, 236 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 237 }; 238 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 239 240 MachineState *current_machine; 241 242 static char *machine_get_kernel(Object *obj, Error **errp) 243 { 244 MachineState *ms = MACHINE(obj); 245 246 return g_strdup(ms->kernel_filename); 247 } 248 249 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 250 { 251 MachineState *ms = MACHINE(obj); 252 253 g_free(ms->kernel_filename); 254 ms->kernel_filename = g_strdup(value); 255 } 256 257 static char *machine_get_initrd(Object *obj, Error **errp) 258 { 259 MachineState *ms = MACHINE(obj); 260 261 return g_strdup(ms->initrd_filename); 262 } 263 264 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 265 { 266 MachineState *ms = MACHINE(obj); 267 268 g_free(ms->initrd_filename); 269 ms->initrd_filename = g_strdup(value); 270 } 271 272 static char *machine_get_append(Object *obj, Error **errp) 273 { 274 MachineState *ms = MACHINE(obj); 275 276 return g_strdup(ms->kernel_cmdline); 277 } 278 279 static void machine_set_append(Object *obj, const char *value, Error **errp) 280 { 281 MachineState *ms = MACHINE(obj); 282 283 g_free(ms->kernel_cmdline); 284 ms->kernel_cmdline = g_strdup(value); 285 } 286 287 static char *machine_get_dtb(Object *obj, Error **errp) 288 { 289 MachineState *ms = MACHINE(obj); 290 291 return g_strdup(ms->dtb); 292 } 293 294 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 295 { 296 MachineState *ms = MACHINE(obj); 297 298 g_free(ms->dtb); 299 ms->dtb = g_strdup(value); 300 } 301 302 static char *machine_get_dumpdtb(Object *obj, Error **errp) 303 { 304 MachineState *ms = MACHINE(obj); 305 306 return g_strdup(ms->dumpdtb); 307 } 308 309 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 310 { 311 MachineState *ms = MACHINE(obj); 312 313 g_free(ms->dumpdtb); 314 ms->dumpdtb = g_strdup(value); 315 } 316 317 static void machine_get_phandle_start(Object *obj, Visitor *v, 318 const char *name, void *opaque, 319 Error **errp) 320 { 321 MachineState *ms = MACHINE(obj); 322 int64_t value = ms->phandle_start; 323 324 visit_type_int(v, name, &value, errp); 325 } 326 327 static void machine_set_phandle_start(Object *obj, Visitor *v, 328 const char *name, void *opaque, 329 Error **errp) 330 { 331 MachineState *ms = MACHINE(obj); 332 int64_t value; 333 334 if (!visit_type_int(v, name, &value, errp)) { 335 return; 336 } 337 338 ms->phandle_start = value; 339 } 340 341 static char *machine_get_dt_compatible(Object *obj, Error **errp) 342 { 343 MachineState *ms = MACHINE(obj); 344 345 return g_strdup(ms->dt_compatible); 346 } 347 348 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 349 { 350 MachineState *ms = MACHINE(obj); 351 352 g_free(ms->dt_compatible); 353 ms->dt_compatible = g_strdup(value); 354 } 355 356 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 357 { 358 MachineState *ms = MACHINE(obj); 359 360 return ms->dump_guest_core; 361 } 362 363 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 364 { 365 MachineState *ms = MACHINE(obj); 366 367 ms->dump_guest_core = value; 368 } 369 370 static bool machine_get_mem_merge(Object *obj, Error **errp) 371 { 372 MachineState *ms = MACHINE(obj); 373 374 return ms->mem_merge; 375 } 376 377 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 378 { 379 MachineState *ms = MACHINE(obj); 380 381 ms->mem_merge = value; 382 } 383 384 static bool machine_get_usb(Object *obj, Error **errp) 385 { 386 MachineState *ms = MACHINE(obj); 387 388 return ms->usb; 389 } 390 391 static void machine_set_usb(Object *obj, bool value, Error **errp) 392 { 393 MachineState *ms = MACHINE(obj); 394 395 ms->usb = value; 396 ms->usb_disabled = !value; 397 } 398 399 static bool machine_get_graphics(Object *obj, Error **errp) 400 { 401 MachineState *ms = MACHINE(obj); 402 403 return ms->enable_graphics; 404 } 405 406 static void machine_set_graphics(Object *obj, bool value, Error **errp) 407 { 408 MachineState *ms = MACHINE(obj); 409 410 ms->enable_graphics = value; 411 } 412 413 static char *machine_get_firmware(Object *obj, Error **errp) 414 { 415 MachineState *ms = MACHINE(obj); 416 417 return g_strdup(ms->firmware); 418 } 419 420 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 421 { 422 MachineState *ms = MACHINE(obj); 423 424 g_free(ms->firmware); 425 ms->firmware = g_strdup(value); 426 } 427 428 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 429 { 430 MachineState *ms = MACHINE(obj); 431 432 ms->suppress_vmdesc = value; 433 } 434 435 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 436 { 437 MachineState *ms = MACHINE(obj); 438 439 return ms->suppress_vmdesc; 440 } 441 442 static char *machine_get_memory_encryption(Object *obj, Error **errp) 443 { 444 MachineState *ms = MACHINE(obj); 445 446 if (ms->cgs) { 447 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 448 } 449 450 return NULL; 451 } 452 453 static void machine_set_memory_encryption(Object *obj, const char *value, 454 Error **errp) 455 { 456 Object *cgs = 457 object_resolve_path_component(object_get_objects_root(), value); 458 459 if (!cgs) { 460 error_setg(errp, "No such memory encryption object '%s'", value); 461 return; 462 } 463 464 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 465 } 466 467 static void machine_check_confidential_guest_support(const Object *obj, 468 const char *name, 469 Object *new_target, 470 Error **errp) 471 { 472 /* 473 * So far the only constraint is that the target has the 474 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 475 * by the QOM core 476 */ 477 } 478 479 static bool machine_get_nvdimm(Object *obj, Error **errp) 480 { 481 MachineState *ms = MACHINE(obj); 482 483 return ms->nvdimms_state->is_enabled; 484 } 485 486 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 487 { 488 MachineState *ms = MACHINE(obj); 489 490 ms->nvdimms_state->is_enabled = value; 491 } 492 493 static bool machine_get_hmat(Object *obj, Error **errp) 494 { 495 MachineState *ms = MACHINE(obj); 496 497 return ms->numa_state->hmat_enabled; 498 } 499 500 static void machine_set_hmat(Object *obj, bool value, Error **errp) 501 { 502 MachineState *ms = MACHINE(obj); 503 504 ms->numa_state->hmat_enabled = value; 505 } 506 507 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 508 { 509 MachineState *ms = MACHINE(obj); 510 511 return g_strdup(ms->nvdimms_state->persistence_string); 512 } 513 514 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 515 Error **errp) 516 { 517 MachineState *ms = MACHINE(obj); 518 NVDIMMState *nvdimms_state = ms->nvdimms_state; 519 520 if (strcmp(value, "cpu") == 0) { 521 nvdimms_state->persistence = 3; 522 } else if (strcmp(value, "mem-ctrl") == 0) { 523 nvdimms_state->persistence = 2; 524 } else { 525 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 526 value); 527 return; 528 } 529 530 g_free(nvdimms_state->persistence_string); 531 nvdimms_state->persistence_string = g_strdup(value); 532 } 533 534 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 535 { 536 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 537 } 538 539 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 540 { 541 bool allowed = false; 542 strList *wl; 543 Object *obj = OBJECT(dev); 544 545 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 546 return false; 547 } 548 549 for (wl = mc->allowed_dynamic_sysbus_devices; 550 !allowed && wl; 551 wl = wl->next) { 552 allowed |= !!object_dynamic_cast(obj, wl->value); 553 } 554 555 return allowed; 556 } 557 558 static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) 559 { 560 MachineState *machine = opaque; 561 MachineClass *mc = MACHINE_GET_CLASS(machine); 562 563 if (!device_is_dynamic_sysbus(mc, DEVICE(sbdev))) { 564 error_report("Option '-device %s' cannot be handled by this machine", 565 object_class_get_name(object_get_class(OBJECT(sbdev)))); 566 exit(1); 567 } 568 } 569 570 static char *machine_get_memdev(Object *obj, Error **errp) 571 { 572 MachineState *ms = MACHINE(obj); 573 574 return g_strdup(ms->ram_memdev_id); 575 } 576 577 static void machine_set_memdev(Object *obj, const char *value, Error **errp) 578 { 579 MachineState *ms = MACHINE(obj); 580 581 g_free(ms->ram_memdev_id); 582 ms->ram_memdev_id = g_strdup(value); 583 } 584 585 586 static void machine_init_notify(Notifier *notifier, void *data) 587 { 588 MachineState *machine = MACHINE(qdev_get_machine()); 589 590 /* 591 * Loop through all dynamically created sysbus devices and check if they are 592 * all allowed. If a device is not allowed, error out. 593 */ 594 foreach_dynamic_sysbus_device(validate_sysbus_device, machine); 595 } 596 597 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 598 { 599 int i; 600 HotpluggableCPUList *head = NULL; 601 MachineClass *mc = MACHINE_GET_CLASS(machine); 602 603 /* force board to initialize possible_cpus if it hasn't been done yet */ 604 mc->possible_cpu_arch_ids(machine); 605 606 for (i = 0; i < machine->possible_cpus->len; i++) { 607 Object *cpu; 608 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 609 610 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 611 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 612 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 613 sizeof(*cpu_item->props)); 614 615 cpu = machine->possible_cpus->cpus[i].cpu; 616 if (cpu) { 617 cpu_item->has_qom_path = true; 618 cpu_item->qom_path = object_get_canonical_path(cpu); 619 } 620 QAPI_LIST_PREPEND(head, cpu_item); 621 } 622 return head; 623 } 624 625 /** 626 * machine_set_cpu_numa_node: 627 * @machine: machine object to modify 628 * @props: specifies which cpu objects to assign to 629 * numa node specified by @props.node_id 630 * @errp: if an error occurs, a pointer to an area to store the error 631 * 632 * Associate NUMA node specified by @props.node_id with cpu slots that 633 * match socket/core/thread-ids specified by @props. It's recommended to use 634 * query-hotpluggable-cpus.props values to specify affected cpu slots, 635 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 636 * 637 * However for CLI convenience it's possible to pass in subset of properties, 638 * which would affect all cpu slots that match it. 639 * Ex for pc machine: 640 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 641 * -numa cpu,node-id=0,socket_id=0 \ 642 * -numa cpu,node-id=1,socket_id=1 643 * will assign all child cores of socket 0 to node 0 and 644 * of socket 1 to node 1. 645 * 646 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 647 * return error. 648 * Empty subset is disallowed and function will return with error in this case. 649 */ 650 void machine_set_cpu_numa_node(MachineState *machine, 651 const CpuInstanceProperties *props, Error **errp) 652 { 653 MachineClass *mc = MACHINE_GET_CLASS(machine); 654 NodeInfo *numa_info = machine->numa_state->nodes; 655 bool match = false; 656 int i; 657 658 if (!mc->possible_cpu_arch_ids) { 659 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 660 return; 661 } 662 663 /* disabling node mapping is not supported, forbid it */ 664 assert(props->has_node_id); 665 666 /* force board to initialize possible_cpus if it hasn't been done yet */ 667 mc->possible_cpu_arch_ids(machine); 668 669 for (i = 0; i < machine->possible_cpus->len; i++) { 670 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 671 672 /* reject unsupported by board properties */ 673 if (props->has_thread_id && !slot->props.has_thread_id) { 674 error_setg(errp, "thread-id is not supported"); 675 return; 676 } 677 678 if (props->has_core_id && !slot->props.has_core_id) { 679 error_setg(errp, "core-id is not supported"); 680 return; 681 } 682 683 if (props->has_socket_id && !slot->props.has_socket_id) { 684 error_setg(errp, "socket-id is not supported"); 685 return; 686 } 687 688 if (props->has_die_id && !slot->props.has_die_id) { 689 error_setg(errp, "die-id is not supported"); 690 return; 691 } 692 693 /* skip slots with explicit mismatch */ 694 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 695 continue; 696 } 697 698 if (props->has_core_id && props->core_id != slot->props.core_id) { 699 continue; 700 } 701 702 if (props->has_die_id && props->die_id != slot->props.die_id) { 703 continue; 704 } 705 706 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 707 continue; 708 } 709 710 /* reject assignment if slot is already assigned, for compatibility 711 * of legacy cpu_index mapping with SPAPR core based mapping do not 712 * error out if cpu thread and matched core have the same node-id */ 713 if (slot->props.has_node_id && 714 slot->props.node_id != props->node_id) { 715 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 716 slot->props.node_id); 717 return; 718 } 719 720 /* assign slot to node as it's matched '-numa cpu' key */ 721 match = true; 722 slot->props.node_id = props->node_id; 723 slot->props.has_node_id = props->has_node_id; 724 725 if (machine->numa_state->hmat_enabled) { 726 if ((numa_info[props->node_id].initiator < MAX_NODES) && 727 (props->node_id != numa_info[props->node_id].initiator)) { 728 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 729 " should be itself", props->node_id); 730 return; 731 } 732 numa_info[props->node_id].has_cpu = true; 733 numa_info[props->node_id].initiator = props->node_id; 734 } 735 } 736 737 if (!match) { 738 error_setg(errp, "no match found"); 739 } 740 } 741 742 static void smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp) 743 { 744 unsigned cpus = config->has_cpus ? config->cpus : 0; 745 unsigned sockets = config->has_sockets ? config->sockets : 0; 746 unsigned cores = config->has_cores ? config->cores : 0; 747 unsigned threads = config->has_threads ? config->threads : 0; 748 749 /* compute missing values, prefer sockets over cores over threads */ 750 if (cpus == 0 || sockets == 0) { 751 cores = cores > 0 ? cores : 1; 752 threads = threads > 0 ? threads : 1; 753 if (cpus == 0) { 754 sockets = sockets > 0 ? sockets : 1; 755 cpus = cores * threads * sockets; 756 } else { 757 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 758 sockets = ms->smp.max_cpus / (cores * threads); 759 } 760 } else if (cores == 0) { 761 threads = threads > 0 ? threads : 1; 762 cores = cpus / (sockets * threads); 763 cores = cores > 0 ? cores : 1; 764 } else if (threads == 0) { 765 threads = cpus / (cores * sockets); 766 threads = threads > 0 ? threads : 1; 767 } else if (sockets * cores * threads < cpus) { 768 error_setg(errp, "cpu topology: " 769 "sockets (%u) * cores (%u) * threads (%u) < " 770 "smp_cpus (%u)", 771 sockets, cores, threads, cpus); 772 return; 773 } 774 775 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 776 777 if (ms->smp.max_cpus < cpus) { 778 error_setg(errp, "maxcpus must be equal to or greater than smp"); 779 return; 780 } 781 782 if (sockets * cores * threads != ms->smp.max_cpus) { 783 error_setg(errp, "Invalid CPU topology: " 784 "sockets (%u) * cores (%u) * threads (%u) " 785 "!= maxcpus (%u)", 786 sockets, cores, threads, 787 ms->smp.max_cpus); 788 return; 789 } 790 791 ms->smp.cpus = cpus; 792 ms->smp.cores = cores; 793 ms->smp.threads = threads; 794 ms->smp.sockets = sockets; 795 } 796 797 static void machine_class_init(ObjectClass *oc, void *data) 798 { 799 MachineClass *mc = MACHINE_CLASS(oc); 800 801 /* Default 128 MB as guest ram size */ 802 mc->default_ram_size = 128 * MiB; 803 mc->rom_file_has_mr = true; 804 mc->smp_parse = smp_parse; 805 806 /* numa node memory size aligned on 8MB by default. 807 * On Linux, each node's border has to be 8MB aligned 808 */ 809 mc->numa_mem_align_shift = 23; 810 811 object_class_property_add_str(oc, "kernel", 812 machine_get_kernel, machine_set_kernel); 813 object_class_property_set_description(oc, "kernel", 814 "Linux kernel image file"); 815 816 object_class_property_add_str(oc, "initrd", 817 machine_get_initrd, machine_set_initrd); 818 object_class_property_set_description(oc, "initrd", 819 "Linux initial ramdisk file"); 820 821 object_class_property_add_str(oc, "append", 822 machine_get_append, machine_set_append); 823 object_class_property_set_description(oc, "append", 824 "Linux kernel command line"); 825 826 object_class_property_add_str(oc, "dtb", 827 machine_get_dtb, machine_set_dtb); 828 object_class_property_set_description(oc, "dtb", 829 "Linux kernel device tree file"); 830 831 object_class_property_add_str(oc, "dumpdtb", 832 machine_get_dumpdtb, machine_set_dumpdtb); 833 object_class_property_set_description(oc, "dumpdtb", 834 "Dump current dtb to a file and quit"); 835 836 object_class_property_add(oc, "phandle-start", "int", 837 machine_get_phandle_start, machine_set_phandle_start, 838 NULL, NULL); 839 object_class_property_set_description(oc, "phandle-start", 840 "The first phandle ID we may generate dynamically"); 841 842 object_class_property_add_str(oc, "dt-compatible", 843 machine_get_dt_compatible, machine_set_dt_compatible); 844 object_class_property_set_description(oc, "dt-compatible", 845 "Overrides the \"compatible\" property of the dt root node"); 846 847 object_class_property_add_bool(oc, "dump-guest-core", 848 machine_get_dump_guest_core, machine_set_dump_guest_core); 849 object_class_property_set_description(oc, "dump-guest-core", 850 "Include guest memory in a core dump"); 851 852 object_class_property_add_bool(oc, "mem-merge", 853 machine_get_mem_merge, machine_set_mem_merge); 854 object_class_property_set_description(oc, "mem-merge", 855 "Enable/disable memory merge support"); 856 857 object_class_property_add_bool(oc, "usb", 858 machine_get_usb, machine_set_usb); 859 object_class_property_set_description(oc, "usb", 860 "Set on/off to enable/disable usb"); 861 862 object_class_property_add_bool(oc, "graphics", 863 machine_get_graphics, machine_set_graphics); 864 object_class_property_set_description(oc, "graphics", 865 "Set on/off to enable/disable graphics emulation"); 866 867 object_class_property_add_str(oc, "firmware", 868 machine_get_firmware, machine_set_firmware); 869 object_class_property_set_description(oc, "firmware", 870 "Firmware image"); 871 872 object_class_property_add_bool(oc, "suppress-vmdesc", 873 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 874 object_class_property_set_description(oc, "suppress-vmdesc", 875 "Set on to disable self-describing migration"); 876 877 object_class_property_add_link(oc, "confidential-guest-support", 878 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 879 offsetof(MachineState, cgs), 880 machine_check_confidential_guest_support, 881 OBJ_PROP_LINK_STRONG); 882 object_class_property_set_description(oc, "confidential-guest-support", 883 "Set confidential guest scheme to support"); 884 885 /* For compatibility */ 886 object_class_property_add_str(oc, "memory-encryption", 887 machine_get_memory_encryption, machine_set_memory_encryption); 888 object_class_property_set_description(oc, "memory-encryption", 889 "Set memory encryption object to use"); 890 891 object_class_property_add_str(oc, "memory-backend", 892 machine_get_memdev, machine_set_memdev); 893 object_class_property_set_description(oc, "memory-backend", 894 "Set RAM backend" 895 "Valid value is ID of hostmem based backend"); 896 } 897 898 static void machine_class_base_init(ObjectClass *oc, void *data) 899 { 900 MachineClass *mc = MACHINE_CLASS(oc); 901 mc->max_cpus = mc->max_cpus ?: 1; 902 mc->min_cpus = mc->min_cpus ?: 1; 903 mc->default_cpus = mc->default_cpus ?: 1; 904 905 if (!object_class_is_abstract(oc)) { 906 const char *cname = object_class_get_name(oc); 907 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 908 mc->name = g_strndup(cname, 909 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 910 mc->compat_props = g_ptr_array_new(); 911 } 912 } 913 914 static void machine_initfn(Object *obj) 915 { 916 MachineState *ms = MACHINE(obj); 917 MachineClass *mc = MACHINE_GET_CLASS(obj); 918 919 container_get(obj, "/peripheral"); 920 container_get(obj, "/peripheral-anon"); 921 922 ms->dump_guest_core = true; 923 ms->mem_merge = true; 924 ms->enable_graphics = true; 925 ms->kernel_cmdline = g_strdup(""); 926 927 if (mc->nvdimm_supported) { 928 Object *obj = OBJECT(ms); 929 930 ms->nvdimms_state = g_new0(NVDIMMState, 1); 931 object_property_add_bool(obj, "nvdimm", 932 machine_get_nvdimm, machine_set_nvdimm); 933 object_property_set_description(obj, "nvdimm", 934 "Set on/off to enable/disable " 935 "NVDIMM instantiation"); 936 937 object_property_add_str(obj, "nvdimm-persistence", 938 machine_get_nvdimm_persistence, 939 machine_set_nvdimm_persistence); 940 object_property_set_description(obj, "nvdimm-persistence", 941 "Set NVDIMM persistence" 942 "Valid values are cpu, mem-ctrl"); 943 } 944 945 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 946 ms->numa_state = g_new0(NumaState, 1); 947 object_property_add_bool(obj, "hmat", 948 machine_get_hmat, machine_set_hmat); 949 object_property_set_description(obj, "hmat", 950 "Set on/off to enable/disable " 951 "ACPI Heterogeneous Memory Attribute " 952 "Table (HMAT)"); 953 } 954 955 /* Register notifier when init is done for sysbus sanity checks */ 956 ms->sysbus_notifier.notify = machine_init_notify; 957 qemu_add_machine_init_done_notifier(&ms->sysbus_notifier); 958 959 /* default to mc->default_cpus */ 960 ms->smp.cpus = mc->default_cpus; 961 ms->smp.max_cpus = mc->default_cpus; 962 ms->smp.cores = 1; 963 ms->smp.dies = 1; 964 ms->smp.threads = 1; 965 ms->smp.sockets = 1; 966 } 967 968 static void machine_finalize(Object *obj) 969 { 970 MachineState *ms = MACHINE(obj); 971 972 g_free(ms->kernel_filename); 973 g_free(ms->initrd_filename); 974 g_free(ms->kernel_cmdline); 975 g_free(ms->dtb); 976 g_free(ms->dumpdtb); 977 g_free(ms->dt_compatible); 978 g_free(ms->firmware); 979 g_free(ms->device_memory); 980 g_free(ms->nvdimms_state); 981 g_free(ms->numa_state); 982 } 983 984 bool machine_usb(MachineState *machine) 985 { 986 return machine->usb; 987 } 988 989 int machine_phandle_start(MachineState *machine) 990 { 991 return machine->phandle_start; 992 } 993 994 bool machine_dump_guest_core(MachineState *machine) 995 { 996 return machine->dump_guest_core; 997 } 998 999 bool machine_mem_merge(MachineState *machine) 1000 { 1001 return machine->mem_merge; 1002 } 1003 1004 static char *cpu_slot_to_string(const CPUArchId *cpu) 1005 { 1006 GString *s = g_string_new(NULL); 1007 if (cpu->props.has_socket_id) { 1008 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1009 } 1010 if (cpu->props.has_die_id) { 1011 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1012 } 1013 if (cpu->props.has_core_id) { 1014 if (s->len) { 1015 g_string_append_printf(s, ", "); 1016 } 1017 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1018 } 1019 if (cpu->props.has_thread_id) { 1020 if (s->len) { 1021 g_string_append_printf(s, ", "); 1022 } 1023 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1024 } 1025 return g_string_free(s, false); 1026 } 1027 1028 static void numa_validate_initiator(NumaState *numa_state) 1029 { 1030 int i; 1031 NodeInfo *numa_info = numa_state->nodes; 1032 1033 for (i = 0; i < numa_state->num_nodes; i++) { 1034 if (numa_info[i].initiator == MAX_NODES) { 1035 error_report("The initiator of NUMA node %d is missing, use " 1036 "'-numa node,initiator' option to declare it", i); 1037 exit(1); 1038 } 1039 1040 if (!numa_info[numa_info[i].initiator].present) { 1041 error_report("NUMA node %" PRIu16 " is missing, use " 1042 "'-numa node' option to declare it first", 1043 numa_info[i].initiator); 1044 exit(1); 1045 } 1046 1047 if (!numa_info[numa_info[i].initiator].has_cpu) { 1048 error_report("The initiator of NUMA node %d is invalid", i); 1049 exit(1); 1050 } 1051 } 1052 } 1053 1054 static void machine_numa_finish_cpu_init(MachineState *machine) 1055 { 1056 int i; 1057 bool default_mapping; 1058 GString *s = g_string_new(NULL); 1059 MachineClass *mc = MACHINE_GET_CLASS(machine); 1060 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1061 1062 assert(machine->numa_state->num_nodes); 1063 for (i = 0; i < possible_cpus->len; i++) { 1064 if (possible_cpus->cpus[i].props.has_node_id) { 1065 break; 1066 } 1067 } 1068 default_mapping = (i == possible_cpus->len); 1069 1070 for (i = 0; i < possible_cpus->len; i++) { 1071 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1072 1073 if (!cpu_slot->props.has_node_id) { 1074 /* fetch default mapping from board and enable it */ 1075 CpuInstanceProperties props = cpu_slot->props; 1076 1077 props.node_id = mc->get_default_cpu_node_id(machine, i); 1078 if (!default_mapping) { 1079 /* record slots with not set mapping, 1080 * TODO: make it hard error in future */ 1081 char *cpu_str = cpu_slot_to_string(cpu_slot); 1082 g_string_append_printf(s, "%sCPU %d [%s]", 1083 s->len ? ", " : "", i, cpu_str); 1084 g_free(cpu_str); 1085 1086 /* non mapped cpus used to fallback to node 0 */ 1087 props.node_id = 0; 1088 } 1089 1090 props.has_node_id = true; 1091 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1092 } 1093 } 1094 1095 if (machine->numa_state->hmat_enabled) { 1096 numa_validate_initiator(machine->numa_state); 1097 } 1098 1099 if (s->len && !qtest_enabled()) { 1100 warn_report("CPU(s) not present in any NUMA nodes: %s", 1101 s->str); 1102 warn_report("All CPU(s) up to maxcpus should be described " 1103 "in NUMA config, ability to start up with partial NUMA " 1104 "mappings is obsoleted and will be removed in future"); 1105 } 1106 g_string_free(s, true); 1107 } 1108 1109 MemoryRegion *machine_consume_memdev(MachineState *machine, 1110 HostMemoryBackend *backend) 1111 { 1112 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1113 1114 if (memory_region_is_mapped(ret)) { 1115 error_report("memory backend %s can't be used multiple times.", 1116 object_get_canonical_path_component(OBJECT(backend))); 1117 exit(EXIT_FAILURE); 1118 } 1119 host_memory_backend_set_mapped(backend, true); 1120 vmstate_register_ram_global(ret); 1121 return ret; 1122 } 1123 1124 bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp) 1125 { 1126 MachineClass *mc = MACHINE_GET_CLASS(ms); 1127 ERRP_GUARD(); 1128 1129 if (opts) { 1130 SMPConfiguration config = { 1131 .has_cpus = !!qemu_opt_get(opts, "cpus"), 1132 .cpus = qemu_opt_get_number(opts, "cpus", 0), 1133 .has_sockets = !!qemu_opt_get(opts, "sockets"), 1134 .sockets = qemu_opt_get_number(opts, "sockets", 0), 1135 .has_dies = !!qemu_opt_get(opts, "dies"), 1136 .dies = qemu_opt_get_number(opts, "dies", 0), 1137 .has_cores = !!qemu_opt_get(opts, "cores"), 1138 .cores = qemu_opt_get_number(opts, "cores", 0), 1139 .has_threads = !!qemu_opt_get(opts, "threads"), 1140 .threads = qemu_opt_get_number(opts, "threads", 0), 1141 .has_maxcpus = !!qemu_opt_get(opts, "maxcpus"), 1142 .maxcpus = qemu_opt_get_number(opts, "maxcpus", 0), 1143 }; 1144 1145 mc->smp_parse(ms, &config, errp); 1146 if (*errp) { 1147 return false; 1148 } 1149 } 1150 1151 /* sanity-check smp_cpus and max_cpus against mc */ 1152 if (ms->smp.cpus < mc->min_cpus) { 1153 error_setg(errp, "Invalid SMP CPUs %d. The min CPUs " 1154 "supported by machine '%s' is %d", 1155 ms->smp.cpus, 1156 mc->name, mc->min_cpus); 1157 return false; 1158 } else if (ms->smp.max_cpus > mc->max_cpus) { 1159 error_setg(errp, "Invalid SMP CPUs %d. The max CPUs " 1160 "supported by machine '%s' is %d", 1161 current_machine->smp.max_cpus, 1162 mc->name, mc->max_cpus); 1163 return false; 1164 } 1165 1166 if (ms->smp.cpus > 1) { 1167 Error *blocker = NULL; 1168 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 1169 replay_add_blocker(blocker); 1170 } 1171 return true; 1172 } 1173 1174 void machine_run_board_init(MachineState *machine) 1175 { 1176 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1177 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1178 CPUClass *cc; 1179 1180 /* This checkpoint is required by replay to separate prior clock 1181 reading from the other reads, because timer polling functions query 1182 clock values from the log. */ 1183 replay_checkpoint(CHECKPOINT_INIT); 1184 1185 if (machine->ram_memdev_id) { 1186 Object *o; 1187 o = object_resolve_path_type(machine->ram_memdev_id, 1188 TYPE_MEMORY_BACKEND, NULL); 1189 machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o)); 1190 } 1191 1192 if (machine->numa_state) { 1193 numa_complete_configuration(machine); 1194 if (machine->numa_state->num_nodes) { 1195 machine_numa_finish_cpu_init(machine); 1196 } 1197 } 1198 1199 /* If the machine supports the valid_cpu_types check and the user 1200 * specified a CPU with -cpu check here that the user CPU is supported. 1201 */ 1202 if (machine_class->valid_cpu_types && machine->cpu_type) { 1203 int i; 1204 1205 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1206 if (object_class_dynamic_cast(oc, 1207 machine_class->valid_cpu_types[i])) { 1208 /* The user specificed CPU is in the valid field, we are 1209 * good to go. 1210 */ 1211 break; 1212 } 1213 } 1214 1215 if (!machine_class->valid_cpu_types[i]) { 1216 /* The user specified CPU is not valid */ 1217 error_report("Invalid CPU type: %s", machine->cpu_type); 1218 error_printf("The valid types are: %s", 1219 machine_class->valid_cpu_types[0]); 1220 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1221 error_printf(", %s", machine_class->valid_cpu_types[i]); 1222 } 1223 error_printf("\n"); 1224 1225 exit(1); 1226 } 1227 } 1228 1229 /* Check if CPU type is deprecated and warn if so */ 1230 cc = CPU_CLASS(oc); 1231 if (cc && cc->deprecation_note) { 1232 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1233 cc->deprecation_note); 1234 } 1235 1236 if (machine->cgs) { 1237 /* 1238 * With confidential guests, the host can't see the real 1239 * contents of RAM, so there's no point in it trying to merge 1240 * areas. 1241 */ 1242 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1243 1244 /* 1245 * Virtio devices can't count on directly accessing guest 1246 * memory, so they need iommu_platform=on to use normal DMA 1247 * mechanisms. That requires also disabling legacy virtio 1248 * support for those virtio pci devices which allow it. 1249 */ 1250 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1251 "on", true); 1252 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1253 "on", false); 1254 } 1255 1256 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1257 machine_class->init(machine); 1258 phase_advance(PHASE_MACHINE_INITIALIZED); 1259 } 1260 1261 static NotifierList machine_init_done_notifiers = 1262 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1263 1264 void qemu_add_machine_init_done_notifier(Notifier *notify) 1265 { 1266 notifier_list_add(&machine_init_done_notifiers, notify); 1267 if (phase_check(PHASE_MACHINE_READY)) { 1268 notify->notify(notify, NULL); 1269 } 1270 } 1271 1272 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1273 { 1274 notifier_remove(notify); 1275 } 1276 1277 void qdev_machine_creation_done(void) 1278 { 1279 cpu_synchronize_all_post_init(); 1280 1281 if (current_machine->boot_once) { 1282 qemu_boot_set(current_machine->boot_once, &error_fatal); 1283 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order)); 1284 } 1285 1286 /* 1287 * ok, initial machine setup is done, starting from now we can 1288 * only create hotpluggable devices 1289 */ 1290 phase_advance(PHASE_MACHINE_READY); 1291 qdev_assert_realized_properly(); 1292 1293 /* TODO: once all bus devices are qdevified, this should be done 1294 * when bus is created by qdev.c */ 1295 /* 1296 * TODO: If we had a main 'reset container' that the whole system 1297 * lived in, we could reset that using the multi-phase reset 1298 * APIs. For the moment, we just reset the sysbus, which will cause 1299 * all devices hanging off it (and all their child buses, recursively) 1300 * to be reset. Note that this will *not* reset any Device objects 1301 * which are not attached to some part of the qbus tree! 1302 */ 1303 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1304 1305 notifier_list_notify(&machine_init_done_notifiers, NULL); 1306 1307 if (rom_check_and_register_reset() != 0) { 1308 exit(1); 1309 } 1310 1311 replay_start(); 1312 1313 /* This checkpoint is required by replay to separate prior clock 1314 reading from the other reads, because timer polling functions query 1315 clock values from the log. */ 1316 replay_checkpoint(CHECKPOINT_RESET); 1317 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1318 register_global_state(); 1319 } 1320 1321 static const TypeInfo machine_info = { 1322 .name = TYPE_MACHINE, 1323 .parent = TYPE_OBJECT, 1324 .abstract = true, 1325 .class_size = sizeof(MachineClass), 1326 .class_init = machine_class_init, 1327 .class_base_init = machine_class_base_init, 1328 .instance_size = sizeof(MachineState), 1329 .instance_init = machine_initfn, 1330 .instance_finalize = machine_finalize, 1331 }; 1332 1333 static void machine_register_types(void) 1334 { 1335 type_register_static(&machine_info); 1336 } 1337 1338 type_init(machine_register_types) 1339