xref: /openbmc/qemu/hw/core/cpu-common.c (revision effd60c8)
1 /*
2  * QEMU CPU model
3  *
4  * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/core/cpu.h"
24 #include "sysemu/hw_accel.h"
25 #include "qemu/notify.h"
26 #include "qemu/log.h"
27 #include "qemu/main-loop.h"
28 #include "exec/log.h"
29 #include "exec/cpu-common.h"
30 #include "qemu/error-report.h"
31 #include "qemu/qemu-print.h"
32 #include "sysemu/tcg.h"
33 #include "hw/boards.h"
34 #include "hw/qdev-properties.h"
35 #include "trace.h"
36 #include "qemu/plugin.h"
37 
38 CPUState *cpu_by_arch_id(int64_t id)
39 {
40     CPUState *cpu;
41 
42     CPU_FOREACH(cpu) {
43         CPUClass *cc = CPU_GET_CLASS(cpu);
44 
45         if (cc->get_arch_id(cpu) == id) {
46             return cpu;
47         }
48     }
49     return NULL;
50 }
51 
52 bool cpu_exists(int64_t id)
53 {
54     return !!cpu_by_arch_id(id);
55 }
56 
57 CPUState *cpu_create(const char *typename)
58 {
59     Error *err = NULL;
60     CPUState *cpu = CPU(object_new(typename));
61     if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
62         error_report_err(err);
63         object_unref(OBJECT(cpu));
64         exit(EXIT_FAILURE);
65     }
66     return cpu;
67 }
68 
69 /* Resetting the IRQ comes from across the code base so we take the
70  * BQL here if we need to.  cpu_interrupt assumes it is held.*/
71 void cpu_reset_interrupt(CPUState *cpu, int mask)
72 {
73     bool need_lock = !bql_locked();
74 
75     if (need_lock) {
76         bql_lock();
77     }
78     cpu->interrupt_request &= ~mask;
79     if (need_lock) {
80         bql_unlock();
81     }
82 }
83 
84 void cpu_exit(CPUState *cpu)
85 {
86     qatomic_set(&cpu->exit_request, 1);
87     /* Ensure cpu_exec will see the exit request after TCG has exited.  */
88     smp_wmb();
89     qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
90 }
91 
92 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
93 {
94     return 0;
95 }
96 
97 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
98 {
99     return 0;
100 }
101 
102 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
103 {
104     CPUClass *cc = CPU_GET_CLASS(cpu);
105 
106     if (cc->dump_state) {
107         cpu_synchronize_state(cpu);
108         cc->dump_state(cpu, f, flags);
109     }
110 }
111 
112 void cpu_reset(CPUState *cpu)
113 {
114     device_cold_reset(DEVICE(cpu));
115 
116     trace_cpu_reset(cpu->cpu_index);
117 }
118 
119 static void cpu_common_reset_hold(Object *obj)
120 {
121     CPUState *cpu = CPU(obj);
122     CPUClass *cc = CPU_GET_CLASS(cpu);
123 
124     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
125         qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
126         log_cpu_state(cpu, cc->reset_dump_flags);
127     }
128 
129     cpu->interrupt_request = 0;
130     cpu->halted = cpu->start_powered_off;
131     cpu->mem_io_pc = 0;
132     cpu->icount_extra = 0;
133     qatomic_set(&cpu->neg.icount_decr.u32, 0);
134     cpu->neg.can_do_io = true;
135     cpu->exception_index = -1;
136     cpu->crash_occurred = false;
137     cpu->cflags_next_tb = -1;
138 
139     cpu_exec_reset_hold(cpu);
140 }
141 
142 static bool cpu_common_has_work(CPUState *cs)
143 {
144     return false;
145 }
146 
147 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
148 {
149     ObjectClass *oc;
150     CPUClass *cc;
151 
152     oc = object_class_by_name(typename);
153     cc = CPU_CLASS(oc);
154     assert(cc->class_by_name);
155     assert(cpu_model);
156     oc = cc->class_by_name(cpu_model);
157     if (object_class_dynamic_cast(oc, typename) &&
158         !object_class_is_abstract(oc)) {
159         return oc;
160     }
161 
162     return NULL;
163 }
164 
165 static void cpu_common_parse_features(const char *typename, char *features,
166                                       Error **errp)
167 {
168     char *val;
169     static bool cpu_globals_initialized;
170     /* Single "key=value" string being parsed */
171     char *featurestr = features ? strtok(features, ",") : NULL;
172 
173     /* should be called only once, catch invalid users */
174     assert(!cpu_globals_initialized);
175     cpu_globals_initialized = true;
176 
177     while (featurestr) {
178         val = strchr(featurestr, '=');
179         if (val) {
180             GlobalProperty *prop = g_new0(typeof(*prop), 1);
181             *val = 0;
182             val++;
183             prop->driver = typename;
184             prop->property = g_strdup(featurestr);
185             prop->value = g_strdup(val);
186             qdev_prop_register_global(prop);
187         } else {
188             error_setg(errp, "Expected key=value format, found %s.",
189                        featurestr);
190             return;
191         }
192         featurestr = strtok(NULL, ",");
193     }
194 }
195 
196 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
197 {
198     CPUState *cpu = CPU(dev);
199     Object *machine = qdev_get_machine();
200 
201     /* qdev_get_machine() can return something that's not TYPE_MACHINE
202      * if this is one of the user-only emulators; in that case there's
203      * no need to check the ignore_memory_transaction_failures board flag.
204      */
205     if (object_dynamic_cast(machine, TYPE_MACHINE)) {
206         MachineClass *mc = MACHINE_GET_CLASS(machine);
207 
208         if (mc) {
209             cpu->ignore_memory_transaction_failures =
210                 mc->ignore_memory_transaction_failures;
211         }
212     }
213 
214     if (dev->hotplugged) {
215         cpu_synchronize_post_init(cpu);
216         cpu_resume(cpu);
217     }
218 
219     /* Plugin initialization must wait until the cpu is fully realized. */
220     if (tcg_enabled()) {
221         qemu_plugin_vcpu_init_hook(cpu);
222     }
223 
224     /* NOTE: latest generic point where the cpu is fully realized */
225 }
226 
227 static void cpu_common_unrealizefn(DeviceState *dev)
228 {
229     CPUState *cpu = CPU(dev);
230 
231     /* Call the plugin hook before clearing the cpu is fully unrealized */
232     if (tcg_enabled()) {
233         qemu_plugin_vcpu_exit_hook(cpu);
234     }
235 
236     /* NOTE: latest generic point before the cpu is fully unrealized */
237     cpu_exec_unrealizefn(cpu);
238 }
239 
240 static void cpu_common_initfn(Object *obj)
241 {
242     CPUState *cpu = CPU(obj);
243     CPUClass *cc = CPU_GET_CLASS(obj);
244 
245     cpu->cpu_index = UNASSIGNED_CPU_INDEX;
246     cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
247     cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
248     /* user-mode doesn't have configurable SMP topology */
249     /* the default value is changed by qemu_init_vcpu() for system-mode */
250     cpu->nr_cores = 1;
251     cpu->nr_threads = 1;
252     cpu->cflags_next_tb = -1;
253 
254     qemu_mutex_init(&cpu->work_mutex);
255     qemu_lockcnt_init(&cpu->in_ioctl_lock);
256     QSIMPLEQ_INIT(&cpu->work_list);
257     QTAILQ_INIT(&cpu->breakpoints);
258     QTAILQ_INIT(&cpu->watchpoints);
259 
260     cpu_exec_initfn(cpu);
261 }
262 
263 static void cpu_common_finalize(Object *obj)
264 {
265     CPUState *cpu = CPU(obj);
266 
267     qemu_lockcnt_destroy(&cpu->in_ioctl_lock);
268     qemu_mutex_destroy(&cpu->work_mutex);
269 }
270 
271 static int64_t cpu_common_get_arch_id(CPUState *cpu)
272 {
273     return cpu->cpu_index;
274 }
275 
276 static void cpu_common_class_init(ObjectClass *klass, void *data)
277 {
278     DeviceClass *dc = DEVICE_CLASS(klass);
279     ResettableClass *rc = RESETTABLE_CLASS(klass);
280     CPUClass *k = CPU_CLASS(klass);
281 
282     k->parse_features = cpu_common_parse_features;
283     k->get_arch_id = cpu_common_get_arch_id;
284     k->has_work = cpu_common_has_work;
285     k->gdb_read_register = cpu_common_gdb_read_register;
286     k->gdb_write_register = cpu_common_gdb_write_register;
287     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
288     dc->realize = cpu_common_realizefn;
289     dc->unrealize = cpu_common_unrealizefn;
290     rc->phases.hold = cpu_common_reset_hold;
291     cpu_class_init_props(dc);
292     /*
293      * Reason: CPUs still need special care by board code: wiring up
294      * IRQs, adding reset handlers, halting non-first CPUs, ...
295      */
296     dc->user_creatable = false;
297 }
298 
299 static const TypeInfo cpu_type_info = {
300     .name = TYPE_CPU,
301     .parent = TYPE_DEVICE,
302     .instance_size = sizeof(CPUState),
303     .instance_init = cpu_common_initfn,
304     .instance_finalize = cpu_common_finalize,
305     .abstract = true,
306     .class_size = sizeof(CPUClass),
307     .class_init = cpu_common_class_init,
308 };
309 
310 static void cpu_register_types(void)
311 {
312     type_register_static(&cpu_type_info);
313 }
314 
315 type_init(cpu_register_types)
316