1 /* 2 * QEMU model of Xilinx uartlite. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "sysemu/char.h" 27 28 #define DUART(x) 29 30 #define R_RX 0 31 #define R_TX 1 32 #define R_STATUS 2 33 #define R_CTRL 3 34 #define R_MAX 4 35 36 #define STATUS_RXVALID 0x01 37 #define STATUS_RXFULL 0x02 38 #define STATUS_TXEMPTY 0x04 39 #define STATUS_TXFULL 0x08 40 #define STATUS_IE 0x10 41 #define STATUS_OVERRUN 0x20 42 #define STATUS_FRAME 0x40 43 #define STATUS_PARITY 0x80 44 45 #define CONTROL_RST_TX 0x01 46 #define CONTROL_RST_RX 0x02 47 #define CONTROL_IE 0x10 48 49 struct xlx_uartlite 50 { 51 SysBusDevice busdev; 52 MemoryRegion mmio; 53 CharDriverState *chr; 54 qemu_irq irq; 55 56 uint8_t rx_fifo[8]; 57 unsigned int rx_fifo_pos; 58 unsigned int rx_fifo_len; 59 60 uint32_t regs[R_MAX]; 61 }; 62 63 static void uart_update_irq(struct xlx_uartlite *s) 64 { 65 unsigned int irq; 66 67 if (s->rx_fifo_len) 68 s->regs[R_STATUS] |= STATUS_IE; 69 70 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); 71 qemu_set_irq(s->irq, irq); 72 } 73 74 static void uart_update_status(struct xlx_uartlite *s) 75 { 76 uint32_t r; 77 78 r = s->regs[R_STATUS]; 79 r &= ~7; 80 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ 81 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; 82 r |= (!!s->rx_fifo_len); 83 s->regs[R_STATUS] = r; 84 } 85 86 static uint64_t 87 uart_read(void *opaque, hwaddr addr, unsigned int size) 88 { 89 struct xlx_uartlite *s = opaque; 90 uint32_t r = 0; 91 addr >>= 2; 92 switch (addr) 93 { 94 case R_RX: 95 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; 96 if (s->rx_fifo_len) 97 s->rx_fifo_len--; 98 uart_update_status(s); 99 uart_update_irq(s); 100 qemu_chr_accept_input(s->chr); 101 break; 102 103 default: 104 if (addr < ARRAY_SIZE(s->regs)) 105 r = s->regs[addr]; 106 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); 107 break; 108 } 109 return r; 110 } 111 112 static void 113 uart_write(void *opaque, hwaddr addr, 114 uint64_t val64, unsigned int size) 115 { 116 struct xlx_uartlite *s = opaque; 117 uint32_t value = val64; 118 unsigned char ch = value; 119 120 addr >>= 2; 121 switch (addr) 122 { 123 case R_STATUS: 124 hw_error("write to UART STATUS?\n"); 125 break; 126 127 case R_CTRL: 128 if (value & CONTROL_RST_RX) { 129 s->rx_fifo_pos = 0; 130 s->rx_fifo_len = 0; 131 } 132 s->regs[addr] = value; 133 break; 134 135 case R_TX: 136 if (s->chr) 137 qemu_chr_fe_write(s->chr, &ch, 1); 138 139 s->regs[addr] = value; 140 141 /* hax. */ 142 s->regs[R_STATUS] |= STATUS_IE; 143 break; 144 145 default: 146 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); 147 if (addr < ARRAY_SIZE(s->regs)) 148 s->regs[addr] = value; 149 break; 150 } 151 uart_update_status(s); 152 uart_update_irq(s); 153 } 154 155 static const MemoryRegionOps uart_ops = { 156 .read = uart_read, 157 .write = uart_write, 158 .endianness = DEVICE_NATIVE_ENDIAN, 159 .valid = { 160 .min_access_size = 1, 161 .max_access_size = 4 162 } 163 }; 164 165 static void uart_rx(void *opaque, const uint8_t *buf, int size) 166 { 167 struct xlx_uartlite *s = opaque; 168 169 /* Got a byte. */ 170 if (s->rx_fifo_len >= 8) { 171 printf("WARNING: UART dropped char.\n"); 172 return; 173 } 174 s->rx_fifo[s->rx_fifo_pos] = *buf; 175 s->rx_fifo_pos++; 176 s->rx_fifo_pos &= 0x7; 177 s->rx_fifo_len++; 178 179 uart_update_status(s); 180 uart_update_irq(s); 181 } 182 183 static int uart_can_rx(void *opaque) 184 { 185 struct xlx_uartlite *s = opaque; 186 187 return s->rx_fifo_len < sizeof(s->rx_fifo); 188 } 189 190 static void uart_event(void *opaque, int event) 191 { 192 193 } 194 195 static int xilinx_uartlite_init(SysBusDevice *dev) 196 { 197 struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev); 198 199 sysbus_init_irq(dev, &s->irq); 200 201 uart_update_status(s); 202 memory_region_init_io(&s->mmio, &uart_ops, s, "xlnx.xps-uartlite", 203 R_MAX * 4); 204 sysbus_init_mmio(dev, &s->mmio); 205 206 s->chr = qemu_char_get_next_serial(); 207 if (s->chr) 208 qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); 209 return 0; 210 } 211 212 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) 213 { 214 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 215 216 sdc->init = xilinx_uartlite_init; 217 } 218 219 static const TypeInfo xilinx_uartlite_info = { 220 .name = "xlnx.xps-uartlite", 221 .parent = TYPE_SYS_BUS_DEVICE, 222 .instance_size = sizeof (struct xlx_uartlite), 223 .class_init = xilinx_uartlite_class_init, 224 }; 225 226 static void xilinx_uart_register_types(void) 227 { 228 type_register_static(&xilinx_uartlite_info); 229 } 230 231 type_init(xilinx_uart_register_types) 232