1 /* 2 * QEMU model of Xilinx uartlite. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/sysbus.h" 30 #include "qemu/module.h" 31 #include "chardev/char-fe.h" 32 #include "qom/object.h" 33 34 #define DUART(x) 35 36 #define R_RX 0 37 #define R_TX 1 38 #define R_STATUS 2 39 #define R_CTRL 3 40 #define R_MAX 4 41 42 #define STATUS_RXVALID 0x01 43 #define STATUS_RXFULL 0x02 44 #define STATUS_TXEMPTY 0x04 45 #define STATUS_TXFULL 0x08 46 #define STATUS_IE 0x10 47 #define STATUS_OVERRUN 0x20 48 #define STATUS_FRAME 0x40 49 #define STATUS_PARITY 0x80 50 51 #define CONTROL_RST_TX 0x01 52 #define CONTROL_RST_RX 0x02 53 #define CONTROL_IE 0x10 54 55 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" 56 typedef struct XilinxUARTLite XilinxUARTLite; 57 DECLARE_INSTANCE_CHECKER(XilinxUARTLite, XILINX_UARTLITE, 58 TYPE_XILINX_UARTLITE) 59 60 struct XilinxUARTLite { 61 SysBusDevice parent_obj; 62 63 MemoryRegion mmio; 64 CharBackend chr; 65 qemu_irq irq; 66 67 uint8_t rx_fifo[8]; 68 unsigned int rx_fifo_pos; 69 unsigned int rx_fifo_len; 70 71 uint32_t regs[R_MAX]; 72 }; 73 74 static void uart_update_irq(XilinxUARTLite *s) 75 { 76 unsigned int irq; 77 78 if (s->rx_fifo_len) 79 s->regs[R_STATUS] |= STATUS_IE; 80 81 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); 82 qemu_set_irq(s->irq, irq); 83 } 84 85 static void uart_update_status(XilinxUARTLite *s) 86 { 87 uint32_t r; 88 89 r = s->regs[R_STATUS]; 90 r &= ~7; 91 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ 92 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; 93 r |= (!!s->rx_fifo_len); 94 s->regs[R_STATUS] = r; 95 } 96 97 static void xilinx_uartlite_reset(DeviceState *dev) 98 { 99 uart_update_status(XILINX_UARTLITE(dev)); 100 } 101 102 static uint64_t 103 uart_read(void *opaque, hwaddr addr, unsigned int size) 104 { 105 XilinxUARTLite *s = opaque; 106 uint32_t r = 0; 107 addr >>= 2; 108 switch (addr) 109 { 110 case R_RX: 111 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; 112 if (s->rx_fifo_len) 113 s->rx_fifo_len--; 114 uart_update_status(s); 115 uart_update_irq(s); 116 qemu_chr_fe_accept_input(&s->chr); 117 break; 118 119 default: 120 if (addr < ARRAY_SIZE(s->regs)) 121 r = s->regs[addr]; 122 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); 123 break; 124 } 125 return r; 126 } 127 128 static void 129 uart_write(void *opaque, hwaddr addr, 130 uint64_t val64, unsigned int size) 131 { 132 XilinxUARTLite *s = opaque; 133 uint32_t value = val64; 134 unsigned char ch = value; 135 136 addr >>= 2; 137 switch (addr) 138 { 139 case R_STATUS: 140 qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n", 141 __func__); 142 break; 143 144 case R_CTRL: 145 if (value & CONTROL_RST_RX) { 146 s->rx_fifo_pos = 0; 147 s->rx_fifo_len = 0; 148 } 149 s->regs[addr] = value; 150 break; 151 152 case R_TX: 153 /* XXX this blocks entire thread. Rewrite to use 154 * qemu_chr_fe_write and background I/O callbacks */ 155 qemu_chr_fe_write_all(&s->chr, &ch, 1); 156 s->regs[addr] = value; 157 158 /* hax. */ 159 s->regs[R_STATUS] |= STATUS_IE; 160 break; 161 162 default: 163 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); 164 if (addr < ARRAY_SIZE(s->regs)) 165 s->regs[addr] = value; 166 break; 167 } 168 uart_update_status(s); 169 uart_update_irq(s); 170 } 171 172 static const MemoryRegionOps uart_ops = { 173 .read = uart_read, 174 .write = uart_write, 175 .endianness = DEVICE_NATIVE_ENDIAN, 176 .valid = { 177 .min_access_size = 1, 178 .max_access_size = 4 179 } 180 }; 181 182 static Property xilinx_uartlite_properties[] = { 183 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), 184 DEFINE_PROP_END_OF_LIST(), 185 }; 186 187 static void uart_rx(void *opaque, const uint8_t *buf, int size) 188 { 189 XilinxUARTLite *s = opaque; 190 191 /* Got a byte. */ 192 if (s->rx_fifo_len >= 8) { 193 printf("WARNING: UART dropped char.\n"); 194 return; 195 } 196 s->rx_fifo[s->rx_fifo_pos] = *buf; 197 s->rx_fifo_pos++; 198 s->rx_fifo_pos &= 0x7; 199 s->rx_fifo_len++; 200 201 uart_update_status(s); 202 uart_update_irq(s); 203 } 204 205 static int uart_can_rx(void *opaque) 206 { 207 XilinxUARTLite *s = opaque; 208 209 return s->rx_fifo_len < sizeof(s->rx_fifo); 210 } 211 212 static void uart_event(void *opaque, QEMUChrEvent event) 213 { 214 215 } 216 217 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) 218 { 219 XilinxUARTLite *s = XILINX_UARTLITE(dev); 220 221 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, 222 uart_event, NULL, s, NULL, true); 223 } 224 225 static void xilinx_uartlite_init(Object *obj) 226 { 227 XilinxUARTLite *s = XILINX_UARTLITE(obj); 228 229 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 230 231 memory_region_init_io(&s->mmio, obj, &uart_ops, s, 232 "xlnx.xps-uartlite", R_MAX * 4); 233 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 234 } 235 236 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) 237 { 238 DeviceClass *dc = DEVICE_CLASS(klass); 239 240 dc->reset = xilinx_uartlite_reset; 241 dc->realize = xilinx_uartlite_realize; 242 device_class_set_props(dc, xilinx_uartlite_properties); 243 } 244 245 static const TypeInfo xilinx_uartlite_info = { 246 .name = TYPE_XILINX_UARTLITE, 247 .parent = TYPE_SYS_BUS_DEVICE, 248 .instance_size = sizeof(XilinxUARTLite), 249 .instance_init = xilinx_uartlite_init, 250 .class_init = xilinx_uartlite_class_init, 251 }; 252 253 static void xilinx_uart_register_types(void) 254 { 255 type_register_static(&xilinx_uartlite_info); 256 } 257 258 type_init(xilinx_uart_register_types) 259