1 /* 2 * QEMU model of Xilinx uartlite. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sysbus.h" 29 #include "qemu/module.h" 30 #include "chardev/char-fe.h" 31 32 #define DUART(x) 33 34 #define R_RX 0 35 #define R_TX 1 36 #define R_STATUS 2 37 #define R_CTRL 3 38 #define R_MAX 4 39 40 #define STATUS_RXVALID 0x01 41 #define STATUS_RXFULL 0x02 42 #define STATUS_TXEMPTY 0x04 43 #define STATUS_TXFULL 0x08 44 #define STATUS_IE 0x10 45 #define STATUS_OVERRUN 0x20 46 #define STATUS_FRAME 0x40 47 #define STATUS_PARITY 0x80 48 49 #define CONTROL_RST_TX 0x01 50 #define CONTROL_RST_RX 0x02 51 #define CONTROL_IE 0x10 52 53 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" 54 #define XILINX_UARTLITE(obj) \ 55 OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE) 56 57 typedef struct XilinxUARTLite { 58 SysBusDevice parent_obj; 59 60 MemoryRegion mmio; 61 CharBackend chr; 62 qemu_irq irq; 63 64 uint8_t rx_fifo[8]; 65 unsigned int rx_fifo_pos; 66 unsigned int rx_fifo_len; 67 68 uint32_t regs[R_MAX]; 69 } XilinxUARTLite; 70 71 static void uart_update_irq(XilinxUARTLite *s) 72 { 73 unsigned int irq; 74 75 if (s->rx_fifo_len) 76 s->regs[R_STATUS] |= STATUS_IE; 77 78 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); 79 qemu_set_irq(s->irq, irq); 80 } 81 82 static void uart_update_status(XilinxUARTLite *s) 83 { 84 uint32_t r; 85 86 r = s->regs[R_STATUS]; 87 r &= ~7; 88 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ 89 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; 90 r |= (!!s->rx_fifo_len); 91 s->regs[R_STATUS] = r; 92 } 93 94 static void xilinx_uartlite_reset(DeviceState *dev) 95 { 96 uart_update_status(XILINX_UARTLITE(dev)); 97 } 98 99 static uint64_t 100 uart_read(void *opaque, hwaddr addr, unsigned int size) 101 { 102 XilinxUARTLite *s = opaque; 103 uint32_t r = 0; 104 addr >>= 2; 105 switch (addr) 106 { 107 case R_RX: 108 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; 109 if (s->rx_fifo_len) 110 s->rx_fifo_len--; 111 uart_update_status(s); 112 uart_update_irq(s); 113 qemu_chr_fe_accept_input(&s->chr); 114 break; 115 116 default: 117 if (addr < ARRAY_SIZE(s->regs)) 118 r = s->regs[addr]; 119 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); 120 break; 121 } 122 return r; 123 } 124 125 static void 126 uart_write(void *opaque, hwaddr addr, 127 uint64_t val64, unsigned int size) 128 { 129 XilinxUARTLite *s = opaque; 130 uint32_t value = val64; 131 unsigned char ch = value; 132 133 addr >>= 2; 134 switch (addr) 135 { 136 case R_STATUS: 137 hw_error("write to UART STATUS?\n"); 138 break; 139 140 case R_CTRL: 141 if (value & CONTROL_RST_RX) { 142 s->rx_fifo_pos = 0; 143 s->rx_fifo_len = 0; 144 } 145 s->regs[addr] = value; 146 break; 147 148 case R_TX: 149 /* XXX this blocks entire thread. Rewrite to use 150 * qemu_chr_fe_write and background I/O callbacks */ 151 qemu_chr_fe_write_all(&s->chr, &ch, 1); 152 s->regs[addr] = value; 153 154 /* hax. */ 155 s->regs[R_STATUS] |= STATUS_IE; 156 break; 157 158 default: 159 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); 160 if (addr < ARRAY_SIZE(s->regs)) 161 s->regs[addr] = value; 162 break; 163 } 164 uart_update_status(s); 165 uart_update_irq(s); 166 } 167 168 static const MemoryRegionOps uart_ops = { 169 .read = uart_read, 170 .write = uart_write, 171 .endianness = DEVICE_NATIVE_ENDIAN, 172 .valid = { 173 .min_access_size = 1, 174 .max_access_size = 4 175 } 176 }; 177 178 static Property xilinx_uartlite_properties[] = { 179 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), 180 DEFINE_PROP_END_OF_LIST(), 181 }; 182 183 static void uart_rx(void *opaque, const uint8_t *buf, int size) 184 { 185 XilinxUARTLite *s = opaque; 186 187 /* Got a byte. */ 188 if (s->rx_fifo_len >= 8) { 189 printf("WARNING: UART dropped char.\n"); 190 return; 191 } 192 s->rx_fifo[s->rx_fifo_pos] = *buf; 193 s->rx_fifo_pos++; 194 s->rx_fifo_pos &= 0x7; 195 s->rx_fifo_len++; 196 197 uart_update_status(s); 198 uart_update_irq(s); 199 } 200 201 static int uart_can_rx(void *opaque) 202 { 203 XilinxUARTLite *s = opaque; 204 205 return s->rx_fifo_len < sizeof(s->rx_fifo); 206 } 207 208 static void uart_event(void *opaque, int event) 209 { 210 211 } 212 213 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) 214 { 215 XilinxUARTLite *s = XILINX_UARTLITE(dev); 216 217 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, 218 uart_event, NULL, s, NULL, true); 219 } 220 221 static void xilinx_uartlite_init(Object *obj) 222 { 223 XilinxUARTLite *s = XILINX_UARTLITE(obj); 224 225 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 226 227 memory_region_init_io(&s->mmio, obj, &uart_ops, s, 228 "xlnx.xps-uartlite", R_MAX * 4); 229 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 230 } 231 232 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) 233 { 234 DeviceClass *dc = DEVICE_CLASS(klass); 235 236 dc->reset = xilinx_uartlite_reset; 237 dc->realize = xilinx_uartlite_realize; 238 dc->props = xilinx_uartlite_properties; 239 } 240 241 static const TypeInfo xilinx_uartlite_info = { 242 .name = TYPE_XILINX_UARTLITE, 243 .parent = TYPE_SYS_BUS_DEVICE, 244 .instance_size = sizeof(XilinxUARTLite), 245 .instance_init = xilinx_uartlite_init, 246 .class_init = xilinx_uartlite_class_init, 247 }; 248 249 static void xilinx_uart_register_types(void) 250 { 251 type_register_static(&xilinx_uartlite_info); 252 } 253 254 type_init(xilinx_uart_register_types) 255