1 /* 2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart 13 * by Alistair Francis. 14 * The reference used is the STMicroElectronics RM0351 Reference manual 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "chardev/char-fe.h" 23 #include "chardev/char-serial.h" 24 #include "migration/vmstate.h" 25 #include "hw/char/stm32l4x5_usart.h" 26 #include "hw/clock.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-clock.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/registerfields.h" 32 #include "trace.h" 33 34 35 REG32(CR1, 0x00) 36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ 37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ 38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ 39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ 40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ 41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ 42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ 43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */ 44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ 45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ 46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */ 47 FIELD(CR1, PS, 9, 1) /* Parity selection */ 48 FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ 49 FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ 50 FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ 51 FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ 52 FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ 53 FIELD(CR1, TE, 3, 1) /* Transmitter enable */ 54 FIELD(CR1, RE, 2, 1) /* Receiver enable */ 55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ 56 FIELD(CR1, UE, 0, 1) /* USART enable */ 57 REG32(CR2, 0x04) 58 FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ 59 FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */ 60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ 61 FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ 62 FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ 63 FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ 64 FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ 65 FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ 66 FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ 67 FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ 68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ 69 FIELD(CR2, STOP, 12, 2) /* STOP bits */ 70 FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ 71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ 72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */ 73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ 74 FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ 75 FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ 76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ 77 78 REG32(CR3, 0x08) 79 /* TCBGTIE only on STM32L496xx/4A6xx devices */ 80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ 81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ 82 FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ 83 FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ 84 FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ 85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ 86 FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ 87 FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ 88 FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ 89 FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ 90 FIELD(CR3, CTSE, 9, 1) /* CTS enable */ 91 FIELD(CR3, RTSE, 8, 1) /* RTS enable */ 92 FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ 93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ 94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ 95 FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ 96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ 97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ 98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ 99 FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ 100 REG32(BRR, 0x0C) 101 FIELD(BRR, BRR, 0, 16) 102 REG32(GTPR, 0x10) 103 FIELD(GTPR, GT, 8, 8) /* Guard time value */ 104 FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ 105 REG32(RTOR, 0x14) 106 FIELD(RTOR, BLEN, 24, 8) /* Block Length */ 107 FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ 108 REG32(RQR, 0x18) 109 FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ 110 FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ 111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ 112 FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ 113 FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ 114 REG32(ISR, 0x1C) 115 /* TCBGT only for STM32L475xx/476xx/486xx devices */ 116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ 117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ 118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ 119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ 120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */ 121 FIELD(ISR, CMF, 17, 1) /* Character match flag */ 122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */ 123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ 124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ 125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */ 126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ 127 FIELD(ISR, CTS, 10, 1) /* CTS flag */ 128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ 129 FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ 130 FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ 131 FIELD(ISR, TC, 6, 1) /* Transmission complete */ 132 FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ 133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ 134 FIELD(ISR, ORE, 3, 1) /* Overrun error */ 135 FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ 136 FIELD(ISR, FE, 1, 1) /* Framing Error */ 137 FIELD(ISR, PE, 0, 1) /* Parity Error */ 138 REG32(ICR, 0x20) 139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ 140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ 141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ 142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ 143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ 144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ 145 /* TCBGTCF only on STM32L496xx/4A6xx devices */ 146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ 147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ 148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ 149 FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ 150 FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ 151 FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ 152 REG32(RDR, 0x24) 153 FIELD(RDR, RDR, 0, 9) 154 REG32(TDR, 0x28) 155 FIELD(TDR, TDR, 0, 9) 156 157 static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) 158 { 159 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || 160 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || 161 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 162 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || 163 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || 164 ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || 165 ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || 166 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || 167 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || 168 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 169 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || 170 ((s->isr & R_ISR_ORE_MASK) && 171 ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || 172 /* TODO: Handle NF ? */ 173 ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || 174 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { 175 qemu_irq_raise(s->irq); 176 trace_stm32l4x5_usart_irq_raised(s->isr); 177 } else { 178 qemu_irq_lower(s->irq); 179 trace_stm32l4x5_usart_irq_lowered(); 180 } 181 } 182 183 static int stm32l4x5_usart_base_can_receive(void *opaque) 184 { 185 Stm32l4x5UsartBaseState *s = opaque; 186 187 if (!(s->isr & R_ISR_RXNE_MASK)) { 188 return 1; 189 } 190 191 return 0; 192 } 193 194 static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, 195 int size) 196 { 197 Stm32l4x5UsartBaseState *s = opaque; 198 199 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { 200 trace_stm32l4x5_usart_receiver_not_enabled( 201 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); 202 return; 203 } 204 205 /* Check if overrun detection is enabled and if there is an overrun */ 206 if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { 207 /* 208 * A character has been received while 209 * the previous has not been read = Overrun. 210 */ 211 s->isr |= R_ISR_ORE_MASK; 212 trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); 213 } else { 214 /* No overrun */ 215 s->rdr = *buf; 216 s->isr |= R_ISR_RXNE_MASK; 217 trace_stm32l4x5_usart_rx(s->rdr); 218 } 219 220 stm32l4x5_update_irq(s); 221 } 222 223 /* 224 * Try to send tx data, and arrange to be called back later if 225 * we can't (ie the char backend is busy/blocking). 226 */ 227 static gboolean usart_transmit(void *do_not_use, GIOCondition cond, 228 void *opaque) 229 { 230 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque); 231 int ret; 232 /* TODO: Handle 9 bits transmission */ 233 uint8_t ch = s->tdr; 234 235 s->watch_tag = 0; 236 237 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { 238 return G_SOURCE_REMOVE; 239 } 240 241 ret = qemu_chr_fe_write(&s->chr, &ch, 1); 242 if (ret <= 0) { 243 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 244 usart_transmit, s); 245 if (!s->watch_tag) { 246 /* 247 * Most common reason to be here is "no chardev backend": 248 * just insta-drain the buffer, so the serial output 249 * goes into a void, rather than blocking the guest. 250 */ 251 goto buffer_drained; 252 } 253 /* Transmit pending */ 254 trace_stm32l4x5_usart_tx_pending(); 255 return G_SOURCE_REMOVE; 256 } 257 258 buffer_drained: 259 /* Character successfully sent */ 260 trace_stm32l4x5_usart_tx(ch); 261 s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; 262 stm32l4x5_update_irq(s); 263 return G_SOURCE_REMOVE; 264 } 265 266 static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) 267 { 268 if (s->watch_tag) { 269 g_source_remove(s->watch_tag); 270 s->watch_tag = 0; 271 } 272 } 273 274 static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) 275 { 276 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 277 278 s->cr1 = 0x00000000; 279 s->cr2 = 0x00000000; 280 s->cr3 = 0x00000000; 281 s->brr = 0x00000000; 282 s->gtpr = 0x00000000; 283 s->rtor = 0x00000000; 284 s->isr = 0x020000C0; 285 s->rdr = 0x00000000; 286 s->tdr = 0x00000000; 287 288 usart_cancel_transmit(s); 289 stm32l4x5_update_irq(s); 290 } 291 292 static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) 293 { 294 /* TXFRQ */ 295 /* Reset RXNE flag */ 296 if (value & R_RQR_RXFRQ_MASK) { 297 s->isr &= ~R_ISR_RXNE_MASK; 298 } 299 /* MMRQ */ 300 /* SBKRQ */ 301 /* ABRRQ */ 302 stm32l4x5_update_irq(s); 303 } 304 305 static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, 306 unsigned int size) 307 { 308 Stm32l4x5UsartBaseState *s = opaque; 309 uint64_t retvalue = 0; 310 311 switch (addr) { 312 case A_CR1: 313 retvalue = s->cr1; 314 break; 315 case A_CR2: 316 retvalue = s->cr2; 317 break; 318 case A_CR3: 319 retvalue = s->cr3; 320 break; 321 case A_BRR: 322 retvalue = FIELD_EX32(s->brr, BRR, BRR); 323 break; 324 case A_GTPR: 325 retvalue = s->gtpr; 326 break; 327 case A_RTOR: 328 retvalue = s->rtor; 329 break; 330 case A_RQR: 331 /* RQR is a write only register */ 332 retvalue = 0x00000000; 333 break; 334 case A_ISR: 335 retvalue = s->isr; 336 break; 337 case A_ICR: 338 /* ICR is a clear register */ 339 retvalue = 0x00000000; 340 break; 341 case A_RDR: 342 retvalue = FIELD_EX32(s->rdr, RDR, RDR); 343 /* Reset RXNE flag */ 344 s->isr &= ~R_ISR_RXNE_MASK; 345 stm32l4x5_update_irq(s); 346 break; 347 case A_TDR: 348 retvalue = FIELD_EX32(s->tdr, TDR, TDR); 349 break; 350 default: 351 qemu_log_mask(LOG_GUEST_ERROR, 352 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 353 break; 354 } 355 356 trace_stm32l4x5_usart_read(addr, retvalue); 357 358 return retvalue; 359 } 360 361 static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, 362 uint64_t val64, unsigned int size) 363 { 364 Stm32l4x5UsartBaseState *s = opaque; 365 const uint32_t value = val64; 366 367 trace_stm32l4x5_usart_write(addr, value); 368 369 switch (addr) { 370 case A_CR1: 371 s->cr1 = value; 372 stm32l4x5_update_irq(s); 373 return; 374 case A_CR2: 375 s->cr2 = value; 376 return; 377 case A_CR3: 378 s->cr3 = value; 379 return; 380 case A_BRR: 381 s->brr = value; 382 return; 383 case A_GTPR: 384 s->gtpr = value; 385 return; 386 case A_RTOR: 387 s->rtor = value; 388 return; 389 case A_RQR: 390 usart_update_rqr(s, value); 391 return; 392 case A_ISR: 393 qemu_log_mask(LOG_GUEST_ERROR, 394 "%s: ISR is read only !\n", __func__); 395 return; 396 case A_ICR: 397 /* Clear the status flags */ 398 s->isr &= ~value; 399 stm32l4x5_update_irq(s); 400 return; 401 case A_RDR: 402 qemu_log_mask(LOG_GUEST_ERROR, 403 "%s: RDR is read only !\n", __func__); 404 return; 405 case A_TDR: 406 s->tdr = value; 407 s->isr &= ~R_ISR_TXE_MASK; 408 usart_transmit(NULL, G_IO_OUT, s); 409 return; 410 default: 411 qemu_log_mask(LOG_GUEST_ERROR, 412 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 413 } 414 } 415 416 static const MemoryRegionOps stm32l4x5_usart_base_ops = { 417 .read = stm32l4x5_usart_base_read, 418 .write = stm32l4x5_usart_base_write, 419 .endianness = DEVICE_NATIVE_ENDIAN, 420 .valid = { 421 .max_access_size = 4, 422 .min_access_size = 4, 423 .unaligned = false 424 }, 425 .impl = { 426 .max_access_size = 4, 427 .min_access_size = 4, 428 .unaligned = false 429 }, 430 }; 431 432 static Property stm32l4x5_usart_base_properties[] = { 433 DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), 434 DEFINE_PROP_END_OF_LIST(), 435 }; 436 437 static void stm32l4x5_usart_base_init(Object *obj) 438 { 439 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 440 441 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 442 443 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, 444 TYPE_STM32L4X5_USART_BASE, 0x400); 445 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 446 447 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); 448 } 449 450 static const VMStateDescription vmstate_stm32l4x5_usart_base = { 451 .name = TYPE_STM32L4X5_USART_BASE, 452 .version_id = 1, 453 .minimum_version_id = 1, 454 .fields = (VMStateField[]) { 455 VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), 456 VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), 457 VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), 458 VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), 459 VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), 460 VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), 461 VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), 462 VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), 463 VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), 464 VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), 465 VMSTATE_END_OF_LIST() 466 } 467 }; 468 469 470 static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) 471 { 472 ERRP_GUARD(); 473 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); 474 if (!clock_has_source(s->clk)) { 475 error_setg(errp, "USART clock must be wired up by SoC code"); 476 return; 477 } 478 479 qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, 480 stm32l4x5_usart_base_receive, NULL, NULL, 481 s, NULL, true); 482 } 483 484 static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) 485 { 486 DeviceClass *dc = DEVICE_CLASS(klass); 487 ResettableClass *rc = RESETTABLE_CLASS(klass); 488 489 rc->phases.hold = stm32l4x5_usart_base_reset_hold; 490 device_class_set_props(dc, stm32l4x5_usart_base_properties); 491 dc->realize = stm32l4x5_usart_base_realize; 492 dc->vmsd = &vmstate_stm32l4x5_usart_base; 493 } 494 495 static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) 496 { 497 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 498 499 subc->type = STM32L4x5_USART; 500 } 501 502 static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) 503 { 504 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 505 506 subc->type = STM32L4x5_UART; 507 } 508 509 static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) 510 { 511 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 512 513 subc->type = STM32L4x5_LPUART; 514 } 515 516 static const TypeInfo stm32l4x5_usart_types[] = { 517 { 518 .name = TYPE_STM32L4X5_USART_BASE, 519 .parent = TYPE_SYS_BUS_DEVICE, 520 .instance_size = sizeof(Stm32l4x5UsartBaseState), 521 .instance_init = stm32l4x5_usart_base_init, 522 .class_init = stm32l4x5_usart_base_class_init, 523 .abstract = true, 524 }, { 525 .name = TYPE_STM32L4X5_USART, 526 .parent = TYPE_STM32L4X5_USART_BASE, 527 .class_init = stm32l4x5_usart_class_init, 528 }, { 529 .name = TYPE_STM32L4X5_UART, 530 .parent = TYPE_STM32L4X5_USART_BASE, 531 .class_init = stm32l4x5_uart_class_init, 532 }, { 533 .name = TYPE_STM32L4X5_LPUART, 534 .parent = TYPE_STM32L4X5_USART_BASE, 535 .class_init = stm32l4x5_lpuart_class_init, 536 } 537 }; 538 539 DEFINE_TYPES(stm32l4x5_usart_types) 540