1 /* 2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart 13 * by Alistair Francis. 14 * The reference used is the STMicroElectronics RM0351 Reference manual 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "chardev/char-fe.h" 23 #include "chardev/char-serial.h" 24 #include "migration/vmstate.h" 25 #include "hw/char/stm32l4x5_usart.h" 26 #include "hw/clock.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-clock.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/registerfields.h" 32 #include "trace.h" 33 34 35 REG32(CR1, 0x00) 36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ 37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ 38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ 39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ 40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ 41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ 42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ 43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */ 44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ 45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ 46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */ 47 FIELD(CR1, PS, 9, 1) /* Parity selection */ 48 FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ 49 FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ 50 FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ 51 FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ 52 FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ 53 FIELD(CR1, TE, 3, 1) /* Transmitter enable */ 54 FIELD(CR1, RE, 2, 1) /* Receiver enable */ 55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ 56 FIELD(CR1, UE, 0, 1) /* USART enable */ 57 REG32(CR2, 0x04) 58 FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ 59 FIELD(CR2, ADD_0, 24, 4) /* ADD[3:0] */ 60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ 61 FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ 62 FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ 63 FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ 64 FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ 65 FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ 66 FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ 67 FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ 68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ 69 FIELD(CR2, STOP, 12, 2) /* STOP bits */ 70 FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ 71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ 72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */ 73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ 74 FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ 75 FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ 76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ 77 78 REG32(CR3, 0x08) 79 /* TCBGTIE only on STM32L496xx/4A6xx devices */ 80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ 81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ 82 FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ 83 FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ 84 FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ 85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ 86 FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ 87 FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ 88 FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ 89 FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ 90 FIELD(CR3, CTSE, 9, 1) /* CTS enable */ 91 FIELD(CR3, RTSE, 8, 1) /* RTS enable */ 92 FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ 93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ 94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ 95 FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ 96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ 97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ 98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ 99 FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ 100 REG32(BRR, 0x0C) 101 FIELD(BRR, BRR, 0, 16) 102 REG32(GTPR, 0x10) 103 FIELD(GTPR, GT, 8, 8) /* Guard time value */ 104 FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ 105 REG32(RTOR, 0x14) 106 FIELD(RTOR, BLEN, 24, 8) /* Block Length */ 107 FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ 108 REG32(RQR, 0x18) 109 FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ 110 FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ 111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ 112 FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ 113 FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ 114 REG32(ISR, 0x1C) 115 /* TCBGT only for STM32L475xx/476xx/486xx devices */ 116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ 117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ 118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ 119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ 120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */ 121 FIELD(ISR, CMF, 17, 1) /* Character match flag */ 122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */ 123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ 124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ 125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */ 126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ 127 FIELD(ISR, CTS, 10, 1) /* CTS flag */ 128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ 129 FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ 130 FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ 131 FIELD(ISR, TC, 6, 1) /* Transmission complete */ 132 FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ 133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ 134 FIELD(ISR, ORE, 3, 1) /* Overrun error */ 135 FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ 136 FIELD(ISR, FE, 1, 1) /* Framing Error */ 137 FIELD(ISR, PE, 0, 1) /* Parity Error */ 138 REG32(ICR, 0x20) 139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ 140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ 141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ 142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ 143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ 144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ 145 /* TCBGTCF only on STM32L496xx/4A6xx devices */ 146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ 147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ 148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ 149 FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ 150 FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ 151 FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ 152 REG32(RDR, 0x24) 153 FIELD(RDR, RDR, 0, 9) 154 REG32(TDR, 0x28) 155 FIELD(TDR, TDR, 0, 9) 156 157 static void stm32l4x5_update_isr(Stm32l4x5UsartBaseState *s) 158 { 159 if (s->cr1 & R_CR1_TE_MASK) { 160 s->isr |= R_ISR_TEACK_MASK; 161 } else { 162 s->isr &= ~R_ISR_TEACK_MASK; 163 } 164 165 if (s->cr1 & R_CR1_RE_MASK) { 166 s->isr |= R_ISR_REACK_MASK; 167 } else { 168 s->isr &= ~R_ISR_REACK_MASK; 169 } 170 } 171 172 static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) 173 { 174 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || 175 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || 176 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 177 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || 178 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || 179 ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || 180 ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || 181 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || 182 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || 183 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 184 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || 185 ((s->isr & R_ISR_ORE_MASK) && 186 ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || 187 /* TODO: Handle NF ? */ 188 ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || 189 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { 190 qemu_irq_raise(s->irq); 191 trace_stm32l4x5_usart_irq_raised(s->isr); 192 } else { 193 qemu_irq_lower(s->irq); 194 trace_stm32l4x5_usart_irq_lowered(); 195 } 196 } 197 198 static int stm32l4x5_usart_base_can_receive(void *opaque) 199 { 200 Stm32l4x5UsartBaseState *s = opaque; 201 202 if (!(s->isr & R_ISR_RXNE_MASK)) { 203 return 1; 204 } 205 206 return 0; 207 } 208 209 static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, 210 int size) 211 { 212 Stm32l4x5UsartBaseState *s = opaque; 213 214 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { 215 trace_stm32l4x5_usart_receiver_not_enabled( 216 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); 217 return; 218 } 219 220 /* Check if overrun detection is enabled and if there is an overrun */ 221 if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { 222 /* 223 * A character has been received while 224 * the previous has not been read = Overrun. 225 */ 226 s->isr |= R_ISR_ORE_MASK; 227 trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); 228 } else { 229 /* No overrun */ 230 s->rdr = *buf; 231 s->isr |= R_ISR_RXNE_MASK; 232 trace_stm32l4x5_usart_rx(s->rdr); 233 } 234 235 stm32l4x5_update_irq(s); 236 } 237 238 /* 239 * Try to send tx data, and arrange to be called back later if 240 * we can't (ie the char backend is busy/blocking). 241 */ 242 static gboolean usart_transmit(void *do_not_use, GIOCondition cond, 243 void *opaque) 244 { 245 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque); 246 int ret; 247 /* TODO: Handle 9 bits transmission */ 248 uint8_t ch = s->tdr; 249 250 s->watch_tag = 0; 251 252 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { 253 return G_SOURCE_REMOVE; 254 } 255 256 ret = qemu_chr_fe_write(&s->chr, &ch, 1); 257 if (ret <= 0) { 258 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 259 usart_transmit, s); 260 if (!s->watch_tag) { 261 /* 262 * Most common reason to be here is "no chardev backend": 263 * just insta-drain the buffer, so the serial output 264 * goes into a void, rather than blocking the guest. 265 */ 266 goto buffer_drained; 267 } 268 /* Transmit pending */ 269 trace_stm32l4x5_usart_tx_pending(); 270 return G_SOURCE_REMOVE; 271 } 272 273 buffer_drained: 274 /* Character successfully sent */ 275 trace_stm32l4x5_usart_tx(ch); 276 s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; 277 stm32l4x5_update_irq(s); 278 return G_SOURCE_REMOVE; 279 } 280 281 static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) 282 { 283 if (s->watch_tag) { 284 g_source_remove(s->watch_tag); 285 s->watch_tag = 0; 286 } 287 } 288 289 static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s) 290 { 291 int speed, parity, data_bits, stop_bits; 292 uint32_t value, usart_div; 293 QEMUSerialSetParams ssp; 294 295 /* Select the parity type */ 296 if (s->cr1 & R_CR1_PCE_MASK) { 297 if (s->cr1 & R_CR1_PS_MASK) { 298 parity = 'O'; 299 } else { 300 parity = 'E'; 301 } 302 } else { 303 parity = 'N'; 304 } 305 306 /* Select the number of stop bits */ 307 switch (FIELD_EX32(s->cr2, CR2, STOP)) { 308 case 0: 309 stop_bits = 1; 310 break; 311 case 2: 312 stop_bits = 2; 313 break; 314 default: 315 qemu_log_mask(LOG_UNIMP, 316 "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u", 317 FIELD_EX32(s->cr2, CR2, STOP)); 318 return; 319 } 320 321 /* Select the length of the word */ 322 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { 323 case 0: 324 data_bits = 8; 325 break; 326 case 1: 327 data_bits = 9; 328 break; 329 case 2: 330 data_bits = 7; 331 break; 332 default: 333 qemu_log_mask(LOG_GUEST_ERROR, 334 "UNDEFINED: invalid word length, CR1.M = 0b11"); 335 return; 336 } 337 338 /* Select the baud rate */ 339 value = FIELD_EX32(s->brr, BRR, BRR); 340 if (value < 16) { 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "UNDEFINED: BRR less than 16: %u", value); 343 return; 344 } 345 346 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { 347 /* 348 * Oversampling by 16 349 * BRR = USARTDIV 350 */ 351 usart_div = value; 352 } else { 353 /* 354 * Oversampling by 8 355 * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. 356 * - BRR[3] must be kept cleared. 357 * - BRR[15:4] = USARTDIV[15:4] 358 * - The frequency is multiplied by 2 359 */ 360 usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; 361 } 362 363 speed = clock_get_hz(s->clk) / usart_div; 364 365 ssp.speed = speed; 366 ssp.parity = parity; 367 ssp.data_bits = data_bits; 368 ssp.stop_bits = stop_bits; 369 370 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 371 372 trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bits); 373 } 374 375 static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) 376 { 377 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 378 379 s->cr1 = 0x00000000; 380 s->cr2 = 0x00000000; 381 s->cr3 = 0x00000000; 382 s->brr = 0x00000000; 383 s->gtpr = 0x00000000; 384 s->rtor = 0x00000000; 385 s->isr = 0x020000C0; 386 s->rdr = 0x00000000; 387 s->tdr = 0x00000000; 388 389 usart_cancel_transmit(s); 390 stm32l4x5_update_irq(s); 391 } 392 393 static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) 394 { 395 /* TXFRQ */ 396 /* Reset RXNE flag */ 397 if (value & R_RQR_RXFRQ_MASK) { 398 s->isr &= ~R_ISR_RXNE_MASK; 399 } 400 /* MMRQ */ 401 /* SBKRQ */ 402 /* ABRRQ */ 403 stm32l4x5_update_irq(s); 404 } 405 406 static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, 407 unsigned int size) 408 { 409 Stm32l4x5UsartBaseState *s = opaque; 410 uint64_t retvalue = 0; 411 412 switch (addr) { 413 case A_CR1: 414 retvalue = s->cr1; 415 break; 416 case A_CR2: 417 retvalue = s->cr2; 418 break; 419 case A_CR3: 420 retvalue = s->cr3; 421 break; 422 case A_BRR: 423 retvalue = FIELD_EX32(s->brr, BRR, BRR); 424 break; 425 case A_GTPR: 426 retvalue = s->gtpr; 427 break; 428 case A_RTOR: 429 retvalue = s->rtor; 430 break; 431 case A_RQR: 432 /* RQR is a write only register */ 433 retvalue = 0x00000000; 434 break; 435 case A_ISR: 436 retvalue = s->isr; 437 break; 438 case A_ICR: 439 /* ICR is a clear register */ 440 retvalue = 0x00000000; 441 break; 442 case A_RDR: 443 retvalue = FIELD_EX32(s->rdr, RDR, RDR); 444 /* Reset RXNE flag */ 445 s->isr &= ~R_ISR_RXNE_MASK; 446 stm32l4x5_update_irq(s); 447 break; 448 case A_TDR: 449 retvalue = FIELD_EX32(s->tdr, TDR, TDR); 450 break; 451 default: 452 qemu_log_mask(LOG_GUEST_ERROR, 453 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 454 break; 455 } 456 457 trace_stm32l4x5_usart_read(addr, retvalue); 458 459 return retvalue; 460 } 461 462 static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, 463 uint64_t val64, unsigned int size) 464 { 465 Stm32l4x5UsartBaseState *s = opaque; 466 const uint32_t value = val64; 467 468 trace_stm32l4x5_usart_write(addr, value); 469 470 switch (addr) { 471 case A_CR1: 472 s->cr1 = value; 473 stm32l4x5_update_params(s); 474 stm32l4x5_update_isr(s); 475 stm32l4x5_update_irq(s); 476 return; 477 case A_CR2: 478 s->cr2 = value; 479 stm32l4x5_update_params(s); 480 return; 481 case A_CR3: 482 s->cr3 = value; 483 return; 484 case A_BRR: 485 s->brr = value; 486 stm32l4x5_update_params(s); 487 return; 488 case A_GTPR: 489 s->gtpr = value; 490 return; 491 case A_RTOR: 492 s->rtor = value; 493 return; 494 case A_RQR: 495 usart_update_rqr(s, value); 496 return; 497 case A_ISR: 498 qemu_log_mask(LOG_GUEST_ERROR, 499 "%s: ISR is read only !\n", __func__); 500 return; 501 case A_ICR: 502 /* Clear the status flags */ 503 s->isr &= ~value; 504 stm32l4x5_update_irq(s); 505 return; 506 case A_RDR: 507 qemu_log_mask(LOG_GUEST_ERROR, 508 "%s: RDR is read only !\n", __func__); 509 return; 510 case A_TDR: 511 s->tdr = value; 512 s->isr &= ~R_ISR_TXE_MASK; 513 usart_transmit(NULL, G_IO_OUT, s); 514 return; 515 default: 516 qemu_log_mask(LOG_GUEST_ERROR, 517 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 518 } 519 } 520 521 static const MemoryRegionOps stm32l4x5_usart_base_ops = { 522 .read = stm32l4x5_usart_base_read, 523 .write = stm32l4x5_usart_base_write, 524 .endianness = DEVICE_NATIVE_ENDIAN, 525 .valid = { 526 .max_access_size = 4, 527 .min_access_size = 4, 528 .unaligned = false 529 }, 530 .impl = { 531 .max_access_size = 4, 532 .min_access_size = 4, 533 .unaligned = false 534 }, 535 }; 536 537 static Property stm32l4x5_usart_base_properties[] = { 538 DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), 539 DEFINE_PROP_END_OF_LIST(), 540 }; 541 542 static void stm32l4x5_usart_base_init(Object *obj) 543 { 544 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 545 546 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 547 548 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, 549 TYPE_STM32L4X5_USART_BASE, 0x400); 550 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 551 552 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); 553 } 554 555 static int stm32l4x5_usart_base_post_load(void *opaque, int version_id) 556 { 557 Stm32l4x5UsartBaseState *s = (Stm32l4x5UsartBaseState *)opaque; 558 559 stm32l4x5_update_params(s); 560 return 0; 561 } 562 563 static const VMStateDescription vmstate_stm32l4x5_usart_base = { 564 .name = TYPE_STM32L4X5_USART_BASE, 565 .version_id = 1, 566 .minimum_version_id = 1, 567 .post_load = stm32l4x5_usart_base_post_load, 568 .fields = (VMStateField[]) { 569 VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), 570 VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), 571 VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), 572 VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), 573 VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), 574 VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), 575 VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), 576 VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), 577 VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), 578 VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), 579 VMSTATE_END_OF_LIST() 580 } 581 }; 582 583 584 static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) 585 { 586 ERRP_GUARD(); 587 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); 588 if (!clock_has_source(s->clk)) { 589 error_setg(errp, "USART clock must be wired up by SoC code"); 590 return; 591 } 592 593 qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, 594 stm32l4x5_usart_base_receive, NULL, NULL, 595 s, NULL, true); 596 } 597 598 static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) 599 { 600 DeviceClass *dc = DEVICE_CLASS(klass); 601 ResettableClass *rc = RESETTABLE_CLASS(klass); 602 603 rc->phases.hold = stm32l4x5_usart_base_reset_hold; 604 device_class_set_props(dc, stm32l4x5_usart_base_properties); 605 dc->realize = stm32l4x5_usart_base_realize; 606 dc->vmsd = &vmstate_stm32l4x5_usart_base; 607 } 608 609 static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) 610 { 611 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 612 613 subc->type = STM32L4x5_USART; 614 } 615 616 static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) 617 { 618 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 619 620 subc->type = STM32L4x5_UART; 621 } 622 623 static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) 624 { 625 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 626 627 subc->type = STM32L4x5_LPUART; 628 } 629 630 static const TypeInfo stm32l4x5_usart_types[] = { 631 { 632 .name = TYPE_STM32L4X5_USART_BASE, 633 .parent = TYPE_SYS_BUS_DEVICE, 634 .instance_size = sizeof(Stm32l4x5UsartBaseState), 635 .instance_init = stm32l4x5_usart_base_init, 636 .class_size = sizeof(Stm32l4x5UsartBaseClass), 637 .class_init = stm32l4x5_usart_base_class_init, 638 .abstract = true, 639 }, { 640 .name = TYPE_STM32L4X5_USART, 641 .parent = TYPE_STM32L4X5_USART_BASE, 642 .class_init = stm32l4x5_usart_class_init, 643 }, { 644 .name = TYPE_STM32L4X5_UART, 645 .parent = TYPE_STM32L4X5_USART_BASE, 646 .class_init = stm32l4x5_uart_class_init, 647 }, { 648 .name = TYPE_STM32L4X5_LPUART, 649 .parent = TYPE_STM32L4X5_USART_BASE, 650 .class_init = stm32l4x5_lpuart_class_init, 651 } 652 }; 653 654 DEFINE_TYPES(stm32l4x5_usart_types) 655