1 /* 2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart 13 * by Alistair Francis. 14 * The reference used is the STMicroElectronics RM0351 Reference manual 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "chardev/char-fe.h" 23 #include "chardev/char-serial.h" 24 #include "migration/vmstate.h" 25 #include "hw/char/stm32l4x5_usart.h" 26 #include "hw/clock.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-clock.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/registerfields.h" 32 #include "trace.h" 33 34 35 REG32(CR1, 0x00) 36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ 37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ 38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ 39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ 40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ 41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ 42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ 43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */ 44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ 45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ 46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */ 47 FIELD(CR1, PS, 9, 1) /* Parity selection */ 48 FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ 49 FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ 50 FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ 51 FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ 52 FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ 53 FIELD(CR1, TE, 3, 1) /* Transmitter enable */ 54 FIELD(CR1, RE, 2, 1) /* Receiver enable */ 55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ 56 FIELD(CR1, UE, 0, 1) /* USART enable */ 57 REG32(CR2, 0x04) 58 FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ 59 FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */ 60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ 61 FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ 62 FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ 63 FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ 64 FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ 65 FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ 66 FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ 67 FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ 68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ 69 FIELD(CR2, STOP, 12, 2) /* STOP bits */ 70 FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ 71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ 72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */ 73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ 74 FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ 75 FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ 76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ 77 78 REG32(CR3, 0x08) 79 /* TCBGTIE only on STM32L496xx/4A6xx devices */ 80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ 81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ 82 FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ 83 FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ 84 FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ 85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ 86 FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ 87 FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ 88 FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ 89 FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ 90 FIELD(CR3, CTSE, 9, 1) /* CTS enable */ 91 FIELD(CR3, RTSE, 8, 1) /* RTS enable */ 92 FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ 93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ 94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ 95 FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ 96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ 97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ 98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ 99 FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ 100 REG32(BRR, 0x0C) 101 FIELD(BRR, BRR, 0, 16) 102 REG32(GTPR, 0x10) 103 FIELD(GTPR, GT, 8, 8) /* Guard time value */ 104 FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ 105 REG32(RTOR, 0x14) 106 FIELD(RTOR, BLEN, 24, 8) /* Block Length */ 107 FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ 108 REG32(RQR, 0x18) 109 FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ 110 FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ 111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ 112 FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ 113 FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ 114 REG32(ISR, 0x1C) 115 /* TCBGT only for STM32L475xx/476xx/486xx devices */ 116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ 117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ 118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ 119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ 120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */ 121 FIELD(ISR, CMF, 17, 1) /* Character match flag */ 122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */ 123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ 124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ 125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */ 126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ 127 FIELD(ISR, CTS, 10, 1) /* CTS flag */ 128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ 129 FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ 130 FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ 131 FIELD(ISR, TC, 6, 1) /* Transmission complete */ 132 FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ 133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ 134 FIELD(ISR, ORE, 3, 1) /* Overrun error */ 135 FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ 136 FIELD(ISR, FE, 1, 1) /* Framing Error */ 137 FIELD(ISR, PE, 0, 1) /* Parity Error */ 138 REG32(ICR, 0x20) 139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ 140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ 141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ 142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ 143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ 144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ 145 /* TCBGTCF only on STM32L496xx/4A6xx devices */ 146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ 147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ 148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ 149 FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ 150 FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ 151 FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ 152 REG32(RDR, 0x24) 153 FIELD(RDR, RDR, 0, 9) 154 REG32(TDR, 0x28) 155 FIELD(TDR, TDR, 0, 9) 156 157 static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) 158 { 159 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 160 161 s->cr1 = 0x00000000; 162 s->cr2 = 0x00000000; 163 s->cr3 = 0x00000000; 164 s->brr = 0x00000000; 165 s->gtpr = 0x00000000; 166 s->rtor = 0x00000000; 167 s->isr = 0x020000C0; 168 s->rdr = 0x00000000; 169 s->tdr = 0x00000000; 170 } 171 172 static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, 173 unsigned int size) 174 { 175 Stm32l4x5UsartBaseState *s = opaque; 176 uint64_t retvalue = 0; 177 178 switch (addr) { 179 case A_CR1: 180 retvalue = s->cr1; 181 break; 182 case A_CR2: 183 retvalue = s->cr2; 184 break; 185 case A_CR3: 186 retvalue = s->cr3; 187 break; 188 case A_BRR: 189 retvalue = FIELD_EX32(s->brr, BRR, BRR); 190 break; 191 case A_GTPR: 192 retvalue = s->gtpr; 193 break; 194 case A_RTOR: 195 retvalue = s->rtor; 196 break; 197 case A_RQR: 198 /* RQR is a write only register */ 199 retvalue = 0x00000000; 200 break; 201 case A_ISR: 202 retvalue = s->isr; 203 break; 204 case A_ICR: 205 /* ICR is a clear register */ 206 retvalue = 0x00000000; 207 break; 208 case A_RDR: 209 retvalue = FIELD_EX32(s->rdr, RDR, RDR); 210 /* Reset RXNE flag */ 211 s->isr &= ~R_ISR_RXNE_MASK; 212 break; 213 case A_TDR: 214 retvalue = FIELD_EX32(s->tdr, TDR, TDR); 215 break; 216 default: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 219 break; 220 } 221 222 trace_stm32l4x5_usart_read(addr, retvalue); 223 224 return retvalue; 225 } 226 227 static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, 228 uint64_t val64, unsigned int size) 229 { 230 Stm32l4x5UsartBaseState *s = opaque; 231 const uint32_t value = val64; 232 233 trace_stm32l4x5_usart_write(addr, value); 234 235 switch (addr) { 236 case A_CR1: 237 s->cr1 = value; 238 return; 239 case A_CR2: 240 s->cr2 = value; 241 return; 242 case A_CR3: 243 s->cr3 = value; 244 return; 245 case A_BRR: 246 s->brr = value; 247 return; 248 case A_GTPR: 249 s->gtpr = value; 250 return; 251 case A_RTOR: 252 s->rtor = value; 253 return; 254 case A_RQR: 255 return; 256 case A_ISR: 257 qemu_log_mask(LOG_GUEST_ERROR, 258 "%s: ISR is read only !\n", __func__); 259 return; 260 case A_ICR: 261 /* Clear the status flags */ 262 s->isr &= ~value; 263 return; 264 case A_RDR: 265 qemu_log_mask(LOG_GUEST_ERROR, 266 "%s: RDR is read only !\n", __func__); 267 return; 268 case A_TDR: 269 s->tdr = value; 270 return; 271 default: 272 qemu_log_mask(LOG_GUEST_ERROR, 273 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 274 } 275 } 276 277 static const MemoryRegionOps stm32l4x5_usart_base_ops = { 278 .read = stm32l4x5_usart_base_read, 279 .write = stm32l4x5_usart_base_write, 280 .endianness = DEVICE_NATIVE_ENDIAN, 281 .valid = { 282 .max_access_size = 4, 283 .min_access_size = 4, 284 .unaligned = false 285 }, 286 .impl = { 287 .max_access_size = 4, 288 .min_access_size = 4, 289 .unaligned = false 290 }, 291 }; 292 293 static Property stm32l4x5_usart_base_properties[] = { 294 DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), 295 DEFINE_PROP_END_OF_LIST(), 296 }; 297 298 static void stm32l4x5_usart_base_init(Object *obj) 299 { 300 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 301 302 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 303 304 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, 305 TYPE_STM32L4X5_USART_BASE, 0x400); 306 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 307 308 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); 309 } 310 311 static const VMStateDescription vmstate_stm32l4x5_usart_base = { 312 .name = TYPE_STM32L4X5_USART_BASE, 313 .version_id = 1, 314 .minimum_version_id = 1, 315 .fields = (VMStateField[]) { 316 VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), 317 VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), 318 VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), 319 VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), 320 VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), 321 VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), 322 VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), 323 VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), 324 VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), 325 VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), 326 VMSTATE_END_OF_LIST() 327 } 328 }; 329 330 331 static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) 332 { 333 ERRP_GUARD(); 334 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); 335 if (!clock_has_source(s->clk)) { 336 error_setg(errp, "USART clock must be wired up by SoC code"); 337 return; 338 } 339 } 340 341 static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) 342 { 343 DeviceClass *dc = DEVICE_CLASS(klass); 344 ResettableClass *rc = RESETTABLE_CLASS(klass); 345 346 rc->phases.hold = stm32l4x5_usart_base_reset_hold; 347 device_class_set_props(dc, stm32l4x5_usart_base_properties); 348 dc->realize = stm32l4x5_usart_base_realize; 349 dc->vmsd = &vmstate_stm32l4x5_usart_base; 350 } 351 352 static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) 353 { 354 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 355 356 subc->type = STM32L4x5_USART; 357 } 358 359 static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) 360 { 361 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 362 363 subc->type = STM32L4x5_UART; 364 } 365 366 static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) 367 { 368 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 369 370 subc->type = STM32L4x5_LPUART; 371 } 372 373 static const TypeInfo stm32l4x5_usart_types[] = { 374 { 375 .name = TYPE_STM32L4X5_USART_BASE, 376 .parent = TYPE_SYS_BUS_DEVICE, 377 .instance_size = sizeof(Stm32l4x5UsartBaseState), 378 .instance_init = stm32l4x5_usart_base_init, 379 .class_init = stm32l4x5_usart_base_class_init, 380 .abstract = true, 381 }, { 382 .name = TYPE_STM32L4X5_USART, 383 .parent = TYPE_STM32L4X5_USART_BASE, 384 .class_init = stm32l4x5_usart_class_init, 385 }, { 386 .name = TYPE_STM32L4X5_UART, 387 .parent = TYPE_STM32L4X5_USART_BASE, 388 .class_init = stm32l4x5_uart_class_init, 389 }, { 390 .name = TYPE_STM32L4X5_LPUART, 391 .parent = TYPE_STM32L4X5_USART_BASE, 392 .class_init = stm32l4x5_lpuart_class_init, 393 } 394 }; 395 396 DEFINE_TYPES(stm32l4x5_usart_types) 397