14fb37aeaSArnaud Minier /* 24fb37aeaSArnaud Minier * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) 34fb37aeaSArnaud Minier * 44fb37aeaSArnaud Minier * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 54fb37aeaSArnaud Minier * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 64fb37aeaSArnaud Minier * 74fb37aeaSArnaud Minier * SPDX-License-Identifier: GPL-2.0-or-later 84fb37aeaSArnaud Minier * 94fb37aeaSArnaud Minier * This work is licensed under the terms of the GNU GPL, version 2 or later. 104fb37aeaSArnaud Minier * See the COPYING file in the top-level directory. 114fb37aeaSArnaud Minier * 124fb37aeaSArnaud Minier * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart 134fb37aeaSArnaud Minier * by Alistair Francis. 144fb37aeaSArnaud Minier * The reference used is the STMicroElectronics RM0351 Reference manual 154fb37aeaSArnaud Minier * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 164fb37aeaSArnaud Minier */ 174fb37aeaSArnaud Minier 184fb37aeaSArnaud Minier #include "qemu/osdep.h" 194fb37aeaSArnaud Minier #include "qemu/log.h" 204fb37aeaSArnaud Minier #include "qemu/module.h" 214fb37aeaSArnaud Minier #include "qapi/error.h" 224fb37aeaSArnaud Minier #include "chardev/char-fe.h" 234fb37aeaSArnaud Minier #include "chardev/char-serial.h" 244fb37aeaSArnaud Minier #include "migration/vmstate.h" 254fb37aeaSArnaud Minier #include "hw/char/stm32l4x5_usart.h" 264fb37aeaSArnaud Minier #include "hw/clock.h" 274fb37aeaSArnaud Minier #include "hw/irq.h" 284fb37aeaSArnaud Minier #include "hw/qdev-clock.h" 294fb37aeaSArnaud Minier #include "hw/qdev-properties.h" 304fb37aeaSArnaud Minier #include "hw/qdev-properties-system.h" 314fb37aeaSArnaud Minier #include "hw/registerfields.h" 324fb37aeaSArnaud Minier #include "trace.h" 334fb37aeaSArnaud Minier 344fb37aeaSArnaud Minier 354fb37aeaSArnaud Minier REG32(CR1, 0x00) 364fb37aeaSArnaud Minier FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ 374fb37aeaSArnaud Minier FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ 384fb37aeaSArnaud Minier FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ 394fb37aeaSArnaud Minier FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ 404fb37aeaSArnaud Minier FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ 414fb37aeaSArnaud Minier FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ 424fb37aeaSArnaud Minier FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ 434fb37aeaSArnaud Minier FIELD(CR1, MME, 13, 1) /* Mute mode enable */ 444fb37aeaSArnaud Minier FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ 454fb37aeaSArnaud Minier FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ 464fb37aeaSArnaud Minier FIELD(CR1, PCE, 10, 1) /* Parity control enable */ 474fb37aeaSArnaud Minier FIELD(CR1, PS, 9, 1) /* Parity selection */ 484fb37aeaSArnaud Minier FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ 494fb37aeaSArnaud Minier FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ 504fb37aeaSArnaud Minier FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ 514fb37aeaSArnaud Minier FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ 524fb37aeaSArnaud Minier FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ 534fb37aeaSArnaud Minier FIELD(CR1, TE, 3, 1) /* Transmitter enable */ 544fb37aeaSArnaud Minier FIELD(CR1, RE, 2, 1) /* Receiver enable */ 554fb37aeaSArnaud Minier FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ 564fb37aeaSArnaud Minier FIELD(CR1, UE, 0, 1) /* USART enable */ 574fb37aeaSArnaud Minier REG32(CR2, 0x04) 584fb37aeaSArnaud Minier FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ 594fb37aeaSArnaud Minier FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */ 604fb37aeaSArnaud Minier FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ 614fb37aeaSArnaud Minier FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ 624fb37aeaSArnaud Minier FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ 634fb37aeaSArnaud Minier FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ 644fb37aeaSArnaud Minier FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ 654fb37aeaSArnaud Minier FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ 664fb37aeaSArnaud Minier FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ 674fb37aeaSArnaud Minier FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ 684fb37aeaSArnaud Minier FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ 694fb37aeaSArnaud Minier FIELD(CR2, STOP, 12, 2) /* STOP bits */ 704fb37aeaSArnaud Minier FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ 714fb37aeaSArnaud Minier FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ 724fb37aeaSArnaud Minier FIELD(CR2, CPHA, 9, 1) /* Clock phase */ 734fb37aeaSArnaud Minier FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ 744fb37aeaSArnaud Minier FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ 754fb37aeaSArnaud Minier FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ 764fb37aeaSArnaud Minier FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ 774fb37aeaSArnaud Minier 784fb37aeaSArnaud Minier REG32(CR3, 0x08) 794fb37aeaSArnaud Minier /* TCBGTIE only on STM32L496xx/4A6xx devices */ 804fb37aeaSArnaud Minier FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ 814fb37aeaSArnaud Minier FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ 824fb37aeaSArnaud Minier FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ 834fb37aeaSArnaud Minier FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ 844fb37aeaSArnaud Minier FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ 854fb37aeaSArnaud Minier FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ 864fb37aeaSArnaud Minier FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ 874fb37aeaSArnaud Minier FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ 884fb37aeaSArnaud Minier FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ 894fb37aeaSArnaud Minier FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ 904fb37aeaSArnaud Minier FIELD(CR3, CTSE, 9, 1) /* CTS enable */ 914fb37aeaSArnaud Minier FIELD(CR3, RTSE, 8, 1) /* RTS enable */ 924fb37aeaSArnaud Minier FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ 934fb37aeaSArnaud Minier FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ 944fb37aeaSArnaud Minier FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ 954fb37aeaSArnaud Minier FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ 964fb37aeaSArnaud Minier FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ 974fb37aeaSArnaud Minier FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ 984fb37aeaSArnaud Minier FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ 994fb37aeaSArnaud Minier FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ 1004fb37aeaSArnaud Minier REG32(BRR, 0x0C) 1014fb37aeaSArnaud Minier FIELD(BRR, BRR, 0, 16) 1024fb37aeaSArnaud Minier REG32(GTPR, 0x10) 1034fb37aeaSArnaud Minier FIELD(GTPR, GT, 8, 8) /* Guard time value */ 1044fb37aeaSArnaud Minier FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ 1054fb37aeaSArnaud Minier REG32(RTOR, 0x14) 1064fb37aeaSArnaud Minier FIELD(RTOR, BLEN, 24, 8) /* Block Length */ 1074fb37aeaSArnaud Minier FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ 1084fb37aeaSArnaud Minier REG32(RQR, 0x18) 1094fb37aeaSArnaud Minier FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ 1104fb37aeaSArnaud Minier FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ 1114fb37aeaSArnaud Minier FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ 1124fb37aeaSArnaud Minier FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ 1134fb37aeaSArnaud Minier FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ 1144fb37aeaSArnaud Minier REG32(ISR, 0x1C) 1154fb37aeaSArnaud Minier /* TCBGT only for STM32L475xx/476xx/486xx devices */ 1164fb37aeaSArnaud Minier FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ 1174fb37aeaSArnaud Minier FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ 1184fb37aeaSArnaud Minier FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ 1194fb37aeaSArnaud Minier FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ 1204fb37aeaSArnaud Minier FIELD(ISR, SBKF, 18, 1) /* Send break flag */ 1214fb37aeaSArnaud Minier FIELD(ISR, CMF, 17, 1) /* Character match flag */ 1224fb37aeaSArnaud Minier FIELD(ISR, BUSY, 16, 1) /* Busy flag */ 1234fb37aeaSArnaud Minier FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ 1244fb37aeaSArnaud Minier FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ 1254fb37aeaSArnaud Minier FIELD(ISR, EOBF, 12, 1) /* End of block flag */ 1264fb37aeaSArnaud Minier FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ 1274fb37aeaSArnaud Minier FIELD(ISR, CTS, 10, 1) /* CTS flag */ 1284fb37aeaSArnaud Minier FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ 1294fb37aeaSArnaud Minier FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ 1304fb37aeaSArnaud Minier FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ 1314fb37aeaSArnaud Minier FIELD(ISR, TC, 6, 1) /* Transmission complete */ 1324fb37aeaSArnaud Minier FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ 1334fb37aeaSArnaud Minier FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ 1344fb37aeaSArnaud Minier FIELD(ISR, ORE, 3, 1) /* Overrun error */ 1354fb37aeaSArnaud Minier FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ 1364fb37aeaSArnaud Minier FIELD(ISR, FE, 1, 1) /* Framing Error */ 1374fb37aeaSArnaud Minier FIELD(ISR, PE, 0, 1) /* Parity Error */ 1384fb37aeaSArnaud Minier REG32(ICR, 0x20) 1394fb37aeaSArnaud Minier FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ 1404fb37aeaSArnaud Minier FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ 1414fb37aeaSArnaud Minier FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ 1424fb37aeaSArnaud Minier FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ 1434fb37aeaSArnaud Minier FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ 1444fb37aeaSArnaud Minier FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ 1454fb37aeaSArnaud Minier /* TCBGTCF only on STM32L496xx/4A6xx devices */ 1464fb37aeaSArnaud Minier FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ 1474fb37aeaSArnaud Minier FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ 1484fb37aeaSArnaud Minier FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ 1494fb37aeaSArnaud Minier FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ 1504fb37aeaSArnaud Minier FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ 1514fb37aeaSArnaud Minier FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ 1524fb37aeaSArnaud Minier REG32(RDR, 0x24) 1534fb37aeaSArnaud Minier FIELD(RDR, RDR, 0, 9) 1544fb37aeaSArnaud Minier REG32(TDR, 0x28) 1554fb37aeaSArnaud Minier FIELD(TDR, TDR, 0, 9) 1564fb37aeaSArnaud Minier 157*87b77e6eSArnaud Minier static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) 158*87b77e6eSArnaud Minier { 159*87b77e6eSArnaud Minier if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || 160*87b77e6eSArnaud Minier ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || 161*87b77e6eSArnaud Minier ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 162*87b77e6eSArnaud Minier ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || 163*87b77e6eSArnaud Minier ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || 164*87b77e6eSArnaud Minier ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || 165*87b77e6eSArnaud Minier ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || 166*87b77e6eSArnaud Minier ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || 167*87b77e6eSArnaud Minier ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || 168*87b77e6eSArnaud Minier ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || 169*87b77e6eSArnaud Minier ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || 170*87b77e6eSArnaud Minier ((s->isr & R_ISR_ORE_MASK) && 171*87b77e6eSArnaud Minier ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || 172*87b77e6eSArnaud Minier /* TODO: Handle NF ? */ 173*87b77e6eSArnaud Minier ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || 174*87b77e6eSArnaud Minier ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { 175*87b77e6eSArnaud Minier qemu_irq_raise(s->irq); 176*87b77e6eSArnaud Minier trace_stm32l4x5_usart_irq_raised(s->isr); 177*87b77e6eSArnaud Minier } else { 178*87b77e6eSArnaud Minier qemu_irq_lower(s->irq); 179*87b77e6eSArnaud Minier trace_stm32l4x5_usart_irq_lowered(); 180*87b77e6eSArnaud Minier } 181*87b77e6eSArnaud Minier } 182*87b77e6eSArnaud Minier 183*87b77e6eSArnaud Minier static int stm32l4x5_usart_base_can_receive(void *opaque) 184*87b77e6eSArnaud Minier { 185*87b77e6eSArnaud Minier Stm32l4x5UsartBaseState *s = opaque; 186*87b77e6eSArnaud Minier 187*87b77e6eSArnaud Minier if (!(s->isr & R_ISR_RXNE_MASK)) { 188*87b77e6eSArnaud Minier return 1; 189*87b77e6eSArnaud Minier } 190*87b77e6eSArnaud Minier 191*87b77e6eSArnaud Minier return 0; 192*87b77e6eSArnaud Minier } 193*87b77e6eSArnaud Minier 194*87b77e6eSArnaud Minier static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, 195*87b77e6eSArnaud Minier int size) 196*87b77e6eSArnaud Minier { 197*87b77e6eSArnaud Minier Stm32l4x5UsartBaseState *s = opaque; 198*87b77e6eSArnaud Minier 199*87b77e6eSArnaud Minier if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { 200*87b77e6eSArnaud Minier trace_stm32l4x5_usart_receiver_not_enabled( 201*87b77e6eSArnaud Minier FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); 202*87b77e6eSArnaud Minier return; 203*87b77e6eSArnaud Minier } 204*87b77e6eSArnaud Minier 205*87b77e6eSArnaud Minier /* Check if overrun detection is enabled and if there is an overrun */ 206*87b77e6eSArnaud Minier if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { 207*87b77e6eSArnaud Minier /* 208*87b77e6eSArnaud Minier * A character has been received while 209*87b77e6eSArnaud Minier * the previous has not been read = Overrun. 210*87b77e6eSArnaud Minier */ 211*87b77e6eSArnaud Minier s->isr |= R_ISR_ORE_MASK; 212*87b77e6eSArnaud Minier trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); 213*87b77e6eSArnaud Minier } else { 214*87b77e6eSArnaud Minier /* No overrun */ 215*87b77e6eSArnaud Minier s->rdr = *buf; 216*87b77e6eSArnaud Minier s->isr |= R_ISR_RXNE_MASK; 217*87b77e6eSArnaud Minier trace_stm32l4x5_usart_rx(s->rdr); 218*87b77e6eSArnaud Minier } 219*87b77e6eSArnaud Minier 220*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 221*87b77e6eSArnaud Minier } 222*87b77e6eSArnaud Minier 223*87b77e6eSArnaud Minier /* 224*87b77e6eSArnaud Minier * Try to send tx data, and arrange to be called back later if 225*87b77e6eSArnaud Minier * we can't (ie the char backend is busy/blocking). 226*87b77e6eSArnaud Minier */ 227*87b77e6eSArnaud Minier static gboolean usart_transmit(void *do_not_use, GIOCondition cond, 228*87b77e6eSArnaud Minier void *opaque) 229*87b77e6eSArnaud Minier { 230*87b77e6eSArnaud Minier Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque); 231*87b77e6eSArnaud Minier int ret; 232*87b77e6eSArnaud Minier /* TODO: Handle 9 bits transmission */ 233*87b77e6eSArnaud Minier uint8_t ch = s->tdr; 234*87b77e6eSArnaud Minier 235*87b77e6eSArnaud Minier s->watch_tag = 0; 236*87b77e6eSArnaud Minier 237*87b77e6eSArnaud Minier if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { 238*87b77e6eSArnaud Minier return G_SOURCE_REMOVE; 239*87b77e6eSArnaud Minier } 240*87b77e6eSArnaud Minier 241*87b77e6eSArnaud Minier ret = qemu_chr_fe_write(&s->chr, &ch, 1); 242*87b77e6eSArnaud Minier if (ret <= 0) { 243*87b77e6eSArnaud Minier s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 244*87b77e6eSArnaud Minier usart_transmit, s); 245*87b77e6eSArnaud Minier if (!s->watch_tag) { 246*87b77e6eSArnaud Minier /* 247*87b77e6eSArnaud Minier * Most common reason to be here is "no chardev backend": 248*87b77e6eSArnaud Minier * just insta-drain the buffer, so the serial output 249*87b77e6eSArnaud Minier * goes into a void, rather than blocking the guest. 250*87b77e6eSArnaud Minier */ 251*87b77e6eSArnaud Minier goto buffer_drained; 252*87b77e6eSArnaud Minier } 253*87b77e6eSArnaud Minier /* Transmit pending */ 254*87b77e6eSArnaud Minier trace_stm32l4x5_usart_tx_pending(); 255*87b77e6eSArnaud Minier return G_SOURCE_REMOVE; 256*87b77e6eSArnaud Minier } 257*87b77e6eSArnaud Minier 258*87b77e6eSArnaud Minier buffer_drained: 259*87b77e6eSArnaud Minier /* Character successfully sent */ 260*87b77e6eSArnaud Minier trace_stm32l4x5_usart_tx(ch); 261*87b77e6eSArnaud Minier s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; 262*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 263*87b77e6eSArnaud Minier return G_SOURCE_REMOVE; 264*87b77e6eSArnaud Minier } 265*87b77e6eSArnaud Minier 266*87b77e6eSArnaud Minier static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) 267*87b77e6eSArnaud Minier { 268*87b77e6eSArnaud Minier if (s->watch_tag) { 269*87b77e6eSArnaud Minier g_source_remove(s->watch_tag); 270*87b77e6eSArnaud Minier s->watch_tag = 0; 271*87b77e6eSArnaud Minier } 272*87b77e6eSArnaud Minier } 273*87b77e6eSArnaud Minier 2744fb37aeaSArnaud Minier static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) 2754fb37aeaSArnaud Minier { 2764fb37aeaSArnaud Minier Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 2774fb37aeaSArnaud Minier 2784fb37aeaSArnaud Minier s->cr1 = 0x00000000; 2794fb37aeaSArnaud Minier s->cr2 = 0x00000000; 2804fb37aeaSArnaud Minier s->cr3 = 0x00000000; 2814fb37aeaSArnaud Minier s->brr = 0x00000000; 2824fb37aeaSArnaud Minier s->gtpr = 0x00000000; 2834fb37aeaSArnaud Minier s->rtor = 0x00000000; 2844fb37aeaSArnaud Minier s->isr = 0x020000C0; 2854fb37aeaSArnaud Minier s->rdr = 0x00000000; 2864fb37aeaSArnaud Minier s->tdr = 0x00000000; 287*87b77e6eSArnaud Minier 288*87b77e6eSArnaud Minier usart_cancel_transmit(s); 289*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 290*87b77e6eSArnaud Minier } 291*87b77e6eSArnaud Minier 292*87b77e6eSArnaud Minier static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) 293*87b77e6eSArnaud Minier { 294*87b77e6eSArnaud Minier /* TXFRQ */ 295*87b77e6eSArnaud Minier /* Reset RXNE flag */ 296*87b77e6eSArnaud Minier if (value & R_RQR_RXFRQ_MASK) { 297*87b77e6eSArnaud Minier s->isr &= ~R_ISR_RXNE_MASK; 298*87b77e6eSArnaud Minier } 299*87b77e6eSArnaud Minier /* MMRQ */ 300*87b77e6eSArnaud Minier /* SBKRQ */ 301*87b77e6eSArnaud Minier /* ABRRQ */ 302*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 3034fb37aeaSArnaud Minier } 3044fb37aeaSArnaud Minier 3054fb37aeaSArnaud Minier static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, 3064fb37aeaSArnaud Minier unsigned int size) 3074fb37aeaSArnaud Minier { 3084fb37aeaSArnaud Minier Stm32l4x5UsartBaseState *s = opaque; 3094fb37aeaSArnaud Minier uint64_t retvalue = 0; 3104fb37aeaSArnaud Minier 3114fb37aeaSArnaud Minier switch (addr) { 3124fb37aeaSArnaud Minier case A_CR1: 3134fb37aeaSArnaud Minier retvalue = s->cr1; 3144fb37aeaSArnaud Minier break; 3154fb37aeaSArnaud Minier case A_CR2: 3164fb37aeaSArnaud Minier retvalue = s->cr2; 3174fb37aeaSArnaud Minier break; 3184fb37aeaSArnaud Minier case A_CR3: 3194fb37aeaSArnaud Minier retvalue = s->cr3; 3204fb37aeaSArnaud Minier break; 3214fb37aeaSArnaud Minier case A_BRR: 3224fb37aeaSArnaud Minier retvalue = FIELD_EX32(s->brr, BRR, BRR); 3234fb37aeaSArnaud Minier break; 3244fb37aeaSArnaud Minier case A_GTPR: 3254fb37aeaSArnaud Minier retvalue = s->gtpr; 3264fb37aeaSArnaud Minier break; 3274fb37aeaSArnaud Minier case A_RTOR: 3284fb37aeaSArnaud Minier retvalue = s->rtor; 3294fb37aeaSArnaud Minier break; 3304fb37aeaSArnaud Minier case A_RQR: 3314fb37aeaSArnaud Minier /* RQR is a write only register */ 3324fb37aeaSArnaud Minier retvalue = 0x00000000; 3334fb37aeaSArnaud Minier break; 3344fb37aeaSArnaud Minier case A_ISR: 3354fb37aeaSArnaud Minier retvalue = s->isr; 3364fb37aeaSArnaud Minier break; 3374fb37aeaSArnaud Minier case A_ICR: 3384fb37aeaSArnaud Minier /* ICR is a clear register */ 3394fb37aeaSArnaud Minier retvalue = 0x00000000; 3404fb37aeaSArnaud Minier break; 3414fb37aeaSArnaud Minier case A_RDR: 3424fb37aeaSArnaud Minier retvalue = FIELD_EX32(s->rdr, RDR, RDR); 3434fb37aeaSArnaud Minier /* Reset RXNE flag */ 3444fb37aeaSArnaud Minier s->isr &= ~R_ISR_RXNE_MASK; 345*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 3464fb37aeaSArnaud Minier break; 3474fb37aeaSArnaud Minier case A_TDR: 3484fb37aeaSArnaud Minier retvalue = FIELD_EX32(s->tdr, TDR, TDR); 3494fb37aeaSArnaud Minier break; 3504fb37aeaSArnaud Minier default: 3514fb37aeaSArnaud Minier qemu_log_mask(LOG_GUEST_ERROR, 3524fb37aeaSArnaud Minier "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 3534fb37aeaSArnaud Minier break; 3544fb37aeaSArnaud Minier } 3554fb37aeaSArnaud Minier 3564fb37aeaSArnaud Minier trace_stm32l4x5_usart_read(addr, retvalue); 3574fb37aeaSArnaud Minier 3584fb37aeaSArnaud Minier return retvalue; 3594fb37aeaSArnaud Minier } 3604fb37aeaSArnaud Minier 3614fb37aeaSArnaud Minier static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, 3624fb37aeaSArnaud Minier uint64_t val64, unsigned int size) 3634fb37aeaSArnaud Minier { 3644fb37aeaSArnaud Minier Stm32l4x5UsartBaseState *s = opaque; 3654fb37aeaSArnaud Minier const uint32_t value = val64; 3664fb37aeaSArnaud Minier 3674fb37aeaSArnaud Minier trace_stm32l4x5_usart_write(addr, value); 3684fb37aeaSArnaud Minier 3694fb37aeaSArnaud Minier switch (addr) { 3704fb37aeaSArnaud Minier case A_CR1: 3714fb37aeaSArnaud Minier s->cr1 = value; 372*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 3734fb37aeaSArnaud Minier return; 3744fb37aeaSArnaud Minier case A_CR2: 3754fb37aeaSArnaud Minier s->cr2 = value; 3764fb37aeaSArnaud Minier return; 3774fb37aeaSArnaud Minier case A_CR3: 3784fb37aeaSArnaud Minier s->cr3 = value; 3794fb37aeaSArnaud Minier return; 3804fb37aeaSArnaud Minier case A_BRR: 3814fb37aeaSArnaud Minier s->brr = value; 3824fb37aeaSArnaud Minier return; 3834fb37aeaSArnaud Minier case A_GTPR: 3844fb37aeaSArnaud Minier s->gtpr = value; 3854fb37aeaSArnaud Minier return; 3864fb37aeaSArnaud Minier case A_RTOR: 3874fb37aeaSArnaud Minier s->rtor = value; 3884fb37aeaSArnaud Minier return; 3894fb37aeaSArnaud Minier case A_RQR: 390*87b77e6eSArnaud Minier usart_update_rqr(s, value); 3914fb37aeaSArnaud Minier return; 3924fb37aeaSArnaud Minier case A_ISR: 3934fb37aeaSArnaud Minier qemu_log_mask(LOG_GUEST_ERROR, 3944fb37aeaSArnaud Minier "%s: ISR is read only !\n", __func__); 3954fb37aeaSArnaud Minier return; 3964fb37aeaSArnaud Minier case A_ICR: 3974fb37aeaSArnaud Minier /* Clear the status flags */ 3984fb37aeaSArnaud Minier s->isr &= ~value; 399*87b77e6eSArnaud Minier stm32l4x5_update_irq(s); 4004fb37aeaSArnaud Minier return; 4014fb37aeaSArnaud Minier case A_RDR: 4024fb37aeaSArnaud Minier qemu_log_mask(LOG_GUEST_ERROR, 4034fb37aeaSArnaud Minier "%s: RDR is read only !\n", __func__); 4044fb37aeaSArnaud Minier return; 4054fb37aeaSArnaud Minier case A_TDR: 4064fb37aeaSArnaud Minier s->tdr = value; 407*87b77e6eSArnaud Minier s->isr &= ~R_ISR_TXE_MASK; 408*87b77e6eSArnaud Minier usart_transmit(NULL, G_IO_OUT, s); 4094fb37aeaSArnaud Minier return; 4104fb37aeaSArnaud Minier default: 4114fb37aeaSArnaud Minier qemu_log_mask(LOG_GUEST_ERROR, 4124fb37aeaSArnaud Minier "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 4134fb37aeaSArnaud Minier } 4144fb37aeaSArnaud Minier } 4154fb37aeaSArnaud Minier 4164fb37aeaSArnaud Minier static const MemoryRegionOps stm32l4x5_usart_base_ops = { 4174fb37aeaSArnaud Minier .read = stm32l4x5_usart_base_read, 4184fb37aeaSArnaud Minier .write = stm32l4x5_usart_base_write, 4194fb37aeaSArnaud Minier .endianness = DEVICE_NATIVE_ENDIAN, 4204fb37aeaSArnaud Minier .valid = { 4214fb37aeaSArnaud Minier .max_access_size = 4, 4224fb37aeaSArnaud Minier .min_access_size = 4, 4234fb37aeaSArnaud Minier .unaligned = false 4244fb37aeaSArnaud Minier }, 4254fb37aeaSArnaud Minier .impl = { 4264fb37aeaSArnaud Minier .max_access_size = 4, 4274fb37aeaSArnaud Minier .min_access_size = 4, 4284fb37aeaSArnaud Minier .unaligned = false 4294fb37aeaSArnaud Minier }, 4304fb37aeaSArnaud Minier }; 4314fb37aeaSArnaud Minier 4324fb37aeaSArnaud Minier static Property stm32l4x5_usart_base_properties[] = { 4334fb37aeaSArnaud Minier DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), 4344fb37aeaSArnaud Minier DEFINE_PROP_END_OF_LIST(), 4354fb37aeaSArnaud Minier }; 4364fb37aeaSArnaud Minier 4374fb37aeaSArnaud Minier static void stm32l4x5_usart_base_init(Object *obj) 4384fb37aeaSArnaud Minier { 4394fb37aeaSArnaud Minier Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); 4404fb37aeaSArnaud Minier 4414fb37aeaSArnaud Minier sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 4424fb37aeaSArnaud Minier 4434fb37aeaSArnaud Minier memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, 4444fb37aeaSArnaud Minier TYPE_STM32L4X5_USART_BASE, 0x400); 4454fb37aeaSArnaud Minier sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 4464fb37aeaSArnaud Minier 4474fb37aeaSArnaud Minier s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); 4484fb37aeaSArnaud Minier } 4494fb37aeaSArnaud Minier 4504fb37aeaSArnaud Minier static const VMStateDescription vmstate_stm32l4x5_usart_base = { 4514fb37aeaSArnaud Minier .name = TYPE_STM32L4X5_USART_BASE, 4524fb37aeaSArnaud Minier .version_id = 1, 4534fb37aeaSArnaud Minier .minimum_version_id = 1, 4544fb37aeaSArnaud Minier .fields = (VMStateField[]) { 4554fb37aeaSArnaud Minier VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), 4564fb37aeaSArnaud Minier VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), 4574fb37aeaSArnaud Minier VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), 4584fb37aeaSArnaud Minier VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), 4594fb37aeaSArnaud Minier VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), 4604fb37aeaSArnaud Minier VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), 4614fb37aeaSArnaud Minier VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), 4624fb37aeaSArnaud Minier VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), 4634fb37aeaSArnaud Minier VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), 4644fb37aeaSArnaud Minier VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), 4654fb37aeaSArnaud Minier VMSTATE_END_OF_LIST() 4664fb37aeaSArnaud Minier } 4674fb37aeaSArnaud Minier }; 4684fb37aeaSArnaud Minier 4694fb37aeaSArnaud Minier 4704fb37aeaSArnaud Minier static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) 4714fb37aeaSArnaud Minier { 4724fb37aeaSArnaud Minier ERRP_GUARD(); 4734fb37aeaSArnaud Minier Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); 4744fb37aeaSArnaud Minier if (!clock_has_source(s->clk)) { 4754fb37aeaSArnaud Minier error_setg(errp, "USART clock must be wired up by SoC code"); 4764fb37aeaSArnaud Minier return; 4774fb37aeaSArnaud Minier } 478*87b77e6eSArnaud Minier 479*87b77e6eSArnaud Minier qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, 480*87b77e6eSArnaud Minier stm32l4x5_usart_base_receive, NULL, NULL, 481*87b77e6eSArnaud Minier s, NULL, true); 4824fb37aeaSArnaud Minier } 4834fb37aeaSArnaud Minier 4844fb37aeaSArnaud Minier static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) 4854fb37aeaSArnaud Minier { 4864fb37aeaSArnaud Minier DeviceClass *dc = DEVICE_CLASS(klass); 4874fb37aeaSArnaud Minier ResettableClass *rc = RESETTABLE_CLASS(klass); 4884fb37aeaSArnaud Minier 4894fb37aeaSArnaud Minier rc->phases.hold = stm32l4x5_usart_base_reset_hold; 4904fb37aeaSArnaud Minier device_class_set_props(dc, stm32l4x5_usart_base_properties); 4914fb37aeaSArnaud Minier dc->realize = stm32l4x5_usart_base_realize; 4924fb37aeaSArnaud Minier dc->vmsd = &vmstate_stm32l4x5_usart_base; 4934fb37aeaSArnaud Minier } 4944fb37aeaSArnaud Minier 4954fb37aeaSArnaud Minier static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) 4964fb37aeaSArnaud Minier { 4974fb37aeaSArnaud Minier Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 4984fb37aeaSArnaud Minier 4994fb37aeaSArnaud Minier subc->type = STM32L4x5_USART; 5004fb37aeaSArnaud Minier } 5014fb37aeaSArnaud Minier 5024fb37aeaSArnaud Minier static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) 5034fb37aeaSArnaud Minier { 5044fb37aeaSArnaud Minier Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 5054fb37aeaSArnaud Minier 5064fb37aeaSArnaud Minier subc->type = STM32L4x5_UART; 5074fb37aeaSArnaud Minier } 5084fb37aeaSArnaud Minier 5094fb37aeaSArnaud Minier static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) 5104fb37aeaSArnaud Minier { 5114fb37aeaSArnaud Minier Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); 5124fb37aeaSArnaud Minier 5134fb37aeaSArnaud Minier subc->type = STM32L4x5_LPUART; 5144fb37aeaSArnaud Minier } 5154fb37aeaSArnaud Minier 5164fb37aeaSArnaud Minier static const TypeInfo stm32l4x5_usart_types[] = { 5174fb37aeaSArnaud Minier { 5184fb37aeaSArnaud Minier .name = TYPE_STM32L4X5_USART_BASE, 5194fb37aeaSArnaud Minier .parent = TYPE_SYS_BUS_DEVICE, 5204fb37aeaSArnaud Minier .instance_size = sizeof(Stm32l4x5UsartBaseState), 5214fb37aeaSArnaud Minier .instance_init = stm32l4x5_usart_base_init, 5224fb37aeaSArnaud Minier .class_init = stm32l4x5_usart_base_class_init, 5234fb37aeaSArnaud Minier .abstract = true, 5244fb37aeaSArnaud Minier }, { 5254fb37aeaSArnaud Minier .name = TYPE_STM32L4X5_USART, 5264fb37aeaSArnaud Minier .parent = TYPE_STM32L4X5_USART_BASE, 5274fb37aeaSArnaud Minier .class_init = stm32l4x5_usart_class_init, 5284fb37aeaSArnaud Minier }, { 5294fb37aeaSArnaud Minier .name = TYPE_STM32L4X5_UART, 5304fb37aeaSArnaud Minier .parent = TYPE_STM32L4X5_USART_BASE, 5314fb37aeaSArnaud Minier .class_init = stm32l4x5_uart_class_init, 5324fb37aeaSArnaud Minier }, { 5334fb37aeaSArnaud Minier .name = TYPE_STM32L4X5_LPUART, 5344fb37aeaSArnaud Minier .parent = TYPE_STM32L4X5_USART_BASE, 5354fb37aeaSArnaud Minier .class_init = stm32l4x5_lpuart_class_init, 5364fb37aeaSArnaud Minier } 5374fb37aeaSArnaud Minier }; 5384fb37aeaSArnaud Minier 5394fb37aeaSArnaud Minier DEFINE_TYPES(stm32l4x5_usart_types) 540