1 /* 2 * STM32F2XX USART 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/char/stm32f2xx_usart.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/qdev-properties-system.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 33 #ifndef STM_USART_ERR_DEBUG 34 #define STM_USART_ERR_DEBUG 0 35 #endif 36 37 #define DB_PRINT_L(lvl, fmt, args...) do { \ 38 if (STM_USART_ERR_DEBUG >= lvl) { \ 39 qemu_log("%s: " fmt, __func__, ## args); \ 40 } \ 41 } while (0) 42 43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 44 45 static int stm32f2xx_usart_can_receive(void *opaque) 46 { 47 STM32F2XXUsartState *s = opaque; 48 49 if (!(s->usart_sr & USART_SR_RXNE)) { 50 return 1; 51 } 52 53 return 0; 54 } 55 56 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 57 { 58 STM32F2XXUsartState *s = opaque; 59 60 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { 61 /* USART not enabled - drop the chars */ 62 DB_PRINT("Dropping the chars\n"); 63 return; 64 } 65 66 s->usart_dr = *buf; 67 s->usart_sr |= USART_SR_RXNE; 68 69 if (s->usart_cr1 & USART_CR1_RXNEIE) { 70 qemu_set_irq(s->irq, 1); 71 } 72 73 DB_PRINT("Receiving: %c\n", s->usart_dr); 74 } 75 76 static void stm32f2xx_usart_reset(DeviceState *dev) 77 { 78 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 79 80 s->usart_sr = USART_SR_RESET; 81 s->usart_dr = 0x00000000; 82 s->usart_brr = 0x00000000; 83 s->usart_cr1 = 0x00000000; 84 s->usart_cr2 = 0x00000000; 85 s->usart_cr3 = 0x00000000; 86 s->usart_gtpr = 0x00000000; 87 88 qemu_set_irq(s->irq, 0); 89 } 90 91 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, 92 unsigned int size) 93 { 94 STM32F2XXUsartState *s = opaque; 95 uint64_t retvalue; 96 97 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); 98 99 switch (addr) { 100 case USART_SR: 101 retvalue = s->usart_sr; 102 qemu_chr_fe_accept_input(&s->chr); 103 return retvalue; 104 case USART_DR: 105 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); 106 s->usart_sr &= ~USART_SR_RXNE; 107 qemu_chr_fe_accept_input(&s->chr); 108 qemu_set_irq(s->irq, 0); 109 return s->usart_dr & 0x3FF; 110 case USART_BRR: 111 return s->usart_brr; 112 case USART_CR1: 113 return s->usart_cr1; 114 case USART_CR2: 115 return s->usart_cr2; 116 case USART_CR3: 117 return s->usart_cr3; 118 case USART_GTPR: 119 return s->usart_gtpr; 120 default: 121 qemu_log_mask(LOG_GUEST_ERROR, 122 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 123 return 0; 124 } 125 126 return 0; 127 } 128 129 static void stm32f2xx_usart_write(void *opaque, hwaddr addr, 130 uint64_t val64, unsigned int size) 131 { 132 STM32F2XXUsartState *s = opaque; 133 uint32_t value = val64; 134 unsigned char ch; 135 136 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); 137 138 switch (addr) { 139 case USART_SR: 140 if (value <= 0x3FF) { 141 /* I/O being synchronous, TXE is always set. In addition, it may 142 only be set by hardware, so keep it set here. */ 143 s->usart_sr = value | USART_SR_TXE; 144 } else { 145 s->usart_sr &= value; 146 } 147 if (!(s->usart_sr & USART_SR_RXNE)) { 148 qemu_set_irq(s->irq, 0); 149 } 150 return; 151 case USART_DR: 152 if (value < 0xF000) { 153 ch = value; 154 /* XXX this blocks entire thread. Rewrite to use 155 * qemu_chr_fe_write and background I/O callbacks */ 156 qemu_chr_fe_write_all(&s->chr, &ch, 1); 157 /* XXX I/O are currently synchronous, making it impossible for 158 software to observe transient states where TXE or TC aren't 159 set. Unlike TXE however, which is read-only, software may 160 clear TC by writing 0 to the SR register, so set it again 161 on each write. */ 162 s->usart_sr |= USART_SR_TC; 163 } 164 return; 165 case USART_BRR: 166 s->usart_brr = value; 167 return; 168 case USART_CR1: 169 s->usart_cr1 = value; 170 if (s->usart_cr1 & USART_CR1_RXNEIE && 171 s->usart_sr & USART_SR_RXNE) { 172 qemu_set_irq(s->irq, 1); 173 } 174 return; 175 case USART_CR2: 176 s->usart_cr2 = value; 177 return; 178 case USART_CR3: 179 s->usart_cr3 = value; 180 return; 181 case USART_GTPR: 182 s->usart_gtpr = value; 183 return; 184 default: 185 qemu_log_mask(LOG_GUEST_ERROR, 186 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 187 } 188 } 189 190 static const MemoryRegionOps stm32f2xx_usart_ops = { 191 .read = stm32f2xx_usart_read, 192 .write = stm32f2xx_usart_write, 193 .endianness = DEVICE_NATIVE_ENDIAN, 194 }; 195 196 static Property stm32f2xx_usart_properties[] = { 197 DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), 198 DEFINE_PROP_END_OF_LIST(), 199 }; 200 201 static void stm32f2xx_usart_init(Object *obj) 202 { 203 STM32F2XXUsartState *s = STM32F2XX_USART(obj); 204 205 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 206 207 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, 208 TYPE_STM32F2XX_USART, 0x400); 209 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 210 } 211 212 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp) 213 { 214 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 215 216 qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive, 217 stm32f2xx_usart_receive, NULL, NULL, 218 s, NULL, true); 219 } 220 221 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) 222 { 223 DeviceClass *dc = DEVICE_CLASS(klass); 224 225 dc->reset = stm32f2xx_usart_reset; 226 device_class_set_props(dc, stm32f2xx_usart_properties); 227 dc->realize = stm32f2xx_usart_realize; 228 } 229 230 static const TypeInfo stm32f2xx_usart_info = { 231 .name = TYPE_STM32F2XX_USART, 232 .parent = TYPE_SYS_BUS_DEVICE, 233 .instance_size = sizeof(STM32F2XXUsartState), 234 .instance_init = stm32f2xx_usart_init, 235 .class_init = stm32f2xx_usart_class_init, 236 }; 237 238 static void stm32f2xx_usart_register_types(void) 239 { 240 type_register_static(&stm32f2xx_usart_info); 241 } 242 243 type_init(stm32f2xx_usart_register_types) 244