1 /* 2 * STM32F2XX USART 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/char/stm32f2xx_usart.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 32 #ifndef STM_USART_ERR_DEBUG 33 #define STM_USART_ERR_DEBUG 0 34 #endif 35 36 #define DB_PRINT_L(lvl, fmt, args...) do { \ 37 if (STM_USART_ERR_DEBUG >= lvl) { \ 38 qemu_log("%s: " fmt, __func__, ## args); \ 39 } \ 40 } while (0) 41 42 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 43 44 static int stm32f2xx_usart_can_receive(void *opaque) 45 { 46 STM32F2XXUsartState *s = opaque; 47 48 if (!(s->usart_sr & USART_SR_RXNE)) { 49 return 1; 50 } 51 52 return 0; 53 } 54 55 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 56 { 57 STM32F2XXUsartState *s = opaque; 58 59 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { 60 /* USART not enabled - drop the chars */ 61 DB_PRINT("Dropping the chars\n"); 62 return; 63 } 64 65 s->usart_dr = *buf; 66 s->usart_sr |= USART_SR_RXNE; 67 68 if (s->usart_cr1 & USART_CR1_RXNEIE) { 69 qemu_set_irq(s->irq, 1); 70 } 71 72 DB_PRINT("Receiving: %c\n", s->usart_dr); 73 } 74 75 static void stm32f2xx_usart_reset(DeviceState *dev) 76 { 77 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 78 79 s->usart_sr = USART_SR_RESET; 80 s->usart_dr = 0x00000000; 81 s->usart_brr = 0x00000000; 82 s->usart_cr1 = 0x00000000; 83 s->usart_cr2 = 0x00000000; 84 s->usart_cr3 = 0x00000000; 85 s->usart_gtpr = 0x00000000; 86 87 qemu_set_irq(s->irq, 0); 88 } 89 90 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, 91 unsigned int size) 92 { 93 STM32F2XXUsartState *s = opaque; 94 uint64_t retvalue; 95 96 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); 97 98 switch (addr) { 99 case USART_SR: 100 retvalue = s->usart_sr; 101 qemu_chr_fe_accept_input(&s->chr); 102 return retvalue; 103 case USART_DR: 104 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); 105 s->usart_sr &= ~USART_SR_RXNE; 106 qemu_chr_fe_accept_input(&s->chr); 107 qemu_set_irq(s->irq, 0); 108 return s->usart_dr & 0x3FF; 109 case USART_BRR: 110 return s->usart_brr; 111 case USART_CR1: 112 return s->usart_cr1; 113 case USART_CR2: 114 return s->usart_cr2; 115 case USART_CR3: 116 return s->usart_cr3; 117 case USART_GTPR: 118 return s->usart_gtpr; 119 default: 120 qemu_log_mask(LOG_GUEST_ERROR, 121 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 122 return 0; 123 } 124 125 return 0; 126 } 127 128 static void stm32f2xx_usart_write(void *opaque, hwaddr addr, 129 uint64_t val64, unsigned int size) 130 { 131 STM32F2XXUsartState *s = opaque; 132 uint32_t value = val64; 133 unsigned char ch; 134 135 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); 136 137 switch (addr) { 138 case USART_SR: 139 if (value <= 0x3FF) { 140 /* I/O being synchronous, TXE is always set. In addition, it may 141 only be set by hardware, so keep it set here. */ 142 s->usart_sr = value | USART_SR_TXE; 143 } else { 144 s->usart_sr &= value; 145 } 146 if (!(s->usart_sr & USART_SR_RXNE)) { 147 qemu_set_irq(s->irq, 0); 148 } 149 return; 150 case USART_DR: 151 if (value < 0xF000) { 152 ch = value; 153 /* XXX this blocks entire thread. Rewrite to use 154 * qemu_chr_fe_write and background I/O callbacks */ 155 qemu_chr_fe_write_all(&s->chr, &ch, 1); 156 /* XXX I/O are currently synchronous, making it impossible for 157 software to observe transient states where TXE or TC aren't 158 set. Unlike TXE however, which is read-only, software may 159 clear TC by writing 0 to the SR register, so set it again 160 on each write. */ 161 s->usart_sr |= USART_SR_TC; 162 } 163 return; 164 case USART_BRR: 165 s->usart_brr = value; 166 return; 167 case USART_CR1: 168 s->usart_cr1 = value; 169 if (s->usart_cr1 & USART_CR1_RXNEIE && 170 s->usart_sr & USART_SR_RXNE) { 171 qemu_set_irq(s->irq, 1); 172 } 173 return; 174 case USART_CR2: 175 s->usart_cr2 = value; 176 return; 177 case USART_CR3: 178 s->usart_cr3 = value; 179 return; 180 case USART_GTPR: 181 s->usart_gtpr = value; 182 return; 183 default: 184 qemu_log_mask(LOG_GUEST_ERROR, 185 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 186 } 187 } 188 189 static const MemoryRegionOps stm32f2xx_usart_ops = { 190 .read = stm32f2xx_usart_read, 191 .write = stm32f2xx_usart_write, 192 .endianness = DEVICE_NATIVE_ENDIAN, 193 }; 194 195 static Property stm32f2xx_usart_properties[] = { 196 DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), 197 DEFINE_PROP_END_OF_LIST(), 198 }; 199 200 static void stm32f2xx_usart_init(Object *obj) 201 { 202 STM32F2XXUsartState *s = STM32F2XX_USART(obj); 203 204 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 205 206 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, 207 TYPE_STM32F2XX_USART, 0x400); 208 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 209 } 210 211 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp) 212 { 213 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 214 215 qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive, 216 stm32f2xx_usart_receive, NULL, NULL, 217 s, NULL, true); 218 } 219 220 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) 221 { 222 DeviceClass *dc = DEVICE_CLASS(klass); 223 224 dc->reset = stm32f2xx_usart_reset; 225 device_class_set_props(dc, stm32f2xx_usart_properties); 226 dc->realize = stm32f2xx_usart_realize; 227 } 228 229 static const TypeInfo stm32f2xx_usart_info = { 230 .name = TYPE_STM32F2XX_USART, 231 .parent = TYPE_SYS_BUS_DEVICE, 232 .instance_size = sizeof(STM32F2XXUsartState), 233 .instance_init = stm32f2xx_usart_init, 234 .class_init = stm32f2xx_usart_class_init, 235 }; 236 237 static void stm32f2xx_usart_register_types(void) 238 { 239 type_register_static(&stm32f2xx_usart_info); 240 } 241 242 type_init(stm32f2xx_usart_register_types) 243