1 /* 2 * STM32F2XX USART 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/char/stm32f2xx_usart.h" 27 #include "hw/irq.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 31 #ifndef STM_USART_ERR_DEBUG 32 #define STM_USART_ERR_DEBUG 0 33 #endif 34 35 #define DB_PRINT_L(lvl, fmt, args...) do { \ 36 if (STM_USART_ERR_DEBUG >= lvl) { \ 37 qemu_log("%s: " fmt, __func__, ## args); \ 38 } \ 39 } while (0) 40 41 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 42 43 static int stm32f2xx_usart_can_receive(void *opaque) 44 { 45 STM32F2XXUsartState *s = opaque; 46 47 if (!(s->usart_sr & USART_SR_RXNE)) { 48 return 1; 49 } 50 51 return 0; 52 } 53 54 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 55 { 56 STM32F2XXUsartState *s = opaque; 57 58 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { 59 /* USART not enabled - drop the chars */ 60 DB_PRINT("Dropping the chars\n"); 61 return; 62 } 63 64 s->usart_dr = *buf; 65 s->usart_sr |= USART_SR_RXNE; 66 67 if (s->usart_cr1 & USART_CR1_RXNEIE) { 68 qemu_set_irq(s->irq, 1); 69 } 70 71 DB_PRINT("Receiving: %c\n", s->usart_dr); 72 } 73 74 static void stm32f2xx_usart_reset(DeviceState *dev) 75 { 76 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 77 78 s->usart_sr = USART_SR_RESET; 79 s->usart_dr = 0x00000000; 80 s->usart_brr = 0x00000000; 81 s->usart_cr1 = 0x00000000; 82 s->usart_cr2 = 0x00000000; 83 s->usart_cr3 = 0x00000000; 84 s->usart_gtpr = 0x00000000; 85 86 qemu_set_irq(s->irq, 0); 87 } 88 89 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, 90 unsigned int size) 91 { 92 STM32F2XXUsartState *s = opaque; 93 uint64_t retvalue; 94 95 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); 96 97 switch (addr) { 98 case USART_SR: 99 retvalue = s->usart_sr; 100 qemu_chr_fe_accept_input(&s->chr); 101 return retvalue; 102 case USART_DR: 103 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); 104 s->usart_sr &= ~USART_SR_RXNE; 105 qemu_chr_fe_accept_input(&s->chr); 106 qemu_set_irq(s->irq, 0); 107 return s->usart_dr & 0x3FF; 108 case USART_BRR: 109 return s->usart_brr; 110 case USART_CR1: 111 return s->usart_cr1; 112 case USART_CR2: 113 return s->usart_cr2; 114 case USART_CR3: 115 return s->usart_cr3; 116 case USART_GTPR: 117 return s->usart_gtpr; 118 default: 119 qemu_log_mask(LOG_GUEST_ERROR, 120 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 121 return 0; 122 } 123 124 return 0; 125 } 126 127 static void stm32f2xx_usart_write(void *opaque, hwaddr addr, 128 uint64_t val64, unsigned int size) 129 { 130 STM32F2XXUsartState *s = opaque; 131 uint32_t value = val64; 132 unsigned char ch; 133 134 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); 135 136 switch (addr) { 137 case USART_SR: 138 if (value <= 0x3FF) { 139 /* I/O being synchronous, TXE is always set. In addition, it may 140 only be set by hardware, so keep it set here. */ 141 s->usart_sr = value | USART_SR_TXE; 142 } else { 143 s->usart_sr &= value; 144 } 145 if (!(s->usart_sr & USART_SR_RXNE)) { 146 qemu_set_irq(s->irq, 0); 147 } 148 return; 149 case USART_DR: 150 if (value < 0xF000) { 151 ch = value; 152 /* XXX this blocks entire thread. Rewrite to use 153 * qemu_chr_fe_write and background I/O callbacks */ 154 qemu_chr_fe_write_all(&s->chr, &ch, 1); 155 /* XXX I/O are currently synchronous, making it impossible for 156 software to observe transient states where TXE or TC aren't 157 set. Unlike TXE however, which is read-only, software may 158 clear TC by writing 0 to the SR register, so set it again 159 on each write. */ 160 s->usart_sr |= USART_SR_TC; 161 } 162 return; 163 case USART_BRR: 164 s->usart_brr = value; 165 return; 166 case USART_CR1: 167 s->usart_cr1 = value; 168 if (s->usart_cr1 & USART_CR1_RXNEIE && 169 s->usart_sr & USART_SR_RXNE) { 170 qemu_set_irq(s->irq, 1); 171 } 172 return; 173 case USART_CR2: 174 s->usart_cr2 = value; 175 return; 176 case USART_CR3: 177 s->usart_cr3 = value; 178 return; 179 case USART_GTPR: 180 s->usart_gtpr = value; 181 return; 182 default: 183 qemu_log_mask(LOG_GUEST_ERROR, 184 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 185 } 186 } 187 188 static const MemoryRegionOps stm32f2xx_usart_ops = { 189 .read = stm32f2xx_usart_read, 190 .write = stm32f2xx_usart_write, 191 .endianness = DEVICE_NATIVE_ENDIAN, 192 }; 193 194 static Property stm32f2xx_usart_properties[] = { 195 DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), 196 DEFINE_PROP_END_OF_LIST(), 197 }; 198 199 static void stm32f2xx_usart_init(Object *obj) 200 { 201 STM32F2XXUsartState *s = STM32F2XX_USART(obj); 202 203 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 204 205 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, 206 TYPE_STM32F2XX_USART, 0x400); 207 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 208 } 209 210 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp) 211 { 212 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 213 214 qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive, 215 stm32f2xx_usart_receive, NULL, NULL, 216 s, NULL, true); 217 } 218 219 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) 220 { 221 DeviceClass *dc = DEVICE_CLASS(klass); 222 223 dc->reset = stm32f2xx_usart_reset; 224 dc->props = stm32f2xx_usart_properties; 225 dc->realize = stm32f2xx_usart_realize; 226 } 227 228 static const TypeInfo stm32f2xx_usart_info = { 229 .name = TYPE_STM32F2XX_USART, 230 .parent = TYPE_SYS_BUS_DEVICE, 231 .instance_size = sizeof(STM32F2XXUsartState), 232 .instance_init = stm32f2xx_usart_init, 233 .class_init = stm32f2xx_usart_class_init, 234 }; 235 236 static void stm32f2xx_usart_register_types(void) 237 { 238 type_register_static(&stm32f2xx_usart_info); 239 } 240 241 type_init(stm32f2xx_usart_register_types) 242