1 /* 2 * STM32F2XX USART 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/char/stm32f2xx_usart.h" 27 #include "qemu/log.h" 28 29 #ifndef STM_USART_ERR_DEBUG 30 #define STM_USART_ERR_DEBUG 0 31 #endif 32 33 #define DB_PRINT_L(lvl, fmt, args...) do { \ 34 if (STM_USART_ERR_DEBUG >= lvl) { \ 35 qemu_log("%s: " fmt, __func__, ## args); \ 36 } \ 37 } while (0) 38 39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 40 41 static int stm32f2xx_usart_can_receive(void *opaque) 42 { 43 STM32F2XXUsartState *s = opaque; 44 45 if (!(s->usart_sr & USART_SR_RXNE)) { 46 return 1; 47 } 48 49 return 0; 50 } 51 52 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 53 { 54 STM32F2XXUsartState *s = opaque; 55 56 s->usart_dr = *buf; 57 58 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { 59 /* USART not enabled - drop the chars */ 60 DB_PRINT("Dropping the chars\n"); 61 return; 62 } 63 64 s->usart_sr |= USART_SR_RXNE; 65 66 if (s->usart_cr1 & USART_CR1_RXNEIE) { 67 qemu_set_irq(s->irq, 1); 68 } 69 70 DB_PRINT("Receiving: %c\n", s->usart_dr); 71 } 72 73 static void stm32f2xx_usart_reset(DeviceState *dev) 74 { 75 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 76 77 s->usart_sr = USART_SR_RESET; 78 s->usart_dr = 0x00000000; 79 s->usart_brr = 0x00000000; 80 s->usart_cr1 = 0x00000000; 81 s->usart_cr2 = 0x00000000; 82 s->usart_cr3 = 0x00000000; 83 s->usart_gtpr = 0x00000000; 84 85 qemu_set_irq(s->irq, 0); 86 } 87 88 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, 89 unsigned int size) 90 { 91 STM32F2XXUsartState *s = opaque; 92 uint64_t retvalue; 93 94 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); 95 96 switch (addr) { 97 case USART_SR: 98 retvalue = s->usart_sr; 99 s->usart_sr &= ~USART_SR_TC; 100 qemu_chr_fe_accept_input(&s->chr); 101 return retvalue; 102 case USART_DR: 103 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); 104 s->usart_sr |= USART_SR_TXE; 105 s->usart_sr &= ~USART_SR_RXNE; 106 qemu_chr_fe_accept_input(&s->chr); 107 qemu_set_irq(s->irq, 0); 108 return s->usart_dr & 0x3FF; 109 case USART_BRR: 110 return s->usart_brr; 111 case USART_CR1: 112 return s->usart_cr1; 113 case USART_CR2: 114 return s->usart_cr2; 115 case USART_CR3: 116 return s->usart_cr3; 117 case USART_GTPR: 118 return s->usart_gtpr; 119 default: 120 qemu_log_mask(LOG_GUEST_ERROR, 121 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 122 return 0; 123 } 124 125 return 0; 126 } 127 128 static void stm32f2xx_usart_write(void *opaque, hwaddr addr, 129 uint64_t val64, unsigned int size) 130 { 131 STM32F2XXUsartState *s = opaque; 132 uint32_t value = val64; 133 unsigned char ch; 134 135 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); 136 137 switch (addr) { 138 case USART_SR: 139 if (value <= 0x3FF) { 140 s->usart_sr = value; 141 } else { 142 s->usart_sr &= value; 143 } 144 if (!(s->usart_sr & USART_SR_RXNE)) { 145 qemu_set_irq(s->irq, 0); 146 } 147 return; 148 case USART_DR: 149 if (value < 0xF000) { 150 ch = value; 151 /* XXX this blocks entire thread. Rewrite to use 152 * qemu_chr_fe_write and background I/O callbacks */ 153 qemu_chr_fe_write_all(&s->chr, &ch, 1); 154 s->usart_sr |= USART_SR_TC; 155 s->usart_sr &= ~USART_SR_TXE; 156 } 157 return; 158 case USART_BRR: 159 s->usart_brr = value; 160 return; 161 case USART_CR1: 162 s->usart_cr1 = value; 163 if (s->usart_cr1 & USART_CR1_RXNEIE && 164 s->usart_sr & USART_SR_RXNE) { 165 qemu_set_irq(s->irq, 1); 166 } 167 return; 168 case USART_CR2: 169 s->usart_cr2 = value; 170 return; 171 case USART_CR3: 172 s->usart_cr3 = value; 173 return; 174 case USART_GTPR: 175 s->usart_gtpr = value; 176 return; 177 default: 178 qemu_log_mask(LOG_GUEST_ERROR, 179 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 180 } 181 } 182 183 static const MemoryRegionOps stm32f2xx_usart_ops = { 184 .read = stm32f2xx_usart_read, 185 .write = stm32f2xx_usart_write, 186 .endianness = DEVICE_NATIVE_ENDIAN, 187 }; 188 189 static Property stm32f2xx_usart_properties[] = { 190 DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), 191 DEFINE_PROP_END_OF_LIST(), 192 }; 193 194 static void stm32f2xx_usart_init(Object *obj) 195 { 196 STM32F2XXUsartState *s = STM32F2XX_USART(obj); 197 198 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 199 200 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, 201 TYPE_STM32F2XX_USART, 0x2000); 202 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 203 } 204 205 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp) 206 { 207 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 208 209 qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive, 210 stm32f2xx_usart_receive, NULL, NULL, 211 s, NULL, true); 212 } 213 214 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) 215 { 216 DeviceClass *dc = DEVICE_CLASS(klass); 217 218 dc->reset = stm32f2xx_usart_reset; 219 dc->props = stm32f2xx_usart_properties; 220 dc->realize = stm32f2xx_usart_realize; 221 } 222 223 static const TypeInfo stm32f2xx_usart_info = { 224 .name = TYPE_STM32F2XX_USART, 225 .parent = TYPE_SYS_BUS_DEVICE, 226 .instance_size = sizeof(STM32F2XXUsartState), 227 .instance_init = stm32f2xx_usart_init, 228 .class_init = stm32f2xx_usart_class_init, 229 }; 230 231 static void stm32f2xx_usart_register_types(void) 232 { 233 type_register_static(&stm32f2xx_usart_info); 234 } 235 236 type_init(stm32f2xx_usart_register_types) 237