1 /* 2 * QEMU SCI/SCIF serial port emulation 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * 6 * Based on serial.c - QEMU 16450 UART emulation 7 * Copyright (c) 2003-2004 Fabrice Bellard 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/hw.h" 30 #include "hw/irq.h" 31 #include "hw/sh4/sh.h" 32 #include "chardev/char-fe.h" 33 #include "qapi/error.h" 34 #include "qemu/timer.h" 35 36 //#define DEBUG_SERIAL 37 38 #define SH_SERIAL_FLAG_TEND (1 << 0) 39 #define SH_SERIAL_FLAG_TDE (1 << 1) 40 #define SH_SERIAL_FLAG_RDF (1 << 2) 41 #define SH_SERIAL_FLAG_BRK (1 << 3) 42 #define SH_SERIAL_FLAG_DR (1 << 4) 43 44 #define SH_RX_FIFO_LENGTH (16) 45 46 typedef struct { 47 MemoryRegion iomem; 48 MemoryRegion iomem_p4; 49 MemoryRegion iomem_a7; 50 uint8_t smr; 51 uint8_t brr; 52 uint8_t scr; 53 uint8_t dr; /* ftdr / tdr */ 54 uint8_t sr; /* fsr / ssr */ 55 uint16_t fcr; 56 uint8_t sptr; 57 58 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ 59 uint8_t rx_cnt; 60 uint8_t rx_tail; 61 uint8_t rx_head; 62 63 int freq; 64 int feat; 65 int flags; 66 int rtrg; 67 68 CharBackend chr; 69 QEMUTimer *fifo_timeout_timer; 70 uint64_t etu; /* Elementary Time Unit (ns) */ 71 72 qemu_irq eri; 73 qemu_irq rxi; 74 qemu_irq txi; 75 qemu_irq tei; 76 qemu_irq bri; 77 } sh_serial_state; 78 79 static void sh_serial_clear_fifo(sh_serial_state * s) 80 { 81 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); 82 s->rx_cnt = 0; 83 s->rx_head = 0; 84 s->rx_tail = 0; 85 } 86 87 static void sh_serial_write(void *opaque, hwaddr offs, 88 uint64_t val, unsigned size) 89 { 90 sh_serial_state *s = opaque; 91 unsigned char ch; 92 93 #ifdef DEBUG_SERIAL 94 printf("sh_serial: write offs=0x%02x val=0x%02x\n", 95 offs, val); 96 #endif 97 switch(offs) { 98 case 0x00: /* SMR */ 99 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); 100 return; 101 case 0x04: /* BRR */ 102 s->brr = val; 103 return; 104 case 0x08: /* SCR */ 105 /* TODO : For SH7751, SCIF mask should be 0xfb. */ 106 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); 107 if (!(val & (1 << 5))) 108 s->flags |= SH_SERIAL_FLAG_TEND; 109 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { 110 qemu_set_irq(s->txi, val & (1 << 7)); 111 } 112 if (!(val & (1 << 6))) { 113 qemu_set_irq(s->rxi, 0); 114 } 115 return; 116 case 0x0c: /* FTDR / TDR */ 117 if (qemu_chr_fe_backend_connected(&s->chr)) { 118 ch = val; 119 /* XXX this blocks entire thread. Rewrite to use 120 * qemu_chr_fe_write and background I/O callbacks */ 121 qemu_chr_fe_write_all(&s->chr, &ch, 1); 122 } 123 s->dr = val; 124 s->flags &= ~SH_SERIAL_FLAG_TDE; 125 return; 126 #if 0 127 case 0x14: /* FRDR / RDR */ 128 ret = 0; 129 break; 130 #endif 131 } 132 if (s->feat & SH_SERIAL_FEAT_SCIF) { 133 switch(offs) { 134 case 0x10: /* FSR */ 135 if (!(val & (1 << 6))) 136 s->flags &= ~SH_SERIAL_FLAG_TEND; 137 if (!(val & (1 << 5))) 138 s->flags &= ~SH_SERIAL_FLAG_TDE; 139 if (!(val & (1 << 4))) 140 s->flags &= ~SH_SERIAL_FLAG_BRK; 141 if (!(val & (1 << 1))) 142 s->flags &= ~SH_SERIAL_FLAG_RDF; 143 if (!(val & (1 << 0))) 144 s->flags &= ~SH_SERIAL_FLAG_DR; 145 146 if (!(val & (1 << 1)) || !(val & (1 << 0))) { 147 if (s->rxi) { 148 qemu_set_irq(s->rxi, 0); 149 } 150 } 151 return; 152 case 0x18: /* FCR */ 153 s->fcr = val; 154 switch ((val >> 6) & 3) { 155 case 0: 156 s->rtrg = 1; 157 break; 158 case 1: 159 s->rtrg = 4; 160 break; 161 case 2: 162 s->rtrg = 8; 163 break; 164 case 3: 165 s->rtrg = 14; 166 break; 167 } 168 if (val & (1 << 1)) { 169 sh_serial_clear_fifo(s); 170 s->sr &= ~(1 << 1); 171 } 172 173 return; 174 case 0x20: /* SPTR */ 175 s->sptr = val & 0xf3; 176 return; 177 case 0x24: /* LSR */ 178 return; 179 } 180 } 181 else { 182 switch(offs) { 183 #if 0 184 case 0x0c: 185 ret = s->dr; 186 break; 187 case 0x10: 188 ret = 0; 189 break; 190 #endif 191 case 0x1c: 192 s->sptr = val & 0x8f; 193 return; 194 } 195 } 196 197 fprintf(stderr, "sh_serial: unsupported write to 0x%02" 198 HWADDR_PRIx "\n", offs); 199 abort(); 200 } 201 202 static uint64_t sh_serial_read(void *opaque, hwaddr offs, 203 unsigned size) 204 { 205 sh_serial_state *s = opaque; 206 uint32_t ret = ~0; 207 208 #if 0 209 switch(offs) { 210 case 0x00: 211 ret = s->smr; 212 break; 213 case 0x04: 214 ret = s->brr; 215 break; 216 case 0x08: 217 ret = s->scr; 218 break; 219 case 0x14: 220 ret = 0; 221 break; 222 } 223 #endif 224 if (s->feat & SH_SERIAL_FEAT_SCIF) { 225 switch(offs) { 226 case 0x00: /* SMR */ 227 ret = s->smr; 228 break; 229 case 0x08: /* SCR */ 230 ret = s->scr; 231 break; 232 case 0x10: /* FSR */ 233 ret = 0; 234 if (s->flags & SH_SERIAL_FLAG_TEND) 235 ret |= (1 << 6); 236 if (s->flags & SH_SERIAL_FLAG_TDE) 237 ret |= (1 << 5); 238 if (s->flags & SH_SERIAL_FLAG_BRK) 239 ret |= (1 << 4); 240 if (s->flags & SH_SERIAL_FLAG_RDF) 241 ret |= (1 << 1); 242 if (s->flags & SH_SERIAL_FLAG_DR) 243 ret |= (1 << 0); 244 245 if (s->scr & (1 << 5)) 246 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; 247 248 break; 249 case 0x14: 250 if (s->rx_cnt > 0) { 251 ret = s->rx_fifo[s->rx_tail++]; 252 s->rx_cnt--; 253 if (s->rx_tail == SH_RX_FIFO_LENGTH) 254 s->rx_tail = 0; 255 if (s->rx_cnt < s->rtrg) 256 s->flags &= ~SH_SERIAL_FLAG_RDF; 257 } 258 break; 259 case 0x18: 260 ret = s->fcr; 261 break; 262 case 0x1c: 263 ret = s->rx_cnt; 264 break; 265 case 0x20: 266 ret = s->sptr; 267 break; 268 case 0x24: 269 ret = 0; 270 break; 271 } 272 } 273 else { 274 switch(offs) { 275 #if 0 276 case 0x0c: 277 ret = s->dr; 278 break; 279 case 0x10: 280 ret = 0; 281 break; 282 case 0x14: 283 ret = s->rx_fifo[0]; 284 break; 285 #endif 286 case 0x1c: 287 ret = s->sptr; 288 break; 289 } 290 } 291 #ifdef DEBUG_SERIAL 292 printf("sh_serial: read offs=0x%02x val=0x%x\n", 293 offs, ret); 294 #endif 295 296 if (ret & ~((1 << 16) - 1)) { 297 fprintf(stderr, "sh_serial: unsupported read from 0x%02" 298 HWADDR_PRIx "\n", offs); 299 abort(); 300 } 301 302 return ret; 303 } 304 305 static int sh_serial_can_receive(sh_serial_state *s) 306 { 307 return s->scr & (1 << 4); 308 } 309 310 static void sh_serial_receive_break(sh_serial_state *s) 311 { 312 if (s->feat & SH_SERIAL_FEAT_SCIF) 313 s->sr |= (1 << 4); 314 } 315 316 static int sh_serial_can_receive1(void *opaque) 317 { 318 sh_serial_state *s = opaque; 319 return sh_serial_can_receive(s); 320 } 321 322 static void sh_serial_timeout_int(void *opaque) 323 { 324 sh_serial_state *s = opaque; 325 326 s->flags |= SH_SERIAL_FLAG_RDF; 327 if (s->scr & (1 << 6) && s->rxi) { 328 qemu_set_irq(s->rxi, 1); 329 } 330 } 331 332 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) 333 { 334 sh_serial_state *s = opaque; 335 336 if (s->feat & SH_SERIAL_FEAT_SCIF) { 337 int i; 338 for (i = 0; i < size; i++) { 339 if (s->rx_cnt < SH_RX_FIFO_LENGTH) { 340 s->rx_fifo[s->rx_head++] = buf[i]; 341 if (s->rx_head == SH_RX_FIFO_LENGTH) { 342 s->rx_head = 0; 343 } 344 s->rx_cnt++; 345 if (s->rx_cnt >= s->rtrg) { 346 s->flags |= SH_SERIAL_FLAG_RDF; 347 if (s->scr & (1 << 6) && s->rxi) { 348 timer_del(s->fifo_timeout_timer); 349 qemu_set_irq(s->rxi, 1); 350 } 351 } else { 352 timer_mod(s->fifo_timeout_timer, 353 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); 354 } 355 } 356 } 357 } else { 358 s->rx_fifo[0] = buf[0]; 359 } 360 } 361 362 static void sh_serial_event(void *opaque, int event) 363 { 364 sh_serial_state *s = opaque; 365 if (event == CHR_EVENT_BREAK) 366 sh_serial_receive_break(s); 367 } 368 369 static const MemoryRegionOps sh_serial_ops = { 370 .read = sh_serial_read, 371 .write = sh_serial_write, 372 .endianness = DEVICE_NATIVE_ENDIAN, 373 }; 374 375 void sh_serial_init(MemoryRegion *sysmem, 376 hwaddr base, int feat, 377 uint32_t freq, Chardev *chr, 378 qemu_irq eri_source, 379 qemu_irq rxi_source, 380 qemu_irq txi_source, 381 qemu_irq tei_source, 382 qemu_irq bri_source) 383 { 384 sh_serial_state *s; 385 386 s = g_malloc0(sizeof(sh_serial_state)); 387 388 s->feat = feat; 389 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; 390 s->rtrg = 1; 391 392 s->smr = 0; 393 s->brr = 0xff; 394 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ 395 s->sptr = 0; 396 397 if (feat & SH_SERIAL_FEAT_SCIF) { 398 s->fcr = 0; 399 } 400 else { 401 s->dr = 0xff; 402 } 403 404 sh_serial_clear_fifo(s); 405 406 memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s, 407 "serial", 0x100000000ULL); 408 409 memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem, 410 0, 0x28); 411 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 412 413 memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem, 414 0, 0x28); 415 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 416 417 if (chr) { 418 qemu_chr_fe_init(&s->chr, chr, &error_abort); 419 qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, 420 sh_serial_receive1, 421 sh_serial_event, NULL, s, NULL, true); 422 } 423 424 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 425 sh_serial_timeout_int, s); 426 s->etu = NANOSECONDS_PER_SECOND / 9600; 427 s->eri = eri_source; 428 s->rxi = rxi_source; 429 s->txi = txi_source; 430 s->tei = tei_source; 431 s->bri = bri_source; 432 } 433