1 /* 2 * QEMU 16550A UART emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2008 Citrix Systems, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "hw/char/serial.h" 27 #include "sysemu/char.h" 28 #include "qemu/timer.h" 29 #include "exec/address-spaces.h" 30 31 //#define DEBUG_SERIAL 32 33 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 34 35 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 36 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 37 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 38 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 39 40 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 41 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 42 43 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 44 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 45 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 46 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 47 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ 48 49 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ 50 #define UART_IIR_FE 0xC0 /* Fifo enabled */ 51 52 /* 53 * These are the definitions for the Modem Control Register 54 */ 55 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 56 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 57 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 58 #define UART_MCR_RTS 0x02 /* RTS complement */ 59 #define UART_MCR_DTR 0x01 /* DTR complement */ 60 61 /* 62 * These are the definitions for the Modem Status Register 63 */ 64 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 65 #define UART_MSR_RI 0x40 /* Ring Indicator */ 66 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 67 #define UART_MSR_CTS 0x10 /* Clear to Send */ 68 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 69 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 70 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 71 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 73 74 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 75 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 76 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 77 #define UART_LSR_FE 0x08 /* Frame error indicator */ 78 #define UART_LSR_PE 0x04 /* Parity error indicator */ 79 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 80 #define UART_LSR_DR 0x01 /* Receiver data ready */ 81 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ 82 83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ 84 85 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ 86 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ 87 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ 88 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ 89 90 #define UART_FCR_DMS 0x08 /* DMA Mode Select */ 91 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ 92 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ 93 #define UART_FCR_FE 0x01 /* FIFO Enable */ 94 95 #define MAX_XMIT_RETRY 4 96 97 #ifdef DEBUG_SERIAL 98 #define DPRINTF(fmt, ...) \ 99 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) 100 #else 101 #define DPRINTF(fmt, ...) \ 102 do {} while (0) 103 #endif 104 105 static void serial_receive1(void *opaque, const uint8_t *buf, int size); 106 107 static inline void recv_fifo_put(SerialState *s, uint8_t chr) 108 { 109 /* Receive overruns do not overwrite FIFO contents. */ 110 if (!fifo8_is_full(&s->recv_fifo)) { 111 fifo8_push(&s->recv_fifo, chr); 112 } else { 113 s->lsr |= UART_LSR_OE; 114 } 115 } 116 117 static void serial_update_irq(SerialState *s) 118 { 119 uint8_t tmp_iir = UART_IIR_NO_INT; 120 121 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { 122 tmp_iir = UART_IIR_RLSI; 123 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { 124 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, 125 * this is not in the specification but is observed on existing 126 * hardware. */ 127 tmp_iir = UART_IIR_CTI; 128 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && 129 (!(s->fcr & UART_FCR_FE) || 130 s->recv_fifo.num >= s->recv_fifo_itl)) { 131 tmp_iir = UART_IIR_RDI; 132 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { 133 tmp_iir = UART_IIR_THRI; 134 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { 135 tmp_iir = UART_IIR_MSI; 136 } 137 138 s->iir = tmp_iir | (s->iir & 0xF0); 139 140 if (tmp_iir != UART_IIR_NO_INT) { 141 qemu_irq_raise(s->irq); 142 } else { 143 qemu_irq_lower(s->irq); 144 } 145 } 146 147 static void serial_update_parameters(SerialState *s) 148 { 149 int speed, parity, data_bits, stop_bits, frame_size; 150 QEMUSerialSetParams ssp; 151 152 if (s->divider == 0) 153 return; 154 155 /* Start bit. */ 156 frame_size = 1; 157 if (s->lcr & 0x08) { 158 /* Parity bit. */ 159 frame_size++; 160 if (s->lcr & 0x10) 161 parity = 'E'; 162 else 163 parity = 'O'; 164 } else { 165 parity = 'N'; 166 } 167 if (s->lcr & 0x04) 168 stop_bits = 2; 169 else 170 stop_bits = 1; 171 172 data_bits = (s->lcr & 0x03) + 5; 173 frame_size += data_bits + stop_bits; 174 speed = s->baudbase / s->divider; 175 ssp.speed = speed; 176 ssp.parity = parity; 177 ssp.data_bits = data_bits; 178 ssp.stop_bits = stop_bits; 179 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 180 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 181 182 DPRINTF("speed=%d parity=%c data=%d stop=%d\n", 183 speed, parity, data_bits, stop_bits); 184 } 185 186 static void serial_update_msl(SerialState *s) 187 { 188 uint8_t omsr; 189 int flags; 190 191 qemu_del_timer(s->modem_status_poll); 192 193 if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { 194 s->poll_msl = -1; 195 return; 196 } 197 198 omsr = s->msr; 199 200 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; 201 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; 202 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; 203 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; 204 205 if (s->msr != omsr) { 206 /* Set delta bits */ 207 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); 208 /* UART_MSR_TERI only if change was from 1 -> 0 */ 209 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) 210 s->msr &= ~UART_MSR_TERI; 211 serial_update_irq(s); 212 } 213 214 /* The real 16550A apparently has a 250ns response latency to line status changes. 215 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ 216 217 if (s->poll_msl) 218 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100); 219 } 220 221 static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) 222 { 223 SerialState *s = opaque; 224 225 if (s->tsr_retry <= 0) { 226 if (s->fcr & UART_FCR_FE) { 227 s->tsr = fifo8_is_full(&s->xmit_fifo) ? 228 0 : fifo8_pop(&s->xmit_fifo); 229 if (!s->xmit_fifo.num) { 230 s->lsr |= UART_LSR_THRE; 231 } 232 } else if ((s->lsr & UART_LSR_THRE)) { 233 return FALSE; 234 } else { 235 s->tsr = s->thr; 236 s->lsr |= UART_LSR_THRE; 237 s->lsr &= ~UART_LSR_TEMT; 238 } 239 } 240 241 if (s->mcr & UART_MCR_LOOP) { 242 /* in loopback mode, say that we just received a char */ 243 serial_receive1(s, &s->tsr, 1); 244 } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { 245 if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY && 246 qemu_chr_fe_add_watch(s->chr, G_IO_OUT, serial_xmit, s) > 0) { 247 s->tsr_retry++; 248 return FALSE; 249 } 250 s->tsr_retry = 0; 251 } else { 252 s->tsr_retry = 0; 253 } 254 255 s->last_xmit_ts = qemu_get_clock_ns(vm_clock); 256 257 if (s->lsr & UART_LSR_THRE) { 258 s->lsr |= UART_LSR_TEMT; 259 s->thr_ipending = 1; 260 serial_update_irq(s); 261 } 262 263 return FALSE; 264 } 265 266 267 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 268 unsigned size) 269 { 270 SerialState *s = opaque; 271 272 addr &= 7; 273 DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val); 274 switch(addr) { 275 default: 276 case 0: 277 if (s->lcr & UART_LCR_DLAB) { 278 s->divider = (s->divider & 0xff00) | val; 279 serial_update_parameters(s); 280 } else { 281 s->thr = (uint8_t) val; 282 if(s->fcr & UART_FCR_FE) { 283 /* xmit overruns overwrite data, so make space if needed */ 284 if (fifo8_is_full(&s->xmit_fifo)) { 285 fifo8_pop(&s->xmit_fifo); 286 } 287 fifo8_push(&s->xmit_fifo, s->thr); 288 s->thr_ipending = 0; 289 s->lsr &= ~UART_LSR_TEMT; 290 s->lsr &= ~UART_LSR_THRE; 291 serial_update_irq(s); 292 } else { 293 s->thr_ipending = 0; 294 s->lsr &= ~UART_LSR_THRE; 295 serial_update_irq(s); 296 } 297 serial_xmit(NULL, G_IO_OUT, s); 298 } 299 break; 300 case 1: 301 if (s->lcr & UART_LCR_DLAB) { 302 s->divider = (s->divider & 0x00ff) | (val << 8); 303 serial_update_parameters(s); 304 } else { 305 s->ier = val & 0x0f; 306 /* If the backend device is a real serial port, turn polling of the modem 307 status lines on physical port on or off depending on UART_IER_MSI state */ 308 if (s->poll_msl >= 0) { 309 if (s->ier & UART_IER_MSI) { 310 s->poll_msl = 1; 311 serial_update_msl(s); 312 } else { 313 qemu_del_timer(s->modem_status_poll); 314 s->poll_msl = 0; 315 } 316 } 317 if (s->lsr & UART_LSR_THRE) { 318 s->thr_ipending = 1; 319 serial_update_irq(s); 320 } 321 } 322 break; 323 case 2: 324 val = val & 0xFF; 325 326 if (s->fcr == val) 327 break; 328 329 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ 330 if ((val ^ s->fcr) & UART_FCR_FE) 331 val |= UART_FCR_XFR | UART_FCR_RFR; 332 333 /* FIFO clear */ 334 335 if (val & UART_FCR_RFR) { 336 qemu_del_timer(s->fifo_timeout_timer); 337 s->timeout_ipending=0; 338 fifo8_reset(&s->recv_fifo); 339 } 340 341 if (val & UART_FCR_XFR) { 342 fifo8_reset(&s->xmit_fifo); 343 } 344 345 if (val & UART_FCR_FE) { 346 s->iir |= UART_IIR_FE; 347 /* Set recv_fifo trigger Level */ 348 switch (val & 0xC0) { 349 case UART_FCR_ITL_1: 350 s->recv_fifo_itl = 1; 351 break; 352 case UART_FCR_ITL_2: 353 s->recv_fifo_itl = 4; 354 break; 355 case UART_FCR_ITL_3: 356 s->recv_fifo_itl = 8; 357 break; 358 case UART_FCR_ITL_4: 359 s->recv_fifo_itl = 14; 360 break; 361 } 362 } else 363 s->iir &= ~UART_IIR_FE; 364 365 /* Set fcr - or at least the bits in it that are supposed to "stick" */ 366 s->fcr = val & 0xC9; 367 serial_update_irq(s); 368 break; 369 case 3: 370 { 371 int break_enable; 372 s->lcr = val; 373 serial_update_parameters(s); 374 break_enable = (val >> 6) & 1; 375 if (break_enable != s->last_break_enable) { 376 s->last_break_enable = break_enable; 377 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 378 &break_enable); 379 } 380 } 381 break; 382 case 4: 383 { 384 int flags; 385 int old_mcr = s->mcr; 386 s->mcr = val & 0x1f; 387 if (val & UART_MCR_LOOP) 388 break; 389 390 if (s->poll_msl >= 0 && old_mcr != s->mcr) { 391 392 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); 393 394 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); 395 396 if (val & UART_MCR_RTS) 397 flags |= CHR_TIOCM_RTS; 398 if (val & UART_MCR_DTR) 399 flags |= CHR_TIOCM_DTR; 400 401 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); 402 /* Update the modem status after a one-character-send wait-time, since there may be a response 403 from the device/computer at the other end of the serial line */ 404 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); 405 } 406 } 407 break; 408 case 5: 409 break; 410 case 6: 411 break; 412 case 7: 413 s->scr = val; 414 break; 415 } 416 } 417 418 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) 419 { 420 SerialState *s = opaque; 421 uint32_t ret; 422 423 addr &= 7; 424 switch(addr) { 425 default: 426 case 0: 427 if (s->lcr & UART_LCR_DLAB) { 428 ret = s->divider & 0xff; 429 } else { 430 if(s->fcr & UART_FCR_FE) { 431 ret = fifo8_is_full(&s->recv_fifo) ? 432 0 : fifo8_pop(&s->recv_fifo); 433 if (s->recv_fifo.num == 0) { 434 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 435 } else { 436 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); 437 } 438 s->timeout_ipending = 0; 439 } else { 440 ret = s->rbr; 441 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 442 } 443 serial_update_irq(s); 444 if (!(s->mcr & UART_MCR_LOOP)) { 445 /* in loopback mode, don't receive any data */ 446 qemu_chr_accept_input(s->chr); 447 } 448 } 449 break; 450 case 1: 451 if (s->lcr & UART_LCR_DLAB) { 452 ret = (s->divider >> 8) & 0xff; 453 } else { 454 ret = s->ier; 455 } 456 break; 457 case 2: 458 ret = s->iir; 459 if ((ret & UART_IIR_ID) == UART_IIR_THRI) { 460 s->thr_ipending = 0; 461 serial_update_irq(s); 462 } 463 break; 464 case 3: 465 ret = s->lcr; 466 break; 467 case 4: 468 ret = s->mcr; 469 break; 470 case 5: 471 ret = s->lsr; 472 /* Clear break and overrun interrupts */ 473 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { 474 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); 475 serial_update_irq(s); 476 } 477 break; 478 case 6: 479 if (s->mcr & UART_MCR_LOOP) { 480 /* in loopback, the modem output pins are connected to the 481 inputs */ 482 ret = (s->mcr & 0x0c) << 4; 483 ret |= (s->mcr & 0x02) << 3; 484 ret |= (s->mcr & 0x01) << 5; 485 } else { 486 if (s->poll_msl >= 0) 487 serial_update_msl(s); 488 ret = s->msr; 489 /* Clear delta bits & msr int after read, if they were set */ 490 if (s->msr & UART_MSR_ANY_DELTA) { 491 s->msr &= 0xF0; 492 serial_update_irq(s); 493 } 494 } 495 break; 496 case 7: 497 ret = s->scr; 498 break; 499 } 500 DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret); 501 return ret; 502 } 503 504 static int serial_can_receive(SerialState *s) 505 { 506 if(s->fcr & UART_FCR_FE) { 507 if (s->recv_fifo.num < UART_FIFO_LENGTH) { 508 /* 509 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 510 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the 511 * effect will be to almost always fill the fifo completely before 512 * the guest has a chance to respond, effectively overriding the ITL 513 * that the guest has set. 514 */ 515 return (s->recv_fifo.num <= s->recv_fifo_itl) ? 516 s->recv_fifo_itl - s->recv_fifo.num : 1; 517 } else { 518 return 0; 519 } 520 } else { 521 return !(s->lsr & UART_LSR_DR); 522 } 523 } 524 525 static void serial_receive_break(SerialState *s) 526 { 527 s->rbr = 0; 528 /* When the LSR_DR is set a null byte is pushed into the fifo */ 529 recv_fifo_put(s, '\0'); 530 s->lsr |= UART_LSR_BI | UART_LSR_DR; 531 serial_update_irq(s); 532 } 533 534 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ 535 static void fifo_timeout_int (void *opaque) { 536 SerialState *s = opaque; 537 if (s->recv_fifo.num) { 538 s->timeout_ipending = 1; 539 serial_update_irq(s); 540 } 541 } 542 543 static int serial_can_receive1(void *opaque) 544 { 545 SerialState *s = opaque; 546 return serial_can_receive(s); 547 } 548 549 static void serial_receive1(void *opaque, const uint8_t *buf, int size) 550 { 551 SerialState *s = opaque; 552 553 if (s->wakeup) { 554 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); 555 } 556 if(s->fcr & UART_FCR_FE) { 557 int i; 558 for (i = 0; i < size; i++) { 559 recv_fifo_put(s, buf[i]); 560 } 561 s->lsr |= UART_LSR_DR; 562 /* call the timeout receive callback in 4 char transmit time */ 563 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); 564 } else { 565 if (s->lsr & UART_LSR_DR) 566 s->lsr |= UART_LSR_OE; 567 s->rbr = buf[0]; 568 s->lsr |= UART_LSR_DR; 569 } 570 serial_update_irq(s); 571 } 572 573 static void serial_event(void *opaque, int event) 574 { 575 SerialState *s = opaque; 576 DPRINTF("event %x\n", event); 577 if (event == CHR_EVENT_BREAK) 578 serial_receive_break(s); 579 } 580 581 static void serial_pre_save(void *opaque) 582 { 583 SerialState *s = opaque; 584 s->fcr_vmstate = s->fcr; 585 } 586 587 static int serial_post_load(void *opaque, int version_id) 588 { 589 SerialState *s = opaque; 590 591 if (version_id < 3) { 592 s->fcr_vmstate = 0; 593 } 594 /* Initialize fcr via setter to perform essential side-effects */ 595 serial_ioport_write(s, 0x02, s->fcr_vmstate, 1); 596 serial_update_parameters(s); 597 return 0; 598 } 599 600 const VMStateDescription vmstate_serial = { 601 .name = "serial", 602 .version_id = 3, 603 .minimum_version_id = 2, 604 .pre_save = serial_pre_save, 605 .post_load = serial_post_load, 606 .fields = (VMStateField []) { 607 VMSTATE_UINT16_V(divider, SerialState, 2), 608 VMSTATE_UINT8(rbr, SerialState), 609 VMSTATE_UINT8(ier, SerialState), 610 VMSTATE_UINT8(iir, SerialState), 611 VMSTATE_UINT8(lcr, SerialState), 612 VMSTATE_UINT8(mcr, SerialState), 613 VMSTATE_UINT8(lsr, SerialState), 614 VMSTATE_UINT8(msr, SerialState), 615 VMSTATE_UINT8(scr, SerialState), 616 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), 617 VMSTATE_END_OF_LIST() 618 } 619 }; 620 621 static void serial_reset(void *opaque) 622 { 623 SerialState *s = opaque; 624 625 s->rbr = 0; 626 s->ier = 0; 627 s->iir = UART_IIR_NO_INT; 628 s->lcr = 0; 629 s->lsr = UART_LSR_TEMT | UART_LSR_THRE; 630 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; 631 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ 632 s->divider = 0x0C; 633 s->mcr = UART_MCR_OUT2; 634 s->scr = 0; 635 s->tsr_retry = 0; 636 s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; 637 s->poll_msl = 0; 638 639 fifo8_reset(&s->recv_fifo); 640 fifo8_reset(&s->xmit_fifo); 641 642 s->last_xmit_ts = qemu_get_clock_ns(vm_clock); 643 644 s->thr_ipending = 0; 645 s->last_break_enable = 0; 646 qemu_irq_lower(s->irq); 647 } 648 649 void serial_init_core(SerialState *s) 650 { 651 if (!s->chr) { 652 fprintf(stderr, "Can't create serial device, empty char device\n"); 653 exit(1); 654 } 655 656 s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); 657 658 s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); 659 qemu_register_reset(serial_reset, s); 660 661 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, 662 serial_event, s); 663 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); 664 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); 665 } 666 667 void serial_exit_core(SerialState *s) 668 { 669 qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL); 670 qemu_unregister_reset(serial_reset, s); 671 } 672 673 /* Change the main reference oscillator frequency. */ 674 void serial_set_frequency(SerialState *s, uint32_t frequency) 675 { 676 s->baudbase = frequency; 677 serial_update_parameters(s); 678 } 679 680 const MemoryRegionOps serial_io_ops = { 681 .read = serial_ioport_read, 682 .write = serial_ioport_write, 683 .impl = { 684 .min_access_size = 1, 685 .max_access_size = 1, 686 }, 687 .endianness = DEVICE_LITTLE_ENDIAN, 688 }; 689 690 SerialState *serial_init(int base, qemu_irq irq, int baudbase, 691 CharDriverState *chr, MemoryRegion *system_io) 692 { 693 SerialState *s; 694 695 s = g_malloc0(sizeof(SerialState)); 696 697 s->irq = irq; 698 s->baudbase = baudbase; 699 s->chr = chr; 700 serial_init_core(s); 701 702 vmstate_register(NULL, base, &vmstate_serial, s); 703 704 memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8); 705 memory_region_add_subregion(system_io, base, &s->io); 706 707 return s; 708 } 709 710 /* Memory mapped interface */ 711 static uint64_t serial_mm_read(void *opaque, hwaddr addr, 712 unsigned size) 713 { 714 SerialState *s = opaque; 715 return serial_ioport_read(s, addr >> s->it_shift, 1); 716 } 717 718 static void serial_mm_write(void *opaque, hwaddr addr, 719 uint64_t value, unsigned size) 720 { 721 SerialState *s = opaque; 722 value &= ~0u >> (32 - (size * 8)); 723 serial_ioport_write(s, addr >> s->it_shift, value, 1); 724 } 725 726 static const MemoryRegionOps serial_mm_ops[3] = { 727 [DEVICE_NATIVE_ENDIAN] = { 728 .read = serial_mm_read, 729 .write = serial_mm_write, 730 .endianness = DEVICE_NATIVE_ENDIAN, 731 }, 732 [DEVICE_LITTLE_ENDIAN] = { 733 .read = serial_mm_read, 734 .write = serial_mm_write, 735 .endianness = DEVICE_LITTLE_ENDIAN, 736 }, 737 [DEVICE_BIG_ENDIAN] = { 738 .read = serial_mm_read, 739 .write = serial_mm_write, 740 .endianness = DEVICE_BIG_ENDIAN, 741 }, 742 }; 743 744 SerialState *serial_mm_init(MemoryRegion *address_space, 745 hwaddr base, int it_shift, 746 qemu_irq irq, int baudbase, 747 CharDriverState *chr, enum device_endian end) 748 { 749 SerialState *s; 750 751 s = g_malloc0(sizeof(SerialState)); 752 753 s->it_shift = it_shift; 754 s->irq = irq; 755 s->baudbase = baudbase; 756 s->chr = chr; 757 758 serial_init_core(s); 759 vmstate_register(NULL, base, &vmstate_serial, s); 760 761 memory_region_init_io(&s->io, &serial_mm_ops[end], s, 762 "serial", 8 << it_shift); 763 memory_region_add_subregion(address_space, base, &s->io); 764 765 serial_update_msl(s); 766 return s; 767 } 768