1 /* 2 * QEMU 16550A UART emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2008 Citrix Systems, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "hw/char/serial.h" 27 #include "sysemu/char.h" 28 #include "qemu/timer.h" 29 #include "exec/address-spaces.h" 30 #include "qemu/error-report.h" 31 32 //#define DEBUG_SERIAL 33 34 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 35 36 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 37 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 38 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 39 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 40 41 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 42 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 43 44 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 45 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 46 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 47 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 48 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ 49 50 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ 51 #define UART_IIR_FE 0xC0 /* Fifo enabled */ 52 53 /* 54 * These are the definitions for the Modem Control Register 55 */ 56 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 57 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 58 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 59 #define UART_MCR_RTS 0x02 /* RTS complement */ 60 #define UART_MCR_DTR 0x01 /* DTR complement */ 61 62 /* 63 * These are the definitions for the Modem Status Register 64 */ 65 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 66 #define UART_MSR_RI 0x40 /* Ring Indicator */ 67 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 68 #define UART_MSR_CTS 0x10 /* Clear to Send */ 69 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 70 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 71 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 72 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 74 75 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 76 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 77 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 78 #define UART_LSR_FE 0x08 /* Frame error indicator */ 79 #define UART_LSR_PE 0x04 /* Parity error indicator */ 80 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 81 #define UART_LSR_DR 0x01 /* Receiver data ready */ 82 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ 83 84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ 85 86 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ 87 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ 88 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ 89 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ 90 91 #define UART_FCR_DMS 0x08 /* DMA Mode Select */ 92 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ 93 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ 94 #define UART_FCR_FE 0x01 /* FIFO Enable */ 95 96 #define MAX_XMIT_RETRY 4 97 98 #ifdef DEBUG_SERIAL 99 #define DPRINTF(fmt, ...) \ 100 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) 101 #else 102 #define DPRINTF(fmt, ...) \ 103 do {} while (0) 104 #endif 105 106 static void serial_receive1(void *opaque, const uint8_t *buf, int size); 107 108 static inline void recv_fifo_put(SerialState *s, uint8_t chr) 109 { 110 /* Receive overruns do not overwrite FIFO contents. */ 111 if (!fifo8_is_full(&s->recv_fifo)) { 112 fifo8_push(&s->recv_fifo, chr); 113 } else { 114 s->lsr |= UART_LSR_OE; 115 } 116 } 117 118 static void serial_update_irq(SerialState *s) 119 { 120 uint8_t tmp_iir = UART_IIR_NO_INT; 121 122 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { 123 tmp_iir = UART_IIR_RLSI; 124 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { 125 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, 126 * this is not in the specification but is observed on existing 127 * hardware. */ 128 tmp_iir = UART_IIR_CTI; 129 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && 130 (!(s->fcr & UART_FCR_FE) || 131 s->recv_fifo.num >= s->recv_fifo_itl)) { 132 tmp_iir = UART_IIR_RDI; 133 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { 134 tmp_iir = UART_IIR_THRI; 135 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { 136 tmp_iir = UART_IIR_MSI; 137 } 138 139 s->iir = tmp_iir | (s->iir & 0xF0); 140 141 if (tmp_iir != UART_IIR_NO_INT) { 142 qemu_irq_raise(s->irq); 143 } else { 144 qemu_irq_lower(s->irq); 145 } 146 } 147 148 static void serial_update_parameters(SerialState *s) 149 { 150 int speed, parity, data_bits, stop_bits, frame_size; 151 QEMUSerialSetParams ssp; 152 153 if (s->divider == 0) 154 return; 155 156 /* Start bit. */ 157 frame_size = 1; 158 if (s->lcr & 0x08) { 159 /* Parity bit. */ 160 frame_size++; 161 if (s->lcr & 0x10) 162 parity = 'E'; 163 else 164 parity = 'O'; 165 } else { 166 parity = 'N'; 167 } 168 if (s->lcr & 0x04) 169 stop_bits = 2; 170 else 171 stop_bits = 1; 172 173 data_bits = (s->lcr & 0x03) + 5; 174 frame_size += data_bits + stop_bits; 175 speed = s->baudbase / s->divider; 176 ssp.speed = speed; 177 ssp.parity = parity; 178 ssp.data_bits = data_bits; 179 ssp.stop_bits = stop_bits; 180 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 181 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 182 183 DPRINTF("speed=%d parity=%c data=%d stop=%d\n", 184 speed, parity, data_bits, stop_bits); 185 } 186 187 static void serial_update_msl(SerialState *s) 188 { 189 uint8_t omsr; 190 int flags; 191 192 timer_del(s->modem_status_poll); 193 194 if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { 195 s->poll_msl = -1; 196 return; 197 } 198 199 omsr = s->msr; 200 201 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; 202 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; 203 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; 204 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; 205 206 if (s->msr != omsr) { 207 /* Set delta bits */ 208 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); 209 /* UART_MSR_TERI only if change was from 1 -> 0 */ 210 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) 211 s->msr &= ~UART_MSR_TERI; 212 serial_update_irq(s); 213 } 214 215 /* The real 16550A apparently has a 250ns response latency to line status changes. 216 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ 217 218 if (s->poll_msl) 219 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100); 220 } 221 222 static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) 223 { 224 SerialState *s = opaque; 225 226 do { 227 if (s->tsr_retry <= 0) { 228 if (s->fcr & UART_FCR_FE) { 229 if (fifo8_is_empty(&s->xmit_fifo)) { 230 return FALSE; 231 } 232 s->tsr = fifo8_pop(&s->xmit_fifo); 233 if (!s->xmit_fifo.num) { 234 s->lsr |= UART_LSR_THRE; 235 } 236 } else if ((s->lsr & UART_LSR_THRE)) { 237 return FALSE; 238 } else { 239 s->tsr = s->thr; 240 s->lsr |= UART_LSR_THRE; 241 s->lsr &= ~UART_LSR_TEMT; 242 } 243 } 244 245 if (s->mcr & UART_MCR_LOOP) { 246 /* in loopback mode, say that we just received a char */ 247 serial_receive1(s, &s->tsr, 1); 248 } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { 249 if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY && 250 qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, 251 serial_xmit, s) > 0) { 252 s->tsr_retry++; 253 return FALSE; 254 } 255 s->tsr_retry = 0; 256 } else { 257 s->tsr_retry = 0; 258 } 259 /* Transmit another byte if it is already available. It is only 260 possible when FIFO is enabled and not empty. */ 261 } while ((s->fcr & UART_FCR_FE) && !fifo8_is_empty(&s->xmit_fifo)); 262 263 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 264 265 if (s->lsr & UART_LSR_THRE) { 266 s->lsr |= UART_LSR_TEMT; 267 s->thr_ipending = 1; 268 serial_update_irq(s); 269 } 270 271 return FALSE; 272 } 273 274 275 /* Setter for FCR. 276 is_load flag means, that value is set while loading VM state 277 and interrupt should not be invoked */ 278 static void serial_write_fcr(SerialState *s, uint8_t val) 279 { 280 /* Set fcr - val only has the bits that are supposed to "stick" */ 281 s->fcr = val; 282 283 if (val & UART_FCR_FE) { 284 s->iir |= UART_IIR_FE; 285 /* Set recv_fifo trigger Level */ 286 switch (val & 0xC0) { 287 case UART_FCR_ITL_1: 288 s->recv_fifo_itl = 1; 289 break; 290 case UART_FCR_ITL_2: 291 s->recv_fifo_itl = 4; 292 break; 293 case UART_FCR_ITL_3: 294 s->recv_fifo_itl = 8; 295 break; 296 case UART_FCR_ITL_4: 297 s->recv_fifo_itl = 14; 298 break; 299 } 300 } else { 301 s->iir &= ~UART_IIR_FE; 302 } 303 } 304 305 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 306 unsigned size) 307 { 308 SerialState *s = opaque; 309 310 addr &= 7; 311 DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val); 312 switch(addr) { 313 default: 314 case 0: 315 if (s->lcr & UART_LCR_DLAB) { 316 s->divider = (s->divider & 0xff00) | val; 317 serial_update_parameters(s); 318 } else { 319 s->thr = (uint8_t) val; 320 if(s->fcr & UART_FCR_FE) { 321 /* xmit overruns overwrite data, so make space if needed */ 322 if (fifo8_is_full(&s->xmit_fifo)) { 323 fifo8_pop(&s->xmit_fifo); 324 } 325 fifo8_push(&s->xmit_fifo, s->thr); 326 s->lsr &= ~UART_LSR_TEMT; 327 } 328 s->thr_ipending = 0; 329 s->lsr &= ~UART_LSR_THRE; 330 serial_update_irq(s); 331 if (s->tsr_retry <= 0) { 332 serial_xmit(NULL, G_IO_OUT, s); 333 } 334 } 335 break; 336 case 1: 337 if (s->lcr & UART_LCR_DLAB) { 338 s->divider = (s->divider & 0x00ff) | (val << 8); 339 serial_update_parameters(s); 340 } else { 341 s->ier = val & 0x0f; 342 /* If the backend device is a real serial port, turn polling of the modem 343 status lines on physical port on or off depending on UART_IER_MSI state */ 344 if (s->poll_msl >= 0) { 345 if (s->ier & UART_IER_MSI) { 346 s->poll_msl = 1; 347 serial_update_msl(s); 348 } else { 349 timer_del(s->modem_status_poll); 350 s->poll_msl = 0; 351 } 352 } 353 if (s->lsr & UART_LSR_THRE) { 354 s->thr_ipending = 1; 355 serial_update_irq(s); 356 } 357 } 358 break; 359 case 2: 360 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ 361 if ((val ^ s->fcr) & UART_FCR_FE) { 362 val |= UART_FCR_XFR | UART_FCR_RFR; 363 } 364 365 /* FIFO clear */ 366 367 if (val & UART_FCR_RFR) { 368 timer_del(s->fifo_timeout_timer); 369 s->timeout_ipending = 0; 370 fifo8_reset(&s->recv_fifo); 371 } 372 373 if (val & UART_FCR_XFR) { 374 fifo8_reset(&s->xmit_fifo); 375 } 376 377 serial_write_fcr(s, val & 0xC9); 378 serial_update_irq(s); 379 break; 380 case 3: 381 { 382 int break_enable; 383 s->lcr = val; 384 serial_update_parameters(s); 385 break_enable = (val >> 6) & 1; 386 if (break_enable != s->last_break_enable) { 387 s->last_break_enable = break_enable; 388 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 389 &break_enable); 390 } 391 } 392 break; 393 case 4: 394 { 395 int flags; 396 int old_mcr = s->mcr; 397 s->mcr = val & 0x1f; 398 if (val & UART_MCR_LOOP) 399 break; 400 401 if (s->poll_msl >= 0 && old_mcr != s->mcr) { 402 403 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); 404 405 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); 406 407 if (val & UART_MCR_RTS) 408 flags |= CHR_TIOCM_RTS; 409 if (val & UART_MCR_DTR) 410 flags |= CHR_TIOCM_DTR; 411 412 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); 413 /* Update the modem status after a one-character-send wait-time, since there may be a response 414 from the device/computer at the other end of the serial line */ 415 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); 416 } 417 } 418 break; 419 case 5: 420 break; 421 case 6: 422 break; 423 case 7: 424 s->scr = val; 425 break; 426 } 427 } 428 429 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) 430 { 431 SerialState *s = opaque; 432 uint32_t ret; 433 434 addr &= 7; 435 switch(addr) { 436 default: 437 case 0: 438 if (s->lcr & UART_LCR_DLAB) { 439 ret = s->divider & 0xff; 440 } else { 441 if(s->fcr & UART_FCR_FE) { 442 ret = fifo8_is_empty(&s->recv_fifo) ? 443 0 : fifo8_pop(&s->recv_fifo); 444 if (s->recv_fifo.num == 0) { 445 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 446 } else { 447 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); 448 } 449 s->timeout_ipending = 0; 450 } else { 451 ret = s->rbr; 452 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 453 } 454 serial_update_irq(s); 455 if (!(s->mcr & UART_MCR_LOOP)) { 456 /* in loopback mode, don't receive any data */ 457 qemu_chr_accept_input(s->chr); 458 } 459 } 460 break; 461 case 1: 462 if (s->lcr & UART_LCR_DLAB) { 463 ret = (s->divider >> 8) & 0xff; 464 } else { 465 ret = s->ier; 466 } 467 break; 468 case 2: 469 ret = s->iir; 470 if ((ret & UART_IIR_ID) == UART_IIR_THRI) { 471 s->thr_ipending = 0; 472 serial_update_irq(s); 473 } 474 break; 475 case 3: 476 ret = s->lcr; 477 break; 478 case 4: 479 ret = s->mcr; 480 break; 481 case 5: 482 ret = s->lsr; 483 /* Clear break and overrun interrupts */ 484 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { 485 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); 486 serial_update_irq(s); 487 } 488 break; 489 case 6: 490 if (s->mcr & UART_MCR_LOOP) { 491 /* in loopback, the modem output pins are connected to the 492 inputs */ 493 ret = (s->mcr & 0x0c) << 4; 494 ret |= (s->mcr & 0x02) << 3; 495 ret |= (s->mcr & 0x01) << 5; 496 } else { 497 if (s->poll_msl >= 0) 498 serial_update_msl(s); 499 ret = s->msr; 500 /* Clear delta bits & msr int after read, if they were set */ 501 if (s->msr & UART_MSR_ANY_DELTA) { 502 s->msr &= 0xF0; 503 serial_update_irq(s); 504 } 505 } 506 break; 507 case 7: 508 ret = s->scr; 509 break; 510 } 511 DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret); 512 return ret; 513 } 514 515 static int serial_can_receive(SerialState *s) 516 { 517 if(s->fcr & UART_FCR_FE) { 518 if (s->recv_fifo.num < UART_FIFO_LENGTH) { 519 /* 520 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 521 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the 522 * effect will be to almost always fill the fifo completely before 523 * the guest has a chance to respond, effectively overriding the ITL 524 * that the guest has set. 525 */ 526 return (s->recv_fifo.num <= s->recv_fifo_itl) ? 527 s->recv_fifo_itl - s->recv_fifo.num : 1; 528 } else { 529 return 0; 530 } 531 } else { 532 return !(s->lsr & UART_LSR_DR); 533 } 534 } 535 536 static void serial_receive_break(SerialState *s) 537 { 538 s->rbr = 0; 539 /* When the LSR_DR is set a null byte is pushed into the fifo */ 540 recv_fifo_put(s, '\0'); 541 s->lsr |= UART_LSR_BI | UART_LSR_DR; 542 serial_update_irq(s); 543 } 544 545 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ 546 static void fifo_timeout_int (void *opaque) { 547 SerialState *s = opaque; 548 if (s->recv_fifo.num) { 549 s->timeout_ipending = 1; 550 serial_update_irq(s); 551 } 552 } 553 554 static int serial_can_receive1(void *opaque) 555 { 556 SerialState *s = opaque; 557 return serial_can_receive(s); 558 } 559 560 static void serial_receive1(void *opaque, const uint8_t *buf, int size) 561 { 562 SerialState *s = opaque; 563 564 if (s->wakeup) { 565 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); 566 } 567 if(s->fcr & UART_FCR_FE) { 568 int i; 569 for (i = 0; i < size; i++) { 570 recv_fifo_put(s, buf[i]); 571 } 572 s->lsr |= UART_LSR_DR; 573 /* call the timeout receive callback in 4 char transmit time */ 574 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); 575 } else { 576 if (s->lsr & UART_LSR_DR) 577 s->lsr |= UART_LSR_OE; 578 s->rbr = buf[0]; 579 s->lsr |= UART_LSR_DR; 580 } 581 serial_update_irq(s); 582 } 583 584 static void serial_event(void *opaque, int event) 585 { 586 SerialState *s = opaque; 587 DPRINTF("event %x\n", event); 588 if (event == CHR_EVENT_BREAK) 589 serial_receive_break(s); 590 } 591 592 static void serial_pre_save(void *opaque) 593 { 594 SerialState *s = opaque; 595 s->fcr_vmstate = s->fcr; 596 } 597 598 static int serial_pre_load(void *opaque) 599 { 600 SerialState *s = opaque; 601 s->thr_ipending = -1; 602 s->poll_msl = -1; 603 return 0; 604 } 605 606 static int serial_post_load(void *opaque, int version_id) 607 { 608 SerialState *s = opaque; 609 610 if (version_id < 3) { 611 s->fcr_vmstate = 0; 612 } 613 if (s->thr_ipending == -1) { 614 s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); 615 } 616 s->last_break_enable = (s->lcr >> 6) & 1; 617 /* Initialize fcr via setter to perform essential side-effects */ 618 serial_write_fcr(s, s->fcr_vmstate); 619 serial_update_parameters(s); 620 return 0; 621 } 622 623 static bool serial_thr_ipending_needed(void *opaque) 624 { 625 SerialState *s = opaque; 626 bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); 627 return s->thr_ipending != expected_value; 628 } 629 630 const VMStateDescription vmstate_serial_thr_ipending = { 631 .name = "serial/thr_ipending", 632 .version_id = 1, 633 .minimum_version_id = 1, 634 .fields = (VMStateField[]) { 635 VMSTATE_INT32(thr_ipending, SerialState), 636 VMSTATE_END_OF_LIST() 637 } 638 }; 639 640 static bool serial_tsr_needed(void *opaque) 641 { 642 SerialState *s = (SerialState *)opaque; 643 return s->tsr_retry != 0; 644 } 645 646 const VMStateDescription vmstate_serial_tsr = { 647 .name = "serial/tsr", 648 .version_id = 1, 649 .minimum_version_id = 1, 650 .fields = (VMStateField[]) { 651 VMSTATE_INT32(tsr_retry, SerialState), 652 VMSTATE_UINT8(thr, SerialState), 653 VMSTATE_UINT8(tsr, SerialState), 654 VMSTATE_END_OF_LIST() 655 } 656 }; 657 658 static bool serial_recv_fifo_needed(void *opaque) 659 { 660 SerialState *s = (SerialState *)opaque; 661 return !fifo8_is_empty(&s->recv_fifo); 662 663 } 664 665 const VMStateDescription vmstate_serial_recv_fifo = { 666 .name = "serial/recv_fifo", 667 .version_id = 1, 668 .minimum_version_id = 1, 669 .fields = (VMStateField[]) { 670 VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), 671 VMSTATE_END_OF_LIST() 672 } 673 }; 674 675 static bool serial_xmit_fifo_needed(void *opaque) 676 { 677 SerialState *s = (SerialState *)opaque; 678 return !fifo8_is_empty(&s->xmit_fifo); 679 } 680 681 const VMStateDescription vmstate_serial_xmit_fifo = { 682 .name = "serial/xmit_fifo", 683 .version_id = 1, 684 .minimum_version_id = 1, 685 .fields = (VMStateField[]) { 686 VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), 687 VMSTATE_END_OF_LIST() 688 } 689 }; 690 691 static bool serial_fifo_timeout_timer_needed(void *opaque) 692 { 693 SerialState *s = (SerialState *)opaque; 694 return timer_pending(s->fifo_timeout_timer); 695 } 696 697 const VMStateDescription vmstate_serial_fifo_timeout_timer = { 698 .name = "serial/fifo_timeout_timer", 699 .version_id = 1, 700 .minimum_version_id = 1, 701 .fields = (VMStateField[]) { 702 VMSTATE_TIMER(fifo_timeout_timer, SerialState), 703 VMSTATE_END_OF_LIST() 704 } 705 }; 706 707 static bool serial_timeout_ipending_needed(void *opaque) 708 { 709 SerialState *s = (SerialState *)opaque; 710 return s->timeout_ipending != 0; 711 } 712 713 const VMStateDescription vmstate_serial_timeout_ipending = { 714 .name = "serial/timeout_ipending", 715 .version_id = 1, 716 .minimum_version_id = 1, 717 .fields = (VMStateField[]) { 718 VMSTATE_INT32(timeout_ipending, SerialState), 719 VMSTATE_END_OF_LIST() 720 } 721 }; 722 723 static bool serial_poll_needed(void *opaque) 724 { 725 SerialState *s = (SerialState *)opaque; 726 return s->poll_msl >= 0; 727 } 728 729 const VMStateDescription vmstate_serial_poll = { 730 .name = "serial/poll", 731 .version_id = 1, 732 .minimum_version_id = 1, 733 .fields = (VMStateField[]) { 734 VMSTATE_INT32(poll_msl, SerialState), 735 VMSTATE_TIMER(modem_status_poll, SerialState), 736 VMSTATE_END_OF_LIST() 737 } 738 }; 739 740 const VMStateDescription vmstate_serial = { 741 .name = "serial", 742 .version_id = 3, 743 .minimum_version_id = 2, 744 .pre_save = serial_pre_save, 745 .pre_load = serial_pre_load, 746 .post_load = serial_post_load, 747 .fields = (VMStateField[]) { 748 VMSTATE_UINT16_V(divider, SerialState, 2), 749 VMSTATE_UINT8(rbr, SerialState), 750 VMSTATE_UINT8(ier, SerialState), 751 VMSTATE_UINT8(iir, SerialState), 752 VMSTATE_UINT8(lcr, SerialState), 753 VMSTATE_UINT8(mcr, SerialState), 754 VMSTATE_UINT8(lsr, SerialState), 755 VMSTATE_UINT8(msr, SerialState), 756 VMSTATE_UINT8(scr, SerialState), 757 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), 758 VMSTATE_END_OF_LIST() 759 }, 760 .subsections = (VMStateSubsection[]) { 761 { 762 .vmsd = &vmstate_serial_thr_ipending, 763 .needed = &serial_thr_ipending_needed, 764 } , { 765 .vmsd = &vmstate_serial_tsr, 766 .needed = &serial_tsr_needed, 767 } , { 768 .vmsd = &vmstate_serial_recv_fifo, 769 .needed = &serial_recv_fifo_needed, 770 } , { 771 .vmsd = &vmstate_serial_xmit_fifo, 772 .needed = &serial_xmit_fifo_needed, 773 } , { 774 .vmsd = &vmstate_serial_fifo_timeout_timer, 775 .needed = &serial_fifo_timeout_timer_needed, 776 } , { 777 .vmsd = &vmstate_serial_timeout_ipending, 778 .needed = &serial_timeout_ipending_needed, 779 } , { 780 .vmsd = &vmstate_serial_poll, 781 .needed = &serial_poll_needed, 782 } , { 783 /* empty */ 784 } 785 } 786 }; 787 788 static void serial_reset(void *opaque) 789 { 790 SerialState *s = opaque; 791 792 s->rbr = 0; 793 s->ier = 0; 794 s->iir = UART_IIR_NO_INT; 795 s->lcr = 0; 796 s->lsr = UART_LSR_TEMT | UART_LSR_THRE; 797 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; 798 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ 799 s->divider = 0x0C; 800 s->mcr = UART_MCR_OUT2; 801 s->scr = 0; 802 s->tsr_retry = 0; 803 s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; 804 s->poll_msl = 0; 805 806 s->timeout_ipending = 0; 807 timer_del(s->fifo_timeout_timer); 808 timer_del(s->modem_status_poll); 809 810 fifo8_reset(&s->recv_fifo); 811 fifo8_reset(&s->xmit_fifo); 812 813 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 814 815 s->thr_ipending = 0; 816 s->last_break_enable = 0; 817 qemu_irq_lower(s->irq); 818 } 819 820 void serial_realize_core(SerialState *s, Error **errp) 821 { 822 if (!s->chr) { 823 error_setg(errp, "Can't create serial device, empty char device"); 824 return; 825 } 826 827 s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); 828 829 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); 830 qemu_register_reset(serial_reset, s); 831 832 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, 833 serial_event, s); 834 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); 835 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); 836 } 837 838 void serial_exit_core(SerialState *s) 839 { 840 qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL); 841 qemu_unregister_reset(serial_reset, s); 842 } 843 844 /* Change the main reference oscillator frequency. */ 845 void serial_set_frequency(SerialState *s, uint32_t frequency) 846 { 847 s->baudbase = frequency; 848 serial_update_parameters(s); 849 } 850 851 const MemoryRegionOps serial_io_ops = { 852 .read = serial_ioport_read, 853 .write = serial_ioport_write, 854 .impl = { 855 .min_access_size = 1, 856 .max_access_size = 1, 857 }, 858 .endianness = DEVICE_LITTLE_ENDIAN, 859 }; 860 861 SerialState *serial_init(int base, qemu_irq irq, int baudbase, 862 CharDriverState *chr, MemoryRegion *system_io) 863 { 864 SerialState *s; 865 Error *err = NULL; 866 867 s = g_malloc0(sizeof(SerialState)); 868 869 s->irq = irq; 870 s->baudbase = baudbase; 871 s->chr = chr; 872 serial_realize_core(s, &err); 873 if (err != NULL) { 874 error_report("%s", error_get_pretty(err)); 875 error_free(err); 876 exit(1); 877 } 878 879 vmstate_register(NULL, base, &vmstate_serial, s); 880 881 memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); 882 memory_region_add_subregion(system_io, base, &s->io); 883 884 return s; 885 } 886 887 /* Memory mapped interface */ 888 static uint64_t serial_mm_read(void *opaque, hwaddr addr, 889 unsigned size) 890 { 891 SerialState *s = opaque; 892 return serial_ioport_read(s, addr >> s->it_shift, 1); 893 } 894 895 static void serial_mm_write(void *opaque, hwaddr addr, 896 uint64_t value, unsigned size) 897 { 898 SerialState *s = opaque; 899 value &= ~0u >> (32 - (size * 8)); 900 serial_ioport_write(s, addr >> s->it_shift, value, 1); 901 } 902 903 static const MemoryRegionOps serial_mm_ops[3] = { 904 [DEVICE_NATIVE_ENDIAN] = { 905 .read = serial_mm_read, 906 .write = serial_mm_write, 907 .endianness = DEVICE_NATIVE_ENDIAN, 908 }, 909 [DEVICE_LITTLE_ENDIAN] = { 910 .read = serial_mm_read, 911 .write = serial_mm_write, 912 .endianness = DEVICE_LITTLE_ENDIAN, 913 }, 914 [DEVICE_BIG_ENDIAN] = { 915 .read = serial_mm_read, 916 .write = serial_mm_write, 917 .endianness = DEVICE_BIG_ENDIAN, 918 }, 919 }; 920 921 SerialState *serial_mm_init(MemoryRegion *address_space, 922 hwaddr base, int it_shift, 923 qemu_irq irq, int baudbase, 924 CharDriverState *chr, enum device_endian end) 925 { 926 SerialState *s; 927 Error *err = NULL; 928 929 s = g_malloc0(sizeof(SerialState)); 930 931 s->it_shift = it_shift; 932 s->irq = irq; 933 s->baudbase = baudbase; 934 s->chr = chr; 935 936 serial_realize_core(s, &err); 937 if (err != NULL) { 938 error_report("%s", error_get_pretty(err)); 939 error_free(err); 940 exit(1); 941 } 942 vmstate_register(NULL, base, &vmstate_serial, s); 943 944 memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, 945 "serial", 8 << it_shift); 946 memory_region_add_subregion(address_space, base, &s->io); 947 948 serial_update_msl(s); 949 return s; 950 } 951