1 /* 2 * QEMU 16550A multi UART emulation 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Copyright (c) 2003-2004 Fabrice Bellard 7 * Copyright (c) 2008 Citrix Systems, Inc. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 /* see docs/specs/pci-serial.txt */ 29 30 #include "qemu/osdep.h" 31 #include "qapi/error.h" 32 #include "hw/char/serial.h" 33 #include "hw/irq.h" 34 #include "hw/pci/pci.h" 35 #include "migration/vmstate.h" 36 37 #define PCI_SERIAL_MAX_PORTS 4 38 39 typedef struct PCIMultiSerialState { 40 PCIDevice dev; 41 MemoryRegion iobar; 42 uint32_t ports; 43 char *name[PCI_SERIAL_MAX_PORTS]; 44 SerialState state[PCI_SERIAL_MAX_PORTS]; 45 uint32_t level[PCI_SERIAL_MAX_PORTS]; 46 qemu_irq *irqs; 47 uint8_t prog_if; 48 } PCIMultiSerialState; 49 50 static void multi_serial_pci_exit(PCIDevice *dev) 51 { 52 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 53 SerialState *s; 54 int i; 55 56 for (i = 0; i < pci->ports; i++) { 57 s = pci->state + i; 58 serial_exit_core(s); 59 memory_region_del_subregion(&pci->iobar, &s->io); 60 g_free(pci->name[i]); 61 } 62 qemu_free_irqs(pci->irqs, pci->ports); 63 } 64 65 static void multi_serial_irq_mux(void *opaque, int n, int level) 66 { 67 PCIMultiSerialState *pci = opaque; 68 int i, pending = 0; 69 70 pci->level[n] = level; 71 for (i = 0; i < pci->ports; i++) { 72 if (pci->level[i]) { 73 pending = 1; 74 } 75 } 76 pci_set_irq(&pci->dev, pending); 77 } 78 79 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) 80 { 81 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 82 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 83 SerialState *s; 84 Error *err = NULL; 85 int i, nr_ports = 0; 86 87 switch (pc->device_id) { 88 case 0x0003: 89 nr_ports = 2; 90 break; 91 case 0x0004: 92 nr_ports = 4; 93 break; 94 } 95 assert(nr_ports > 0); 96 assert(nr_ports <= PCI_SERIAL_MAX_PORTS); 97 98 pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; 99 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; 100 memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports); 101 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); 102 pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, 103 nr_ports); 104 105 for (i = 0; i < nr_ports; i++) { 106 s = pci->state + i; 107 s->baudbase = 115200; 108 serial_realize_core(s, &err); 109 if (err != NULL) { 110 error_propagate(errp, err); 111 multi_serial_pci_exit(dev); 112 return; 113 } 114 s->irq = pci->irqs[i]; 115 pci->name[i] = g_strdup_printf("uart #%d", i + 1); 116 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, 117 pci->name[i], 8); 118 memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); 119 pci->ports++; 120 } 121 } 122 123 static const VMStateDescription vmstate_pci_multi_serial = { 124 .name = "pci-serial-multi", 125 .version_id = 1, 126 .minimum_version_id = 1, 127 .fields = (VMStateField[]) { 128 VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), 129 VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 130 0, vmstate_serial, SerialState), 131 VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), 132 VMSTATE_END_OF_LIST() 133 } 134 }; 135 136 static Property multi_2x_serial_pci_properties[] = { 137 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 138 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 139 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 140 DEFINE_PROP_END_OF_LIST(), 141 }; 142 143 static Property multi_4x_serial_pci_properties[] = { 144 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 145 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 146 DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr), 147 DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr), 148 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 149 DEFINE_PROP_END_OF_LIST(), 150 }; 151 152 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 156 pc->realize = multi_serial_pci_realize; 157 pc->exit = multi_serial_pci_exit; 158 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 159 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2; 160 pc->revision = 1; 161 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 162 dc->vmsd = &vmstate_pci_multi_serial; 163 dc->props = multi_2x_serial_pci_properties; 164 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 165 } 166 167 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) 168 { 169 DeviceClass *dc = DEVICE_CLASS(klass); 170 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 171 pc->realize = multi_serial_pci_realize; 172 pc->exit = multi_serial_pci_exit; 173 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 174 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4; 175 pc->revision = 1; 176 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 177 dc->vmsd = &vmstate_pci_multi_serial; 178 dc->props = multi_4x_serial_pci_properties; 179 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 180 } 181 182 static const TypeInfo multi_2x_serial_pci_info = { 183 .name = "pci-serial-2x", 184 .parent = TYPE_PCI_DEVICE, 185 .instance_size = sizeof(PCIMultiSerialState), 186 .class_init = multi_2x_serial_pci_class_initfn, 187 .interfaces = (InterfaceInfo[]) { 188 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 189 { }, 190 }, 191 }; 192 193 static const TypeInfo multi_4x_serial_pci_info = { 194 .name = "pci-serial-4x", 195 .parent = TYPE_PCI_DEVICE, 196 .instance_size = sizeof(PCIMultiSerialState), 197 .class_init = multi_4x_serial_pci_class_initfn, 198 .interfaces = (InterfaceInfo[]) { 199 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 200 { }, 201 }, 202 }; 203 204 static void multi_serial_pci_register_types(void) 205 { 206 type_register_static(&multi_2x_serial_pci_info); 207 type_register_static(&multi_4x_serial_pci_info); 208 } 209 210 type_init(multi_serial_pci_register_types) 211