1 /* 2 * QEMU 16550A multi UART emulation 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Copyright (c) 2003-2004 Fabrice Bellard 7 * Copyright (c) 2008 Citrix Systems, Inc. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 /* see docs/specs/pci-serial.txt */ 29 30 #include "qemu/osdep.h" 31 #include "qapi/error.h" 32 #include "hw/char/serial.h" 33 #include "hw/irq.h" 34 #include "hw/pci/pci.h" 35 36 #define PCI_SERIAL_MAX_PORTS 4 37 38 typedef struct PCIMultiSerialState { 39 PCIDevice dev; 40 MemoryRegion iobar; 41 uint32_t ports; 42 char *name[PCI_SERIAL_MAX_PORTS]; 43 SerialState state[PCI_SERIAL_MAX_PORTS]; 44 uint32_t level[PCI_SERIAL_MAX_PORTS]; 45 qemu_irq *irqs; 46 uint8_t prog_if; 47 } PCIMultiSerialState; 48 49 static void multi_serial_pci_exit(PCIDevice *dev) 50 { 51 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 52 SerialState *s; 53 int i; 54 55 for (i = 0; i < pci->ports; i++) { 56 s = pci->state + i; 57 serial_exit_core(s); 58 memory_region_del_subregion(&pci->iobar, &s->io); 59 g_free(pci->name[i]); 60 } 61 qemu_free_irqs(pci->irqs, pci->ports); 62 } 63 64 static void multi_serial_irq_mux(void *opaque, int n, int level) 65 { 66 PCIMultiSerialState *pci = opaque; 67 int i, pending = 0; 68 69 pci->level[n] = level; 70 for (i = 0; i < pci->ports; i++) { 71 if (pci->level[i]) { 72 pending = 1; 73 } 74 } 75 pci_set_irq(&pci->dev, pending); 76 } 77 78 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) 79 { 80 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 81 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 82 SerialState *s; 83 Error *err = NULL; 84 int i, nr_ports = 0; 85 86 switch (pc->device_id) { 87 case 0x0003: 88 nr_ports = 2; 89 break; 90 case 0x0004: 91 nr_ports = 4; 92 break; 93 } 94 assert(nr_ports > 0); 95 assert(nr_ports <= PCI_SERIAL_MAX_PORTS); 96 97 pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; 98 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; 99 memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports); 100 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); 101 pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, 102 nr_ports); 103 104 for (i = 0; i < nr_ports; i++) { 105 s = pci->state + i; 106 s->baudbase = 115200; 107 serial_realize_core(s, &err); 108 if (err != NULL) { 109 error_propagate(errp, err); 110 multi_serial_pci_exit(dev); 111 return; 112 } 113 s->irq = pci->irqs[i]; 114 pci->name[i] = g_strdup_printf("uart #%d", i + 1); 115 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, 116 pci->name[i], 8); 117 memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); 118 pci->ports++; 119 } 120 } 121 122 static const VMStateDescription vmstate_pci_multi_serial = { 123 .name = "pci-serial-multi", 124 .version_id = 1, 125 .minimum_version_id = 1, 126 .fields = (VMStateField[]) { 127 VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), 128 VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 129 0, vmstate_serial, SerialState), 130 VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), 131 VMSTATE_END_OF_LIST() 132 } 133 }; 134 135 static Property multi_2x_serial_pci_properties[] = { 136 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 137 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 138 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 139 DEFINE_PROP_END_OF_LIST(), 140 }; 141 142 static Property multi_4x_serial_pci_properties[] = { 143 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 144 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 145 DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr), 146 DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr), 147 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 148 DEFINE_PROP_END_OF_LIST(), 149 }; 150 151 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) 152 { 153 DeviceClass *dc = DEVICE_CLASS(klass); 154 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 155 pc->realize = multi_serial_pci_realize; 156 pc->exit = multi_serial_pci_exit; 157 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 158 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2; 159 pc->revision = 1; 160 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 161 dc->vmsd = &vmstate_pci_multi_serial; 162 dc->props = multi_2x_serial_pci_properties; 163 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 164 } 165 166 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) 167 { 168 DeviceClass *dc = DEVICE_CLASS(klass); 169 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 170 pc->realize = multi_serial_pci_realize; 171 pc->exit = multi_serial_pci_exit; 172 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 173 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4; 174 pc->revision = 1; 175 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 176 dc->vmsd = &vmstate_pci_multi_serial; 177 dc->props = multi_4x_serial_pci_properties; 178 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 179 } 180 181 static const TypeInfo multi_2x_serial_pci_info = { 182 .name = "pci-serial-2x", 183 .parent = TYPE_PCI_DEVICE, 184 .instance_size = sizeof(PCIMultiSerialState), 185 .class_init = multi_2x_serial_pci_class_initfn, 186 .interfaces = (InterfaceInfo[]) { 187 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 188 { }, 189 }, 190 }; 191 192 static const TypeInfo multi_4x_serial_pci_info = { 193 .name = "pci-serial-4x", 194 .parent = TYPE_PCI_DEVICE, 195 .instance_size = sizeof(PCIMultiSerialState), 196 .class_init = multi_4x_serial_pci_class_initfn, 197 .interfaces = (InterfaceInfo[]) { 198 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 199 { }, 200 }, 201 }; 202 203 static void multi_serial_pci_register_types(void) 204 { 205 type_register_static(&multi_2x_serial_pci_info); 206 type_register_static(&multi_4x_serial_pci_info); 207 } 208 209 type_init(multi_serial_pci_register_types) 210