1 /*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/char/serial-mm.h"
28 #include "exec/cpu-common.h"
29 #include "migration/vmstate.h"
30 #include "qapi/error.h"
31 #include "hw/qdev-properties.h"
32
serial_mm_read(void * opaque,hwaddr addr,unsigned size)33 static uint64_t serial_mm_read(void *opaque, hwaddr addr, unsigned size)
34 {
35 SerialMM *s = SERIAL_MM(opaque);
36 return serial_io_ops.read(&s->serial, addr >> s->regshift, 1);
37 }
38
serial_mm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)39 static void serial_mm_write(void *opaque, hwaddr addr,
40 uint64_t value, unsigned size)
41 {
42 SerialMM *s = SERIAL_MM(opaque);
43 value &= 255;
44 serial_io_ops.write(&s->serial, addr >> s->regshift, value, 1);
45 }
46
47 static const MemoryRegionOps serial_mm_ops[3] = {
48 [DEVICE_NATIVE_ENDIAN] = {
49 .read = serial_mm_read,
50 .write = serial_mm_write,
51 .endianness = DEVICE_NATIVE_ENDIAN,
52 .valid.max_access_size = 8,
53 .impl.max_access_size = 8,
54 },
55 [DEVICE_LITTLE_ENDIAN] = {
56 .read = serial_mm_read,
57 .write = serial_mm_write,
58 .endianness = DEVICE_LITTLE_ENDIAN,
59 .valid.max_access_size = 8,
60 .impl.max_access_size = 8,
61 },
62 [DEVICE_BIG_ENDIAN] = {
63 .read = serial_mm_read,
64 .write = serial_mm_write,
65 .endianness = DEVICE_BIG_ENDIAN,
66 .valid.max_access_size = 8,
67 .impl.max_access_size = 8,
68 },
69 };
70
serial_mm_realize(DeviceState * dev,Error ** errp)71 static void serial_mm_realize(DeviceState *dev, Error **errp)
72 {
73 SerialMM *smm = SERIAL_MM(dev);
74 SerialState *s = &smm->serial;
75
76 if (!qdev_realize(DEVICE(s), NULL, errp)) {
77 return;
78 }
79
80 memory_region_init_io(&s->io, OBJECT(dev),
81 &serial_mm_ops[smm->endianness], smm, "serial",
82 8 << smm->regshift);
83 sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io);
84 sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq);
85 }
86
87 static const VMStateDescription vmstate_serial_mm = {
88 .name = "serial",
89 .version_id = 3,
90 .minimum_version_id = 2,
91 .fields = (const VMStateField[]) {
92 VMSTATE_STRUCT(serial, SerialMM, 0, vmstate_serial, SerialState),
93 VMSTATE_END_OF_LIST()
94 }
95 };
96
serial_mm_init(MemoryRegion * address_space,hwaddr base,int regshift,qemu_irq irq,int baudbase,Chardev * chr,enum device_endian end)97 SerialMM *serial_mm_init(MemoryRegion *address_space,
98 hwaddr base, int regshift,
99 qemu_irq irq, int baudbase,
100 Chardev *chr, enum device_endian end)
101 {
102 SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM));
103 MemoryRegion *mr;
104
105 qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift);
106 qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase);
107 qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
108 qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
109 qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
110 sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal);
111
112 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
113 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
114 memory_region_add_subregion(address_space, base, mr);
115
116 return smm;
117 }
118
serial_mm_instance_init(Object * o)119 static void serial_mm_instance_init(Object *o)
120 {
121 SerialMM *smm = SERIAL_MM(o);
122
123 object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL);
124
125 qdev_alias_all_properties(DEVICE(&smm->serial), o);
126 }
127
128 static Property serial_mm_properties[] = {
129 /*
130 * Set the spacing between adjacent memory-mapped UART registers.
131 * Each register will be at (1 << regshift) bytes after the previous one.
132 */
133 DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0),
134 DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN),
135 DEFINE_PROP_END_OF_LIST(),
136 };
137
serial_mm_class_init(ObjectClass * oc,void * data)138 static void serial_mm_class_init(ObjectClass *oc, void *data)
139 {
140 DeviceClass *dc = DEVICE_CLASS(oc);
141
142 device_class_set_props(dc, serial_mm_properties);
143 dc->realize = serial_mm_realize;
144 dc->vmsd = &vmstate_serial_mm;
145 }
146
147 static const TypeInfo types[] = {
148 {
149 .name = TYPE_SERIAL_MM,
150 .parent = TYPE_SYS_BUS_DEVICE,
151 .class_init = serial_mm_class_init,
152 .instance_init = serial_mm_instance_init,
153 .instance_size = sizeof(SerialMM),
154 },
155 };
156
157 DEFINE_TYPES(types)
158