1 /* 2 * Arm PrimeCell PL011 UART 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* 11 * QEMU interface: 12 * + sysbus MMIO region 0: device registers 13 * + sysbus IRQ 0: UARTINTR (combined interrupt line) 14 * + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line) 15 * + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line) 16 * + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line) 17 * + sysbus IRQ 4: UARTMSINTR (momem status interrupt line) 18 * + sysbus IRQ 5: UARTEINTR (error interrupt line) 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/char/pl011.h" 24 #include "hw/irq.h" 25 #include "hw/sysbus.h" 26 #include "hw/qdev-clock.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/qdev-properties-system.h" 29 #include "migration/vmstate.h" 30 #include "chardev/char-fe.h" 31 #include "chardev/char-serial.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "trace.h" 35 36 DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) 37 { 38 DeviceState *dev; 39 SysBusDevice *s; 40 41 dev = qdev_new("pl011"); 42 s = SYS_BUS_DEVICE(dev); 43 qdev_prop_set_chr(dev, "chardev", chr); 44 sysbus_realize_and_unref(s, &error_fatal); 45 sysbus_mmio_map(s, 0, addr); 46 sysbus_connect_irq(s, 0, irq); 47 48 return dev; 49 } 50 51 /* Flag Register, UARTFR */ 52 #define PL011_FLAG_RI 0x100 53 #define PL011_FLAG_TXFE 0x80 54 #define PL011_FLAG_RXFF 0x40 55 #define PL011_FLAG_TXFF 0x20 56 #define PL011_FLAG_RXFE 0x10 57 #define PL011_FLAG_DCD 0x04 58 #define PL011_FLAG_DSR 0x02 59 #define PL011_FLAG_CTS 0x01 60 61 /* Data Register, UARTDR */ 62 #define DR_BE (1 << 10) 63 64 /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ 65 #define INT_OE (1 << 10) 66 #define INT_BE (1 << 9) 67 #define INT_PE (1 << 8) 68 #define INT_FE (1 << 7) 69 #define INT_RT (1 << 6) 70 #define INT_TX (1 << 5) 71 #define INT_RX (1 << 4) 72 #define INT_DSR (1 << 3) 73 #define INT_DCD (1 << 2) 74 #define INT_CTS (1 << 1) 75 #define INT_RI (1 << 0) 76 #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) 77 #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) 78 79 /* Line Control Register, UARTLCR_H */ 80 #define LCR_FEN (1 << 4) 81 #define LCR_BRK (1 << 0) 82 83 /* Control Register, UARTCR */ 84 #define CR_OUT2 (1 << 13) 85 #define CR_OUT1 (1 << 12) 86 #define CR_RTS (1 << 11) 87 #define CR_DTR (1 << 10) 88 #define CR_RXE (1 << 9) 89 #define CR_TXE (1 << 8) 90 #define CR_LBE (1 << 7) 91 #define CR_UARTEN (1 << 0) 92 93 /* Integer Baud Rate Divider, UARTIBRD */ 94 #define IBRD_MASK 0xffff 95 96 /* Fractional Baud Rate Divider, UARTFBRD */ 97 #define FBRD_MASK 0x3f 98 99 static const unsigned char pl011_id_arm[8] = 100 { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 101 static const unsigned char pl011_id_luminary[8] = 102 { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 103 104 static const char *pl011_regname(hwaddr offset) 105 { 106 static const char *const rname[] = { 107 [0] = "DR", [1] = "RSR", [6] = "FR", [8] = "ILPR", [9] = "IBRD", 108 [10] = "FBRD", [11] = "LCRH", [12] = "CR", [13] = "IFLS", [14] = "IMSC", 109 [15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR", 110 }; 111 unsigned idx = offset >> 2; 112 113 if (idx < ARRAY_SIZE(rname) && rname[idx]) { 114 return rname[idx]; 115 } 116 if (idx >= 0x3f8 && idx <= 0x400) { 117 return "ID"; 118 } 119 return "UNKN"; 120 } 121 122 /* Which bits in the interrupt status matter for each outbound IRQ line ? */ 123 static const uint32_t irqmask[] = { 124 INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ 125 INT_RX, 126 INT_TX, 127 INT_RT, 128 INT_MS, 129 INT_E, 130 }; 131 132 static void pl011_update(PL011State *s) 133 { 134 uint32_t flags; 135 int i; 136 137 flags = s->int_level & s->int_enabled; 138 trace_pl011_irq_state(flags != 0); 139 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 140 qemu_set_irq(s->irq[i], (flags & irqmask[i]) != 0); 141 } 142 } 143 144 static bool pl011_loopback_enabled(PL011State *s) 145 { 146 return !!(s->cr & CR_LBE); 147 } 148 149 static bool pl011_is_fifo_enabled(PL011State *s) 150 { 151 return (s->lcr & LCR_FEN) != 0; 152 } 153 154 static inline unsigned pl011_get_fifo_depth(PL011State *s) 155 { 156 /* Note: FIFO depth is expected to be power-of-2 */ 157 return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; 158 } 159 160 static inline void pl011_reset_rx_fifo(PL011State *s) 161 { 162 s->read_count = 0; 163 s->read_pos = 0; 164 165 /* Reset FIFO flags */ 166 s->flags &= ~PL011_FLAG_RXFF; 167 s->flags |= PL011_FLAG_RXFE; 168 } 169 170 static inline void pl011_reset_tx_fifo(PL011State *s) 171 { 172 /* Reset FIFO flags */ 173 s->flags &= ~PL011_FLAG_TXFF; 174 s->flags |= PL011_FLAG_TXFE; 175 } 176 177 static void pl011_fifo_rx_put(void *opaque, uint32_t value) 178 { 179 PL011State *s = (PL011State *)opaque; 180 int slot; 181 unsigned pipe_depth; 182 183 pipe_depth = pl011_get_fifo_depth(s); 184 slot = (s->read_pos + s->read_count) & (pipe_depth - 1); 185 s->read_fifo[slot] = value; 186 s->read_count++; 187 s->flags &= ~PL011_FLAG_RXFE; 188 trace_pl011_fifo_rx_put(value, s->read_count, pipe_depth); 189 if (s->read_count == pipe_depth) { 190 trace_pl011_fifo_rx_full(); 191 s->flags |= PL011_FLAG_RXFF; 192 } 193 if (s->read_count == s->read_trigger) { 194 s->int_level |= INT_RX; 195 pl011_update(s); 196 } 197 } 198 199 static void pl011_loopback_tx(PL011State *s, uint32_t value) 200 { 201 if (!pl011_loopback_enabled(s)) { 202 return; 203 } 204 205 /* 206 * Caveat: 207 * 208 * In real hardware, TX loopback happens at the serial-bit level 209 * and then reassembled by the RX logics back into bytes and placed 210 * into the RX fifo. That is, loopback happens after TX fifo. 211 * 212 * Because the real hardware TX fifo is time-drained at the frame 213 * rate governed by the configured serial format, some loopback 214 * bytes in TX fifo may still be able to get into the RX fifo 215 * that could be full at times while being drained at software 216 * pace. 217 * 218 * In such scenario, the RX draining pace is the major factor 219 * deciding which loopback bytes get into the RX fifo, unless 220 * hardware flow-control is enabled. 221 * 222 * For simplicity, the above described is not emulated. 223 */ 224 pl011_fifo_rx_put(s, value); 225 } 226 227 static void pl011_write_txdata(PL011State *s, uint8_t data) 228 { 229 if (!(s->cr & CR_UARTEN)) { 230 qemu_log_mask(LOG_GUEST_ERROR, 231 "PL011 data written to disabled UART\n"); 232 } 233 if (!(s->cr & CR_TXE)) { 234 qemu_log_mask(LOG_GUEST_ERROR, 235 "PL011 data written to disabled TX UART\n"); 236 } 237 238 /* 239 * XXX this blocks entire thread. Rewrite to use 240 * qemu_chr_fe_write and background I/O callbacks 241 */ 242 qemu_chr_fe_write_all(&s->chr, &data, 1); 243 pl011_loopback_tx(s, data); 244 s->int_level |= INT_TX; 245 pl011_update(s); 246 } 247 248 static uint32_t pl011_read_rxdata(PL011State *s) 249 { 250 uint32_t c; 251 unsigned fifo_depth = pl011_get_fifo_depth(s); 252 253 s->flags &= ~PL011_FLAG_RXFF; 254 c = s->read_fifo[s->read_pos]; 255 if (s->read_count > 0) { 256 s->read_count--; 257 s->read_pos = (s->read_pos + 1) & (fifo_depth - 1); 258 } 259 if (s->read_count == 0) { 260 s->flags |= PL011_FLAG_RXFE; 261 } 262 if (s->read_count == s->read_trigger - 1) { 263 s->int_level &= ~INT_RX; 264 } 265 trace_pl011_read_fifo(s->read_count, fifo_depth); 266 s->rsr = c >> 8; 267 pl011_update(s); 268 qemu_chr_fe_accept_input(&s->chr); 269 return c; 270 } 271 272 static uint64_t pl011_read(void *opaque, hwaddr offset, 273 unsigned size) 274 { 275 PL011State *s = (PL011State *)opaque; 276 uint64_t r; 277 278 switch (offset >> 2) { 279 case 0: /* UARTDR */ 280 r = pl011_read_rxdata(s); 281 break; 282 case 1: /* UARTRSR */ 283 r = s->rsr; 284 break; 285 case 6: /* UARTFR */ 286 r = s->flags; 287 break; 288 case 8: /* UARTILPR */ 289 r = s->ilpr; 290 break; 291 case 9: /* UARTIBRD */ 292 r = s->ibrd; 293 break; 294 case 10: /* UARTFBRD */ 295 r = s->fbrd; 296 break; 297 case 11: /* UARTLCR_H */ 298 r = s->lcr; 299 break; 300 case 12: /* UARTCR */ 301 r = s->cr; 302 break; 303 case 13: /* UARTIFLS */ 304 r = s->ifl; 305 break; 306 case 14: /* UARTIMSC */ 307 r = s->int_enabled; 308 break; 309 case 15: /* UARTRIS */ 310 r = s->int_level; 311 break; 312 case 16: /* UARTMIS */ 313 r = s->int_level & s->int_enabled; 314 break; 315 case 18: /* UARTDMACR */ 316 r = s->dmacr; 317 break; 318 case 0x3f8 ... 0x400: 319 r = s->id[(offset - 0xfe0) >> 2]; 320 break; 321 default: 322 qemu_log_mask(LOG_GUEST_ERROR, 323 "pl011_read: Bad offset 0x%x\n", (int)offset); 324 r = 0; 325 break; 326 } 327 328 trace_pl011_read(offset, r, pl011_regname(offset)); 329 return r; 330 } 331 332 static void pl011_set_read_trigger(PL011State *s) 333 { 334 #if 0 335 /* The docs say the RX interrupt is triggered when the FIFO exceeds 336 the threshold. However linux only reads the FIFO in response to an 337 interrupt. Triggering the interrupt when the FIFO is non-empty seems 338 to make things work. */ 339 if (s->lcr & LCR_FEN) 340 s->read_trigger = (s->ifl >> 1) & 0x1c; 341 else 342 #endif 343 s->read_trigger = 1; 344 } 345 346 static unsigned int pl011_get_baudrate(const PL011State *s) 347 { 348 uint64_t clk; 349 350 if (s->ibrd == 0) { 351 return 0; 352 } 353 354 clk = clock_get_hz(s->clk); 355 return (clk / ((s->ibrd << 6) + s->fbrd)) << 2; 356 } 357 358 static void pl011_trace_baudrate_change(const PL011State *s) 359 { 360 trace_pl011_baudrate_change(pl011_get_baudrate(s), 361 clock_get_hz(s->clk), 362 s->ibrd, s->fbrd); 363 } 364 365 static void pl011_loopback_mdmctrl(PL011State *s) 366 { 367 uint32_t cr, fr, il; 368 369 if (!pl011_loopback_enabled(s)) { 370 return; 371 } 372 373 /* 374 * Loopback software-driven modem control outputs to modem status inputs: 375 * FR.RI <= CR.Out2 376 * FR.DCD <= CR.Out1 377 * FR.CTS <= CR.RTS 378 * FR.DSR <= CR.DTR 379 * 380 * The loopback happens immediately even if this call is triggered 381 * by setting only CR.LBE. 382 * 383 * CTS/RTS updates due to enabled hardware flow controls are not 384 * dealt with here. 385 */ 386 cr = s->cr; 387 fr = s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | 388 PL011_FLAG_DSR | PL011_FLAG_CTS); 389 fr |= (cr & CR_OUT2) ? PL011_FLAG_RI : 0; 390 fr |= (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; 391 fr |= (cr & CR_RTS) ? PL011_FLAG_CTS : 0; 392 fr |= (cr & CR_DTR) ? PL011_FLAG_DSR : 0; 393 394 /* Change interrupts based on updated FR */ 395 il = s->int_level & ~(INT_DSR | INT_DCD | INT_CTS | INT_RI); 396 il |= (fr & PL011_FLAG_DSR) ? INT_DSR : 0; 397 il |= (fr & PL011_FLAG_DCD) ? INT_DCD : 0; 398 il |= (fr & PL011_FLAG_CTS) ? INT_CTS : 0; 399 il |= (fr & PL011_FLAG_RI) ? INT_RI : 0; 400 401 s->flags = fr; 402 s->int_level = il; 403 pl011_update(s); 404 } 405 406 static void pl011_loopback_break(PL011State *s, int brk_enable) 407 { 408 if (brk_enable) { 409 pl011_loopback_tx(s, DR_BE); 410 } 411 } 412 413 static void pl011_write(void *opaque, hwaddr offset, 414 uint64_t value, unsigned size) 415 { 416 PL011State *s = (PL011State *)opaque; 417 unsigned char ch; 418 419 trace_pl011_write(offset, value, pl011_regname(offset)); 420 421 switch (offset >> 2) { 422 case 0: /* UARTDR */ 423 ch = value; 424 pl011_write_txdata(s, ch); 425 break; 426 case 1: /* UARTRSR/UARTECR */ 427 s->rsr = 0; 428 break; 429 case 6: /* UARTFR */ 430 /* Writes to Flag register are ignored. */ 431 break; 432 case 8: /* UARTILPR */ 433 s->ilpr = value; 434 break; 435 case 9: /* UARTIBRD */ 436 s->ibrd = value & IBRD_MASK; 437 pl011_trace_baudrate_change(s); 438 break; 439 case 10: /* UARTFBRD */ 440 s->fbrd = value & FBRD_MASK; 441 pl011_trace_baudrate_change(s); 442 break; 443 case 11: /* UARTLCR_H */ 444 /* Reset the FIFO state on FIFO enable or disable */ 445 if ((s->lcr ^ value) & LCR_FEN) { 446 pl011_reset_rx_fifo(s); 447 pl011_reset_tx_fifo(s); 448 } 449 if ((s->lcr ^ value) & LCR_BRK) { 450 int break_enable = value & LCR_BRK; 451 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 452 &break_enable); 453 pl011_loopback_break(s, break_enable); 454 } 455 s->lcr = value; 456 pl011_set_read_trigger(s); 457 break; 458 case 12: /* UARTCR */ 459 /* ??? Need to implement the enable bit. */ 460 s->cr = value; 461 pl011_loopback_mdmctrl(s); 462 break; 463 case 13: /* UARTIFS */ 464 s->ifl = value; 465 pl011_set_read_trigger(s); 466 break; 467 case 14: /* UARTIMSC */ 468 s->int_enabled = value; 469 pl011_update(s); 470 break; 471 case 17: /* UARTICR */ 472 s->int_level &= ~value; 473 pl011_update(s); 474 break; 475 case 18: /* UARTDMACR */ 476 s->dmacr = value; 477 if (value & 3) { 478 qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n"); 479 } 480 break; 481 default: 482 qemu_log_mask(LOG_GUEST_ERROR, 483 "pl011_write: Bad offset 0x%x\n", (int)offset); 484 } 485 } 486 487 static int pl011_can_receive(void *opaque) 488 { 489 PL011State *s = (PL011State *)opaque; 490 unsigned fifo_depth = pl011_get_fifo_depth(s); 491 unsigned fifo_available = fifo_depth - s->read_count; 492 int r = fifo_available ? 1 : 0; 493 494 if (!(s->cr & CR_UARTEN)) { 495 qemu_log_mask(LOG_GUEST_ERROR, 496 "PL011 receiving data on disabled UART\n"); 497 } 498 if (!(s->cr & CR_RXE)) { 499 qemu_log_mask(LOG_GUEST_ERROR, 500 "PL011 receiving data on disabled RX UART\n"); 501 } 502 trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available); 503 return r; 504 } 505 506 static void pl011_receive(void *opaque, const uint8_t *buf, int size) 507 { 508 trace_pl011_receive(size); 509 /* 510 * In loopback mode, the RX input signal is internally disconnected 511 * from the entire receiving logics; thus, all inputs are ignored, 512 * and BREAK detection on RX input signal is also not performed. 513 */ 514 if (pl011_loopback_enabled(opaque)) { 515 return; 516 } 517 518 pl011_fifo_rx_put(opaque, *buf); 519 } 520 521 static void pl011_event(void *opaque, QEMUChrEvent event) 522 { 523 if (event == CHR_EVENT_BREAK && !pl011_loopback_enabled(opaque)) { 524 pl011_fifo_rx_put(opaque, DR_BE); 525 } 526 } 527 528 static void pl011_clock_update(void *opaque, ClockEvent event) 529 { 530 PL011State *s = PL011(opaque); 531 532 pl011_trace_baudrate_change(s); 533 } 534 535 static const MemoryRegionOps pl011_ops = { 536 .read = pl011_read, 537 .write = pl011_write, 538 .endianness = DEVICE_NATIVE_ENDIAN, 539 .impl.min_access_size = 4, 540 .impl.max_access_size = 4, 541 }; 542 543 static bool pl011_clock_needed(void *opaque) 544 { 545 PL011State *s = PL011(opaque); 546 547 return s->migrate_clk; 548 } 549 550 static const VMStateDescription vmstate_pl011_clock = { 551 .name = "pl011/clock", 552 .version_id = 1, 553 .minimum_version_id = 1, 554 .needed = pl011_clock_needed, 555 .fields = (const VMStateField[]) { 556 VMSTATE_CLOCK(clk, PL011State), 557 VMSTATE_END_OF_LIST() 558 } 559 }; 560 561 static int pl011_post_load(void *opaque, int version_id) 562 { 563 PL011State* s = opaque; 564 565 /* Sanity-check input state */ 566 if (s->read_pos >= ARRAY_SIZE(s->read_fifo) || 567 s->read_count > ARRAY_SIZE(s->read_fifo)) { 568 return -1; 569 } 570 571 if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) { 572 /* 573 * Older versions of PL011 didn't ensure that the single 574 * character in the FIFO in FIFO-disabled mode is in 575 * element 0 of the array; convert to follow the current 576 * code's assumptions. 577 */ 578 s->read_fifo[0] = s->read_fifo[s->read_pos]; 579 s->read_pos = 0; 580 } 581 582 s->ibrd &= IBRD_MASK; 583 s->fbrd &= FBRD_MASK; 584 585 return 0; 586 } 587 588 static const VMStateDescription vmstate_pl011 = { 589 .name = "pl011", 590 .version_id = 2, 591 .minimum_version_id = 2, 592 .post_load = pl011_post_load, 593 .fields = (const VMStateField[]) { 594 VMSTATE_UNUSED(sizeof(uint32_t)), 595 VMSTATE_UINT32(flags, PL011State), 596 VMSTATE_UINT32(lcr, PL011State), 597 VMSTATE_UINT32(rsr, PL011State), 598 VMSTATE_UINT32(cr, PL011State), 599 VMSTATE_UINT32(dmacr, PL011State), 600 VMSTATE_UINT32(int_enabled, PL011State), 601 VMSTATE_UINT32(int_level, PL011State), 602 VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH), 603 VMSTATE_UINT32(ilpr, PL011State), 604 VMSTATE_UINT32(ibrd, PL011State), 605 VMSTATE_UINT32(fbrd, PL011State), 606 VMSTATE_UINT32(ifl, PL011State), 607 VMSTATE_INT32(read_pos, PL011State), 608 VMSTATE_INT32(read_count, PL011State), 609 VMSTATE_INT32(read_trigger, PL011State), 610 VMSTATE_END_OF_LIST() 611 }, 612 .subsections = (const VMStateDescription * const []) { 613 &vmstate_pl011_clock, 614 NULL 615 } 616 }; 617 618 static const Property pl011_properties[] = { 619 DEFINE_PROP_CHR("chardev", PL011State, chr), 620 DEFINE_PROP_BOOL("migrate-clk", PL011State, migrate_clk, true), 621 }; 622 623 static void pl011_init(Object *obj) 624 { 625 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 626 PL011State *s = PL011(obj); 627 int i; 628 629 memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000); 630 sysbus_init_mmio(sbd, &s->iomem); 631 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 632 sysbus_init_irq(sbd, &s->irq[i]); 633 } 634 635 s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s, 636 ClockUpdate); 637 638 s->id = pl011_id_arm; 639 } 640 641 static void pl011_realize(DeviceState *dev, Error **errp) 642 { 643 PL011State *s = PL011(dev); 644 645 qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive, 646 pl011_event, NULL, s, NULL, true); 647 } 648 649 static void pl011_reset(DeviceState *dev) 650 { 651 PL011State *s = PL011(dev); 652 653 s->lcr = 0; 654 s->rsr = 0; 655 s->dmacr = 0; 656 s->int_enabled = 0; 657 s->int_level = 0; 658 s->ilpr = 0; 659 s->ibrd = 0; 660 s->fbrd = 0; 661 s->read_trigger = 1; 662 s->ifl = 0x12; 663 s->cr = 0x300; 664 s->flags = 0; 665 pl011_reset_rx_fifo(s); 666 pl011_reset_tx_fifo(s); 667 } 668 669 static void pl011_class_init(ObjectClass *oc, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(oc); 672 673 dc->realize = pl011_realize; 674 device_class_set_legacy_reset(dc, pl011_reset); 675 dc->vmsd = &vmstate_pl011; 676 device_class_set_props(dc, pl011_properties); 677 } 678 679 static const TypeInfo pl011_arm_info = { 680 .name = TYPE_PL011, 681 .parent = TYPE_SYS_BUS_DEVICE, 682 .instance_size = sizeof(PL011State), 683 .instance_init = pl011_init, 684 .class_init = pl011_class_init, 685 }; 686 687 static void pl011_luminary_init(Object *obj) 688 { 689 PL011State *s = PL011(obj); 690 691 s->id = pl011_id_luminary; 692 } 693 694 static const TypeInfo pl011_luminary_info = { 695 .name = TYPE_PL011_LUMINARY, 696 .parent = TYPE_PL011, 697 .instance_init = pl011_luminary_init, 698 }; 699 700 static void pl011_register_types(void) 701 { 702 type_register_static(&pl011_arm_info); 703 type_register_static(&pl011_luminary_info); 704 } 705 706 type_init(pl011_register_types) 707