1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "hw/hw.h" 28 #include "sysemu/char.h" 29 #include "hw/isa/isa.h" 30 #include "hw/i386/pc.h" 31 #include "sysemu/sysemu.h" 32 33 //#define DEBUG_PARALLEL 34 35 #ifdef DEBUG_PARALLEL 36 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 37 #else 38 #define pdebug(fmt, ...) ((void)0) 39 #endif 40 41 #define PARA_REG_DATA 0 42 #define PARA_REG_STS 1 43 #define PARA_REG_CTR 2 44 #define PARA_REG_EPP_ADDR 3 45 #define PARA_REG_EPP_DATA 4 46 47 /* 48 * These are the definitions for the Printer Status Register 49 */ 50 #define PARA_STS_BUSY 0x80 /* Busy complement */ 51 #define PARA_STS_ACK 0x40 /* Acknowledge */ 52 #define PARA_STS_PAPER 0x20 /* Out of paper */ 53 #define PARA_STS_ONLINE 0x10 /* Online */ 54 #define PARA_STS_ERROR 0x08 /* Error complement */ 55 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 56 57 /* 58 * These are the definitions for the Printer Control Register 59 */ 60 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 61 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 62 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 63 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 64 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 65 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 66 67 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 68 69 typedef struct ParallelState { 70 MemoryRegion iomem; 71 uint8_t dataw; 72 uint8_t datar; 73 uint8_t status; 74 uint8_t control; 75 qemu_irq irq; 76 int irq_pending; 77 CharBackend chr; 78 int hw_driver; 79 int epp_timeout; 80 uint32_t last_read_offset; /* For debugging */ 81 /* Memory-mapped interface */ 82 int it_shift; 83 PortioList portio_list; 84 } ParallelState; 85 86 #define TYPE_ISA_PARALLEL "isa-parallel" 87 #define ISA_PARALLEL(obj) \ 88 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) 89 90 typedef struct ISAParallelState { 91 ISADevice parent_obj; 92 93 uint32_t index; 94 uint32_t iobase; 95 uint32_t isairq; 96 ParallelState state; 97 } ISAParallelState; 98 99 static void parallel_update_irq(ParallelState *s) 100 { 101 if (s->irq_pending) 102 qemu_irq_raise(s->irq); 103 else 104 qemu_irq_lower(s->irq); 105 } 106 107 static void 108 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 109 { 110 ParallelState *s = opaque; 111 112 pdebug("write addr=0x%02x val=0x%02x\n", addr, val); 113 114 addr &= 7; 115 switch(addr) { 116 case PARA_REG_DATA: 117 s->dataw = val; 118 parallel_update_irq(s); 119 break; 120 case PARA_REG_CTR: 121 val |= 0xc0; 122 if ((val & PARA_CTR_INIT) == 0 ) { 123 s->status = PARA_STS_BUSY; 124 s->status |= PARA_STS_ACK; 125 s->status |= PARA_STS_ONLINE; 126 s->status |= PARA_STS_ERROR; 127 } 128 else if (val & PARA_CTR_SELECT) { 129 if (val & PARA_CTR_STROBE) { 130 s->status &= ~PARA_STS_BUSY; 131 if ((s->control & PARA_CTR_STROBE) == 0) 132 /* XXX this blocks entire thread. Rewrite to use 133 * qemu_chr_fe_write and background I/O callbacks */ 134 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); 135 } else { 136 if (s->control & PARA_CTR_INTEN) { 137 s->irq_pending = 1; 138 } 139 } 140 } 141 parallel_update_irq(s); 142 s->control = val; 143 break; 144 } 145 } 146 147 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 148 { 149 ParallelState *s = opaque; 150 uint8_t parm = val; 151 int dir; 152 153 /* Sometimes programs do several writes for timing purposes on old 154 HW. Take care not to waste time on writes that do nothing. */ 155 156 s->last_read_offset = ~0U; 157 158 addr &= 7; 159 switch(addr) { 160 case PARA_REG_DATA: 161 if (s->dataw == val) 162 return; 163 pdebug("wd%02x\n", val); 164 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 165 s->dataw = val; 166 break; 167 case PARA_REG_STS: 168 pdebug("ws%02x\n", val); 169 if (val & PARA_STS_TMOUT) 170 s->epp_timeout = 0; 171 break; 172 case PARA_REG_CTR: 173 val |= 0xc0; 174 if (s->control == val) 175 return; 176 pdebug("wc%02x\n", val); 177 178 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 179 if (val & PARA_CTR_DIR) { 180 dir = 1; 181 } else { 182 dir = 0; 183 } 184 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 185 parm &= ~PARA_CTR_DIR; 186 } 187 188 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 189 s->control = val; 190 break; 191 case PARA_REG_EPP_ADDR: 192 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 193 /* Controls not correct for EPP address cycle, so do nothing */ 194 pdebug("wa%02x s\n", val); 195 else { 196 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 197 if (qemu_chr_fe_ioctl(&s->chr, 198 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 199 s->epp_timeout = 1; 200 pdebug("wa%02x t\n", val); 201 } 202 else 203 pdebug("wa%02x\n", val); 204 } 205 break; 206 case PARA_REG_EPP_DATA: 207 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 208 /* Controls not correct for EPP data cycle, so do nothing */ 209 pdebug("we%02x s\n", val); 210 else { 211 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 212 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 213 s->epp_timeout = 1; 214 pdebug("we%02x t\n", val); 215 } 216 else 217 pdebug("we%02x\n", val); 218 } 219 break; 220 } 221 } 222 223 static void 224 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 225 { 226 ParallelState *s = opaque; 227 uint16_t eppdata = cpu_to_le16(val); 228 int err; 229 struct ParallelIOArg ioarg = { 230 .buffer = &eppdata, .count = sizeof(eppdata) 231 }; 232 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 233 /* Controls not correct for EPP data cycle, so do nothing */ 234 pdebug("we%04x s\n", val); 235 return; 236 } 237 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 238 if (err) { 239 s->epp_timeout = 1; 240 pdebug("we%04x t\n", val); 241 } 242 else 243 pdebug("we%04x\n", val); 244 } 245 246 static void 247 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 248 { 249 ParallelState *s = opaque; 250 uint32_t eppdata = cpu_to_le32(val); 251 int err; 252 struct ParallelIOArg ioarg = { 253 .buffer = &eppdata, .count = sizeof(eppdata) 254 }; 255 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 256 /* Controls not correct for EPP data cycle, so do nothing */ 257 pdebug("we%08x s\n", val); 258 return; 259 } 260 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 261 if (err) { 262 s->epp_timeout = 1; 263 pdebug("we%08x t\n", val); 264 } 265 else 266 pdebug("we%08x\n", val); 267 } 268 269 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 270 { 271 ParallelState *s = opaque; 272 uint32_t ret = 0xff; 273 274 addr &= 7; 275 switch(addr) { 276 case PARA_REG_DATA: 277 if (s->control & PARA_CTR_DIR) 278 ret = s->datar; 279 else 280 ret = s->dataw; 281 break; 282 case PARA_REG_STS: 283 ret = s->status; 284 s->irq_pending = 0; 285 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 286 /* XXX Fixme: wait 5 microseconds */ 287 if (s->status & PARA_STS_ACK) 288 s->status &= ~PARA_STS_ACK; 289 else { 290 /* XXX Fixme: wait 5 microseconds */ 291 s->status |= PARA_STS_ACK; 292 s->status |= PARA_STS_BUSY; 293 } 294 } 295 parallel_update_irq(s); 296 break; 297 case PARA_REG_CTR: 298 ret = s->control; 299 break; 300 } 301 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); 302 return ret; 303 } 304 305 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 306 { 307 ParallelState *s = opaque; 308 uint8_t ret = 0xff; 309 addr &= 7; 310 switch(addr) { 311 case PARA_REG_DATA: 312 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 313 if (s->last_read_offset != addr || s->datar != ret) 314 pdebug("rd%02x\n", ret); 315 s->datar = ret; 316 break; 317 case PARA_REG_STS: 318 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 319 ret &= ~PARA_STS_TMOUT; 320 if (s->epp_timeout) 321 ret |= PARA_STS_TMOUT; 322 if (s->last_read_offset != addr || s->status != ret) 323 pdebug("rs%02x\n", ret); 324 s->status = ret; 325 break; 326 case PARA_REG_CTR: 327 /* s->control has some bits fixed to 1. It is zero only when 328 it has not been yet written to. */ 329 if (s->control == 0) { 330 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 331 if (s->last_read_offset != addr) 332 pdebug("rc%02x\n", ret); 333 s->control = ret; 334 } 335 else { 336 ret = s->control; 337 if (s->last_read_offset != addr) 338 pdebug("rc%02x\n", ret); 339 } 340 break; 341 case PARA_REG_EPP_ADDR: 342 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 343 (PARA_CTR_DIR | PARA_CTR_INIT)) 344 /* Controls not correct for EPP addr cycle, so do nothing */ 345 pdebug("ra%02x s\n", ret); 346 else { 347 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 348 if (qemu_chr_fe_ioctl(&s->chr, 349 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 350 s->epp_timeout = 1; 351 pdebug("ra%02x t\n", ret); 352 } 353 else 354 pdebug("ra%02x\n", ret); 355 } 356 break; 357 case PARA_REG_EPP_DATA: 358 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 359 (PARA_CTR_DIR | PARA_CTR_INIT)) 360 /* Controls not correct for EPP data cycle, so do nothing */ 361 pdebug("re%02x s\n", ret); 362 else { 363 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 364 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 365 s->epp_timeout = 1; 366 pdebug("re%02x t\n", ret); 367 } 368 else 369 pdebug("re%02x\n", ret); 370 } 371 break; 372 } 373 s->last_read_offset = addr; 374 return ret; 375 } 376 377 static uint32_t 378 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 379 { 380 ParallelState *s = opaque; 381 uint32_t ret; 382 uint16_t eppdata = ~0; 383 int err; 384 struct ParallelIOArg ioarg = { 385 .buffer = &eppdata, .count = sizeof(eppdata) 386 }; 387 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 388 /* Controls not correct for EPP data cycle, so do nothing */ 389 pdebug("re%04x s\n", eppdata); 390 return eppdata; 391 } 392 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 393 ret = le16_to_cpu(eppdata); 394 395 if (err) { 396 s->epp_timeout = 1; 397 pdebug("re%04x t\n", ret); 398 } 399 else 400 pdebug("re%04x\n", ret); 401 return ret; 402 } 403 404 static uint32_t 405 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 406 { 407 ParallelState *s = opaque; 408 uint32_t ret; 409 uint32_t eppdata = ~0U; 410 int err; 411 struct ParallelIOArg ioarg = { 412 .buffer = &eppdata, .count = sizeof(eppdata) 413 }; 414 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 415 /* Controls not correct for EPP data cycle, so do nothing */ 416 pdebug("re%08x s\n", eppdata); 417 return eppdata; 418 } 419 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 420 ret = le32_to_cpu(eppdata); 421 422 if (err) { 423 s->epp_timeout = 1; 424 pdebug("re%08x t\n", ret); 425 } 426 else 427 pdebug("re%08x\n", ret); 428 return ret; 429 } 430 431 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 432 { 433 pdebug("wecp%d=%02x\n", addr & 7, val); 434 } 435 436 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 437 { 438 uint8_t ret = 0xff; 439 440 pdebug("recp%d:%02x\n", addr & 7, ret); 441 return ret; 442 } 443 444 static void parallel_reset(void *opaque) 445 { 446 ParallelState *s = opaque; 447 448 s->datar = ~0; 449 s->dataw = ~0; 450 s->status = PARA_STS_BUSY; 451 s->status |= PARA_STS_ACK; 452 s->status |= PARA_STS_ONLINE; 453 s->status |= PARA_STS_ERROR; 454 s->status |= PARA_STS_TMOUT; 455 s->control = PARA_CTR_SELECT; 456 s->control |= PARA_CTR_INIT; 457 s->control |= 0xc0; 458 s->irq_pending = 0; 459 s->hw_driver = 0; 460 s->epp_timeout = 0; 461 s->last_read_offset = ~0U; 462 } 463 464 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 465 466 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 467 { 0, 8, 1, 468 .read = parallel_ioport_read_hw, 469 .write = parallel_ioport_write_hw }, 470 { 4, 1, 2, 471 .read = parallel_ioport_eppdata_read_hw2, 472 .write = parallel_ioport_eppdata_write_hw2 }, 473 { 4, 1, 4, 474 .read = parallel_ioport_eppdata_read_hw4, 475 .write = parallel_ioport_eppdata_write_hw4 }, 476 { 0x400, 8, 1, 477 .read = parallel_ioport_ecp_read, 478 .write = parallel_ioport_ecp_write }, 479 PORTIO_END_OF_LIST(), 480 }; 481 482 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 483 { 0, 8, 1, 484 .read = parallel_ioport_read_sw, 485 .write = parallel_ioport_write_sw }, 486 PORTIO_END_OF_LIST(), 487 }; 488 489 490 static const VMStateDescription vmstate_parallel_isa = { 491 .name = "parallel_isa", 492 .version_id = 1, 493 .minimum_version_id = 1, 494 .fields = (VMStateField[]) { 495 VMSTATE_UINT8(state.dataw, ISAParallelState), 496 VMSTATE_UINT8(state.datar, ISAParallelState), 497 VMSTATE_UINT8(state.status, ISAParallelState), 498 VMSTATE_UINT8(state.control, ISAParallelState), 499 VMSTATE_INT32(state.irq_pending, ISAParallelState), 500 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 501 VMSTATE_END_OF_LIST() 502 } 503 }; 504 505 506 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 507 { 508 static int index; 509 ISADevice *isadev = ISA_DEVICE(dev); 510 ISAParallelState *isa = ISA_PARALLEL(dev); 511 ParallelState *s = &isa->state; 512 int base; 513 uint8_t dummy; 514 515 if (!qemu_chr_fe_get_driver(&s->chr)) { 516 error_setg(errp, "Can't create parallel device, empty char device"); 517 return; 518 } 519 520 if (isa->index == -1) { 521 isa->index = index; 522 } 523 if (isa->index >= MAX_PARALLEL_PORTS) { 524 error_setg(errp, "Max. supported number of parallel ports is %d.", 525 MAX_PARALLEL_PORTS); 526 return; 527 } 528 if (isa->iobase == -1) { 529 isa->iobase = isa_parallel_io[isa->index]; 530 } 531 index++; 532 533 base = isa->iobase; 534 isa_init_irq(isadev, &s->irq, isa->isairq); 535 qemu_register_reset(parallel_reset, s); 536 537 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 538 s->hw_driver = 1; 539 s->status = dummy; 540 } 541 542 isa_register_portio_list(isadev, &s->portio_list, base, 543 (s->hw_driver 544 ? &isa_parallel_portio_hw_list[0] 545 : &isa_parallel_portio_sw_list[0]), 546 s, "parallel"); 547 } 548 549 /* Memory mapped interface */ 550 static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) 551 { 552 ParallelState *s = opaque; 553 554 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; 555 } 556 557 static void parallel_mm_writeb (void *opaque, 558 hwaddr addr, uint32_t value) 559 { 560 ParallelState *s = opaque; 561 562 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); 563 } 564 565 static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) 566 { 567 ParallelState *s = opaque; 568 569 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; 570 } 571 572 static void parallel_mm_writew (void *opaque, 573 hwaddr addr, uint32_t value) 574 { 575 ParallelState *s = opaque; 576 577 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); 578 } 579 580 static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) 581 { 582 ParallelState *s = opaque; 583 584 return parallel_ioport_read_sw(s, addr >> s->it_shift); 585 } 586 587 static void parallel_mm_writel (void *opaque, 588 hwaddr addr, uint32_t value) 589 { 590 ParallelState *s = opaque; 591 592 parallel_ioport_write_sw(s, addr >> s->it_shift, value); 593 } 594 595 static const MemoryRegionOps parallel_mm_ops = { 596 .old_mmio = { 597 .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, 598 .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, 599 }, 600 .endianness = DEVICE_NATIVE_ENDIAN, 601 }; 602 603 /* If fd is zero, it means that the parallel device uses the console */ 604 bool parallel_mm_init(MemoryRegion *address_space, 605 hwaddr base, int it_shift, qemu_irq irq, 606 CharDriverState *chr) 607 { 608 ParallelState *s; 609 610 s = g_malloc0(sizeof(ParallelState)); 611 s->irq = irq; 612 qemu_chr_fe_init(&s->chr, chr, &error_abort); 613 s->it_shift = it_shift; 614 qemu_register_reset(parallel_reset, s); 615 616 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 617 "parallel", 8 << it_shift); 618 memory_region_add_subregion(address_space, base, &s->iomem); 619 return true; 620 } 621 622 static Property parallel_isa_properties[] = { 623 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 624 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 625 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 626 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 627 DEFINE_PROP_END_OF_LIST(), 628 }; 629 630 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 631 { 632 DeviceClass *dc = DEVICE_CLASS(klass); 633 634 dc->realize = parallel_isa_realizefn; 635 dc->vmsd = &vmstate_parallel_isa; 636 dc->props = parallel_isa_properties; 637 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 638 } 639 640 static const TypeInfo parallel_isa_info = { 641 .name = TYPE_ISA_PARALLEL, 642 .parent = TYPE_ISA_DEVICE, 643 .instance_size = sizeof(ISAParallelState), 644 .class_init = parallel_isa_class_initfn, 645 }; 646 647 static void parallel_register_types(void) 648 { 649 type_register_static(¶llel_isa_info); 650 } 651 652 type_init(parallel_register_types) 653