1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "hw/hw.h" 28 #include "sysemu/char.h" 29 #include "hw/isa/isa.h" 30 #include "hw/i386/pc.h" 31 #include "sysemu/sysemu.h" 32 33 //#define DEBUG_PARALLEL 34 35 #ifdef DEBUG_PARALLEL 36 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 37 #else 38 #define pdebug(fmt, ...) ((void)0) 39 #endif 40 41 #define PARA_REG_DATA 0 42 #define PARA_REG_STS 1 43 #define PARA_REG_CTR 2 44 #define PARA_REG_EPP_ADDR 3 45 #define PARA_REG_EPP_DATA 4 46 47 /* 48 * These are the definitions for the Printer Status Register 49 */ 50 #define PARA_STS_BUSY 0x80 /* Busy complement */ 51 #define PARA_STS_ACK 0x40 /* Acknowledge */ 52 #define PARA_STS_PAPER 0x20 /* Out of paper */ 53 #define PARA_STS_ONLINE 0x10 /* Online */ 54 #define PARA_STS_ERROR 0x08 /* Error complement */ 55 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 56 57 /* 58 * These are the definitions for the Printer Control Register 59 */ 60 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 61 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 62 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 63 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 64 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 65 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 66 67 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 68 69 typedef struct ParallelState { 70 MemoryRegion iomem; 71 uint8_t dataw; 72 uint8_t datar; 73 uint8_t status; 74 uint8_t control; 75 qemu_irq irq; 76 int irq_pending; 77 CharDriverState *chr; 78 int hw_driver; 79 int epp_timeout; 80 uint32_t last_read_offset; /* For debugging */ 81 /* Memory-mapped interface */ 82 int it_shift; 83 PortioList portio_list; 84 } ParallelState; 85 86 #define TYPE_ISA_PARALLEL "isa-parallel" 87 #define ISA_PARALLEL(obj) \ 88 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) 89 90 typedef struct ISAParallelState { 91 ISADevice parent_obj; 92 93 uint32_t index; 94 uint32_t iobase; 95 uint32_t isairq; 96 ParallelState state; 97 } ISAParallelState; 98 99 static void parallel_update_irq(ParallelState *s) 100 { 101 if (s->irq_pending) 102 qemu_irq_raise(s->irq); 103 else 104 qemu_irq_lower(s->irq); 105 } 106 107 static void 108 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 109 { 110 ParallelState *s = opaque; 111 112 pdebug("write addr=0x%02x val=0x%02x\n", addr, val); 113 114 addr &= 7; 115 switch(addr) { 116 case PARA_REG_DATA: 117 s->dataw = val; 118 parallel_update_irq(s); 119 break; 120 case PARA_REG_CTR: 121 val |= 0xc0; 122 if ((val & PARA_CTR_INIT) == 0 ) { 123 s->status = PARA_STS_BUSY; 124 s->status |= PARA_STS_ACK; 125 s->status |= PARA_STS_ONLINE; 126 s->status |= PARA_STS_ERROR; 127 } 128 else if (val & PARA_CTR_SELECT) { 129 if (val & PARA_CTR_STROBE) { 130 s->status &= ~PARA_STS_BUSY; 131 if ((s->control & PARA_CTR_STROBE) == 0) 132 /* XXX this blocks entire thread. Rewrite to use 133 * qemu_chr_fe_write and background I/O callbacks */ 134 qemu_chr_fe_write_all(s->chr, &s->dataw, 1); 135 } else { 136 if (s->control & PARA_CTR_INTEN) { 137 s->irq_pending = 1; 138 } 139 } 140 } 141 parallel_update_irq(s); 142 s->control = val; 143 break; 144 } 145 } 146 147 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 148 { 149 ParallelState *s = opaque; 150 uint8_t parm = val; 151 int dir; 152 153 /* Sometimes programs do several writes for timing purposes on old 154 HW. Take care not to waste time on writes that do nothing. */ 155 156 s->last_read_offset = ~0U; 157 158 addr &= 7; 159 switch(addr) { 160 case PARA_REG_DATA: 161 if (s->dataw == val) 162 return; 163 pdebug("wd%02x\n", val); 164 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 165 s->dataw = val; 166 break; 167 case PARA_REG_STS: 168 pdebug("ws%02x\n", val); 169 if (val & PARA_STS_TMOUT) 170 s->epp_timeout = 0; 171 break; 172 case PARA_REG_CTR: 173 val |= 0xc0; 174 if (s->control == val) 175 return; 176 pdebug("wc%02x\n", val); 177 178 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 179 if (val & PARA_CTR_DIR) { 180 dir = 1; 181 } else { 182 dir = 0; 183 } 184 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 185 parm &= ~PARA_CTR_DIR; 186 } 187 188 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 189 s->control = val; 190 break; 191 case PARA_REG_EPP_ADDR: 192 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 193 /* Controls not correct for EPP address cycle, so do nothing */ 194 pdebug("wa%02x s\n", val); 195 else { 196 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 197 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 198 s->epp_timeout = 1; 199 pdebug("wa%02x t\n", val); 200 } 201 else 202 pdebug("wa%02x\n", val); 203 } 204 break; 205 case PARA_REG_EPP_DATA: 206 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 207 /* Controls not correct for EPP data cycle, so do nothing */ 208 pdebug("we%02x s\n", val); 209 else { 210 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 211 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 212 s->epp_timeout = 1; 213 pdebug("we%02x t\n", val); 214 } 215 else 216 pdebug("we%02x\n", val); 217 } 218 break; 219 } 220 } 221 222 static void 223 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 224 { 225 ParallelState *s = opaque; 226 uint16_t eppdata = cpu_to_le16(val); 227 int err; 228 struct ParallelIOArg ioarg = { 229 .buffer = &eppdata, .count = sizeof(eppdata) 230 }; 231 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 232 /* Controls not correct for EPP data cycle, so do nothing */ 233 pdebug("we%04x s\n", val); 234 return; 235 } 236 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 237 if (err) { 238 s->epp_timeout = 1; 239 pdebug("we%04x t\n", val); 240 } 241 else 242 pdebug("we%04x\n", val); 243 } 244 245 static void 246 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 247 { 248 ParallelState *s = opaque; 249 uint32_t eppdata = cpu_to_le32(val); 250 int err; 251 struct ParallelIOArg ioarg = { 252 .buffer = &eppdata, .count = sizeof(eppdata) 253 }; 254 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 255 /* Controls not correct for EPP data cycle, so do nothing */ 256 pdebug("we%08x s\n", val); 257 return; 258 } 259 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 260 if (err) { 261 s->epp_timeout = 1; 262 pdebug("we%08x t\n", val); 263 } 264 else 265 pdebug("we%08x\n", val); 266 } 267 268 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 269 { 270 ParallelState *s = opaque; 271 uint32_t ret = 0xff; 272 273 addr &= 7; 274 switch(addr) { 275 case PARA_REG_DATA: 276 if (s->control & PARA_CTR_DIR) 277 ret = s->datar; 278 else 279 ret = s->dataw; 280 break; 281 case PARA_REG_STS: 282 ret = s->status; 283 s->irq_pending = 0; 284 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 285 /* XXX Fixme: wait 5 microseconds */ 286 if (s->status & PARA_STS_ACK) 287 s->status &= ~PARA_STS_ACK; 288 else { 289 /* XXX Fixme: wait 5 microseconds */ 290 s->status |= PARA_STS_ACK; 291 s->status |= PARA_STS_BUSY; 292 } 293 } 294 parallel_update_irq(s); 295 break; 296 case PARA_REG_CTR: 297 ret = s->control; 298 break; 299 } 300 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); 301 return ret; 302 } 303 304 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 305 { 306 ParallelState *s = opaque; 307 uint8_t ret = 0xff; 308 addr &= 7; 309 switch(addr) { 310 case PARA_REG_DATA: 311 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 312 if (s->last_read_offset != addr || s->datar != ret) 313 pdebug("rd%02x\n", ret); 314 s->datar = ret; 315 break; 316 case PARA_REG_STS: 317 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 318 ret &= ~PARA_STS_TMOUT; 319 if (s->epp_timeout) 320 ret |= PARA_STS_TMOUT; 321 if (s->last_read_offset != addr || s->status != ret) 322 pdebug("rs%02x\n", ret); 323 s->status = ret; 324 break; 325 case PARA_REG_CTR: 326 /* s->control has some bits fixed to 1. It is zero only when 327 it has not been yet written to. */ 328 if (s->control == 0) { 329 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 330 if (s->last_read_offset != addr) 331 pdebug("rc%02x\n", ret); 332 s->control = ret; 333 } 334 else { 335 ret = s->control; 336 if (s->last_read_offset != addr) 337 pdebug("rc%02x\n", ret); 338 } 339 break; 340 case PARA_REG_EPP_ADDR: 341 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 342 /* Controls not correct for EPP addr cycle, so do nothing */ 343 pdebug("ra%02x s\n", ret); 344 else { 345 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 346 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 347 s->epp_timeout = 1; 348 pdebug("ra%02x t\n", ret); 349 } 350 else 351 pdebug("ra%02x\n", ret); 352 } 353 break; 354 case PARA_REG_EPP_DATA: 355 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 356 /* Controls not correct for EPP data cycle, so do nothing */ 357 pdebug("re%02x s\n", ret); 358 else { 359 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 360 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 361 s->epp_timeout = 1; 362 pdebug("re%02x t\n", ret); 363 } 364 else 365 pdebug("re%02x\n", ret); 366 } 367 break; 368 } 369 s->last_read_offset = addr; 370 return ret; 371 } 372 373 static uint32_t 374 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 375 { 376 ParallelState *s = opaque; 377 uint32_t ret; 378 uint16_t eppdata = ~0; 379 int err; 380 struct ParallelIOArg ioarg = { 381 .buffer = &eppdata, .count = sizeof(eppdata) 382 }; 383 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 384 /* Controls not correct for EPP data cycle, so do nothing */ 385 pdebug("re%04x s\n", eppdata); 386 return eppdata; 387 } 388 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 389 ret = le16_to_cpu(eppdata); 390 391 if (err) { 392 s->epp_timeout = 1; 393 pdebug("re%04x t\n", ret); 394 } 395 else 396 pdebug("re%04x\n", ret); 397 return ret; 398 } 399 400 static uint32_t 401 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 402 { 403 ParallelState *s = opaque; 404 uint32_t ret; 405 uint32_t eppdata = ~0U; 406 int err; 407 struct ParallelIOArg ioarg = { 408 .buffer = &eppdata, .count = sizeof(eppdata) 409 }; 410 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 411 /* Controls not correct for EPP data cycle, so do nothing */ 412 pdebug("re%08x s\n", eppdata); 413 return eppdata; 414 } 415 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 416 ret = le32_to_cpu(eppdata); 417 418 if (err) { 419 s->epp_timeout = 1; 420 pdebug("re%08x t\n", ret); 421 } 422 else 423 pdebug("re%08x\n", ret); 424 return ret; 425 } 426 427 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 428 { 429 pdebug("wecp%d=%02x\n", addr & 7, val); 430 } 431 432 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 433 { 434 uint8_t ret = 0xff; 435 436 pdebug("recp%d:%02x\n", addr & 7, ret); 437 return ret; 438 } 439 440 static void parallel_reset(void *opaque) 441 { 442 ParallelState *s = opaque; 443 444 s->datar = ~0; 445 s->dataw = ~0; 446 s->status = PARA_STS_BUSY; 447 s->status |= PARA_STS_ACK; 448 s->status |= PARA_STS_ONLINE; 449 s->status |= PARA_STS_ERROR; 450 s->status |= PARA_STS_TMOUT; 451 s->control = PARA_CTR_SELECT; 452 s->control |= PARA_CTR_INIT; 453 s->control |= 0xc0; 454 s->irq_pending = 0; 455 s->hw_driver = 0; 456 s->epp_timeout = 0; 457 s->last_read_offset = ~0U; 458 } 459 460 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 461 462 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 463 { 0, 8, 1, 464 .read = parallel_ioport_read_hw, 465 .write = parallel_ioport_write_hw }, 466 { 4, 1, 2, 467 .read = parallel_ioport_eppdata_read_hw2, 468 .write = parallel_ioport_eppdata_write_hw2 }, 469 { 4, 1, 4, 470 .read = parallel_ioport_eppdata_read_hw4, 471 .write = parallel_ioport_eppdata_write_hw4 }, 472 { 0x400, 8, 1, 473 .read = parallel_ioport_ecp_read, 474 .write = parallel_ioport_ecp_write }, 475 PORTIO_END_OF_LIST(), 476 }; 477 478 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 479 { 0, 8, 1, 480 .read = parallel_ioport_read_sw, 481 .write = parallel_ioport_write_sw }, 482 PORTIO_END_OF_LIST(), 483 }; 484 485 486 static const VMStateDescription vmstate_parallel_isa = { 487 .name = "parallel_isa", 488 .version_id = 1, 489 .minimum_version_id = 1, 490 .fields = (VMStateField[]) { 491 VMSTATE_UINT8(state.dataw, ISAParallelState), 492 VMSTATE_UINT8(state.datar, ISAParallelState), 493 VMSTATE_UINT8(state.status, ISAParallelState), 494 VMSTATE_UINT8(state.control, ISAParallelState), 495 VMSTATE_INT32(state.irq_pending, ISAParallelState), 496 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 497 VMSTATE_END_OF_LIST() 498 } 499 }; 500 501 502 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 503 { 504 static int index; 505 ISADevice *isadev = ISA_DEVICE(dev); 506 ISAParallelState *isa = ISA_PARALLEL(dev); 507 ParallelState *s = &isa->state; 508 int base; 509 uint8_t dummy; 510 511 if (!s->chr) { 512 error_setg(errp, "Can't create parallel device, empty char device"); 513 return; 514 } 515 516 if (isa->index == -1) { 517 isa->index = index; 518 } 519 if (isa->index >= MAX_PARALLEL_PORTS) { 520 error_setg(errp, "Max. supported number of parallel ports is %d.", 521 MAX_PARALLEL_PORTS); 522 return; 523 } 524 if (isa->iobase == -1) { 525 isa->iobase = isa_parallel_io[isa->index]; 526 } 527 index++; 528 529 base = isa->iobase; 530 isa_init_irq(isadev, &s->irq, isa->isairq); 531 qemu_register_reset(parallel_reset, s); 532 533 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 534 s->hw_driver = 1; 535 s->status = dummy; 536 } 537 538 isa_register_portio_list(isadev, &s->portio_list, base, 539 (s->hw_driver 540 ? &isa_parallel_portio_hw_list[0] 541 : &isa_parallel_portio_sw_list[0]), 542 s, "parallel"); 543 } 544 545 /* Memory mapped interface */ 546 static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) 547 { 548 ParallelState *s = opaque; 549 550 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; 551 } 552 553 static void parallel_mm_writeb (void *opaque, 554 hwaddr addr, uint32_t value) 555 { 556 ParallelState *s = opaque; 557 558 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); 559 } 560 561 static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) 562 { 563 ParallelState *s = opaque; 564 565 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; 566 } 567 568 static void parallel_mm_writew (void *opaque, 569 hwaddr addr, uint32_t value) 570 { 571 ParallelState *s = opaque; 572 573 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); 574 } 575 576 static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) 577 { 578 ParallelState *s = opaque; 579 580 return parallel_ioport_read_sw(s, addr >> s->it_shift); 581 } 582 583 static void parallel_mm_writel (void *opaque, 584 hwaddr addr, uint32_t value) 585 { 586 ParallelState *s = opaque; 587 588 parallel_ioport_write_sw(s, addr >> s->it_shift, value); 589 } 590 591 static const MemoryRegionOps parallel_mm_ops = { 592 .old_mmio = { 593 .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, 594 .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, 595 }, 596 .endianness = DEVICE_NATIVE_ENDIAN, 597 }; 598 599 /* If fd is zero, it means that the parallel device uses the console */ 600 bool parallel_mm_init(MemoryRegion *address_space, 601 hwaddr base, int it_shift, qemu_irq irq, 602 CharDriverState *chr) 603 { 604 ParallelState *s; 605 606 s = g_malloc0(sizeof(ParallelState)); 607 s->irq = irq; 608 s->chr = chr; 609 s->it_shift = it_shift; 610 qemu_register_reset(parallel_reset, s); 611 612 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 613 "parallel", 8 << it_shift); 614 memory_region_add_subregion(address_space, base, &s->iomem); 615 return true; 616 } 617 618 static Property parallel_isa_properties[] = { 619 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 620 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 621 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 622 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 623 DEFINE_PROP_END_OF_LIST(), 624 }; 625 626 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 627 { 628 DeviceClass *dc = DEVICE_CLASS(klass); 629 630 dc->realize = parallel_isa_realizefn; 631 dc->vmsd = &vmstate_parallel_isa; 632 dc->props = parallel_isa_properties; 633 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 634 } 635 636 static const TypeInfo parallel_isa_info = { 637 .name = TYPE_ISA_PARALLEL, 638 .parent = TYPE_ISA_DEVICE, 639 .instance_size = sizeof(ISAParallelState), 640 .class_init = parallel_isa_class_initfn, 641 }; 642 643 static void parallel_register_types(void) 644 { 645 type_register_static(¶llel_isa_info); 646 } 647 648 type_init(parallel_register_types) 649