1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu/module.h" 29 #include "chardev/char-parallel.h" 30 #include "chardev/char-fe.h" 31 #include "hw/irq.h" 32 #include "hw/isa/isa.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "hw/char/parallel.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/sysemu.h" 38 #include "trace.h" 39 40 //#define DEBUG_PARALLEL 41 42 #ifdef DEBUG_PARALLEL 43 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 44 #else 45 #define pdebug(fmt, ...) ((void)0) 46 #endif 47 48 #define PARA_REG_DATA 0 49 #define PARA_REG_STS 1 50 #define PARA_REG_CTR 2 51 #define PARA_REG_EPP_ADDR 3 52 #define PARA_REG_EPP_DATA 4 53 54 /* 55 * These are the definitions for the Printer Status Register 56 */ 57 #define PARA_STS_BUSY 0x80 /* Busy complement */ 58 #define PARA_STS_ACK 0x40 /* Acknowledge */ 59 #define PARA_STS_PAPER 0x20 /* Out of paper */ 60 #define PARA_STS_ONLINE 0x10 /* Online */ 61 #define PARA_STS_ERROR 0x08 /* Error complement */ 62 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 63 64 /* 65 * These are the definitions for the Printer Control Register 66 */ 67 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 68 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 69 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 70 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 71 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 72 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 73 74 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 75 76 typedef struct ParallelState { 77 MemoryRegion iomem; 78 uint8_t dataw; 79 uint8_t datar; 80 uint8_t status; 81 uint8_t control; 82 qemu_irq irq; 83 int irq_pending; 84 CharBackend chr; 85 int hw_driver; 86 int epp_timeout; 87 uint32_t last_read_offset; /* For debugging */ 88 /* Memory-mapped interface */ 89 int it_shift; 90 PortioList portio_list; 91 } ParallelState; 92 93 #define TYPE_ISA_PARALLEL "isa-parallel" 94 #define ISA_PARALLEL(obj) \ 95 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) 96 97 typedef struct ISAParallelState { 98 ISADevice parent_obj; 99 100 uint32_t index; 101 uint32_t iobase; 102 uint32_t isairq; 103 ParallelState state; 104 } ISAParallelState; 105 106 static void parallel_update_irq(ParallelState *s) 107 { 108 if (s->irq_pending) 109 qemu_irq_raise(s->irq); 110 else 111 qemu_irq_lower(s->irq); 112 } 113 114 static void 115 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 116 { 117 ParallelState *s = opaque; 118 119 addr &= 7; 120 trace_parallel_ioport_write("SW", addr, val); 121 switch(addr) { 122 case PARA_REG_DATA: 123 s->dataw = val; 124 parallel_update_irq(s); 125 break; 126 case PARA_REG_CTR: 127 val |= 0xc0; 128 if ((val & PARA_CTR_INIT) == 0 ) { 129 s->status = PARA_STS_BUSY; 130 s->status |= PARA_STS_ACK; 131 s->status |= PARA_STS_ONLINE; 132 s->status |= PARA_STS_ERROR; 133 } 134 else if (val & PARA_CTR_SELECT) { 135 if (val & PARA_CTR_STROBE) { 136 s->status &= ~PARA_STS_BUSY; 137 if ((s->control & PARA_CTR_STROBE) == 0) 138 /* XXX this blocks entire thread. Rewrite to use 139 * qemu_chr_fe_write and background I/O callbacks */ 140 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); 141 } else { 142 if (s->control & PARA_CTR_INTEN) { 143 s->irq_pending = 1; 144 } 145 } 146 } 147 parallel_update_irq(s); 148 s->control = val; 149 break; 150 } 151 } 152 153 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 154 { 155 ParallelState *s = opaque; 156 uint8_t parm = val; 157 int dir; 158 159 /* Sometimes programs do several writes for timing purposes on old 160 HW. Take care not to waste time on writes that do nothing. */ 161 162 s->last_read_offset = ~0U; 163 164 addr &= 7; 165 trace_parallel_ioport_write("HW", addr, val); 166 switch(addr) { 167 case PARA_REG_DATA: 168 if (s->dataw == val) 169 return; 170 pdebug("wd%02x\n", val); 171 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 172 s->dataw = val; 173 break; 174 case PARA_REG_STS: 175 pdebug("ws%02x\n", val); 176 if (val & PARA_STS_TMOUT) 177 s->epp_timeout = 0; 178 break; 179 case PARA_REG_CTR: 180 val |= 0xc0; 181 if (s->control == val) 182 return; 183 pdebug("wc%02x\n", val); 184 185 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 186 if (val & PARA_CTR_DIR) { 187 dir = 1; 188 } else { 189 dir = 0; 190 } 191 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 192 parm &= ~PARA_CTR_DIR; 193 } 194 195 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 196 s->control = val; 197 break; 198 case PARA_REG_EPP_ADDR: 199 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 200 /* Controls not correct for EPP address cycle, so do nothing */ 201 pdebug("wa%02x s\n", val); 202 else { 203 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 204 if (qemu_chr_fe_ioctl(&s->chr, 205 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 206 s->epp_timeout = 1; 207 pdebug("wa%02x t\n", val); 208 } 209 else 210 pdebug("wa%02x\n", val); 211 } 212 break; 213 case PARA_REG_EPP_DATA: 214 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 215 /* Controls not correct for EPP data cycle, so do nothing */ 216 pdebug("we%02x s\n", val); 217 else { 218 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 219 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 220 s->epp_timeout = 1; 221 pdebug("we%02x t\n", val); 222 } 223 else 224 pdebug("we%02x\n", val); 225 } 226 break; 227 } 228 } 229 230 static void 231 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 232 { 233 ParallelState *s = opaque; 234 uint16_t eppdata = cpu_to_le16(val); 235 int err; 236 struct ParallelIOArg ioarg = { 237 .buffer = &eppdata, .count = sizeof(eppdata) 238 }; 239 240 trace_parallel_ioport_write("EPP", addr, val); 241 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 242 /* Controls not correct for EPP data cycle, so do nothing */ 243 pdebug("we%04x s\n", val); 244 return; 245 } 246 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 247 if (err) { 248 s->epp_timeout = 1; 249 pdebug("we%04x t\n", val); 250 } 251 else 252 pdebug("we%04x\n", val); 253 } 254 255 static void 256 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 257 { 258 ParallelState *s = opaque; 259 uint32_t eppdata = cpu_to_le32(val); 260 int err; 261 struct ParallelIOArg ioarg = { 262 .buffer = &eppdata, .count = sizeof(eppdata) 263 }; 264 265 trace_parallel_ioport_write("EPP", addr, val); 266 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 267 /* Controls not correct for EPP data cycle, so do nothing */ 268 pdebug("we%08x s\n", val); 269 return; 270 } 271 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 272 if (err) { 273 s->epp_timeout = 1; 274 pdebug("we%08x t\n", val); 275 } 276 else 277 pdebug("we%08x\n", val); 278 } 279 280 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 281 { 282 ParallelState *s = opaque; 283 uint32_t ret = 0xff; 284 285 addr &= 7; 286 switch(addr) { 287 case PARA_REG_DATA: 288 if (s->control & PARA_CTR_DIR) 289 ret = s->datar; 290 else 291 ret = s->dataw; 292 break; 293 case PARA_REG_STS: 294 ret = s->status; 295 s->irq_pending = 0; 296 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 297 /* XXX Fixme: wait 5 microseconds */ 298 if (s->status & PARA_STS_ACK) 299 s->status &= ~PARA_STS_ACK; 300 else { 301 /* XXX Fixme: wait 5 microseconds */ 302 s->status |= PARA_STS_ACK; 303 s->status |= PARA_STS_BUSY; 304 } 305 } 306 parallel_update_irq(s); 307 break; 308 case PARA_REG_CTR: 309 ret = s->control; 310 break; 311 } 312 trace_parallel_ioport_read("SW", addr, ret); 313 return ret; 314 } 315 316 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 317 { 318 ParallelState *s = opaque; 319 uint8_t ret = 0xff; 320 addr &= 7; 321 switch(addr) { 322 case PARA_REG_DATA: 323 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 324 if (s->last_read_offset != addr || s->datar != ret) 325 pdebug("rd%02x\n", ret); 326 s->datar = ret; 327 break; 328 case PARA_REG_STS: 329 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 330 ret &= ~PARA_STS_TMOUT; 331 if (s->epp_timeout) 332 ret |= PARA_STS_TMOUT; 333 if (s->last_read_offset != addr || s->status != ret) 334 pdebug("rs%02x\n", ret); 335 s->status = ret; 336 break; 337 case PARA_REG_CTR: 338 /* s->control has some bits fixed to 1. It is zero only when 339 it has not been yet written to. */ 340 if (s->control == 0) { 341 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 342 if (s->last_read_offset != addr) 343 pdebug("rc%02x\n", ret); 344 s->control = ret; 345 } 346 else { 347 ret = s->control; 348 if (s->last_read_offset != addr) 349 pdebug("rc%02x\n", ret); 350 } 351 break; 352 case PARA_REG_EPP_ADDR: 353 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 354 (PARA_CTR_DIR | PARA_CTR_INIT)) 355 /* Controls not correct for EPP addr cycle, so do nothing */ 356 pdebug("ra%02x s\n", ret); 357 else { 358 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 359 if (qemu_chr_fe_ioctl(&s->chr, 360 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 361 s->epp_timeout = 1; 362 pdebug("ra%02x t\n", ret); 363 } 364 else 365 pdebug("ra%02x\n", ret); 366 } 367 break; 368 case PARA_REG_EPP_DATA: 369 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 370 (PARA_CTR_DIR | PARA_CTR_INIT)) 371 /* Controls not correct for EPP data cycle, so do nothing */ 372 pdebug("re%02x s\n", ret); 373 else { 374 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 375 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 376 s->epp_timeout = 1; 377 pdebug("re%02x t\n", ret); 378 } 379 else 380 pdebug("re%02x\n", ret); 381 } 382 break; 383 } 384 trace_parallel_ioport_read("HW", addr, ret); 385 s->last_read_offset = addr; 386 return ret; 387 } 388 389 static uint32_t 390 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 391 { 392 ParallelState *s = opaque; 393 uint32_t ret; 394 uint16_t eppdata = ~0; 395 int err; 396 struct ParallelIOArg ioarg = { 397 .buffer = &eppdata, .count = sizeof(eppdata) 398 }; 399 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 400 /* Controls not correct for EPP data cycle, so do nothing */ 401 pdebug("re%04x s\n", eppdata); 402 return eppdata; 403 } 404 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 405 ret = le16_to_cpu(eppdata); 406 407 if (err) { 408 s->epp_timeout = 1; 409 pdebug("re%04x t\n", ret); 410 } 411 else 412 pdebug("re%04x\n", ret); 413 trace_parallel_ioport_read("EPP", addr, ret); 414 return ret; 415 } 416 417 static uint32_t 418 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 419 { 420 ParallelState *s = opaque; 421 uint32_t ret; 422 uint32_t eppdata = ~0U; 423 int err; 424 struct ParallelIOArg ioarg = { 425 .buffer = &eppdata, .count = sizeof(eppdata) 426 }; 427 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 428 /* Controls not correct for EPP data cycle, so do nothing */ 429 pdebug("re%08x s\n", eppdata); 430 return eppdata; 431 } 432 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 433 ret = le32_to_cpu(eppdata); 434 435 if (err) { 436 s->epp_timeout = 1; 437 pdebug("re%08x t\n", ret); 438 } 439 else 440 pdebug("re%08x\n", ret); 441 trace_parallel_ioport_read("EPP", addr, ret); 442 return ret; 443 } 444 445 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 446 { 447 trace_parallel_ioport_write("ECP", addr & 7, val); 448 pdebug("wecp%d=%02x\n", addr & 7, val); 449 } 450 451 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 452 { 453 uint8_t ret = 0xff; 454 455 trace_parallel_ioport_read("ECP", addr & 7, ret); 456 pdebug("recp%d:%02x\n", addr & 7, ret); 457 return ret; 458 } 459 460 static void parallel_reset(void *opaque) 461 { 462 ParallelState *s = opaque; 463 464 s->datar = ~0; 465 s->dataw = ~0; 466 s->status = PARA_STS_BUSY; 467 s->status |= PARA_STS_ACK; 468 s->status |= PARA_STS_ONLINE; 469 s->status |= PARA_STS_ERROR; 470 s->status |= PARA_STS_TMOUT; 471 s->control = PARA_CTR_SELECT; 472 s->control |= PARA_CTR_INIT; 473 s->control |= 0xc0; 474 s->irq_pending = 0; 475 s->hw_driver = 0; 476 s->epp_timeout = 0; 477 s->last_read_offset = ~0U; 478 } 479 480 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 481 482 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 483 { 0, 8, 1, 484 .read = parallel_ioport_read_hw, 485 .write = parallel_ioport_write_hw }, 486 { 4, 1, 2, 487 .read = parallel_ioport_eppdata_read_hw2, 488 .write = parallel_ioport_eppdata_write_hw2 }, 489 { 4, 1, 4, 490 .read = parallel_ioport_eppdata_read_hw4, 491 .write = parallel_ioport_eppdata_write_hw4 }, 492 { 0x400, 8, 1, 493 .read = parallel_ioport_ecp_read, 494 .write = parallel_ioport_ecp_write }, 495 PORTIO_END_OF_LIST(), 496 }; 497 498 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 499 { 0, 8, 1, 500 .read = parallel_ioport_read_sw, 501 .write = parallel_ioport_write_sw }, 502 PORTIO_END_OF_LIST(), 503 }; 504 505 506 static const VMStateDescription vmstate_parallel_isa = { 507 .name = "parallel_isa", 508 .version_id = 1, 509 .minimum_version_id = 1, 510 .fields = (VMStateField[]) { 511 VMSTATE_UINT8(state.dataw, ISAParallelState), 512 VMSTATE_UINT8(state.datar, ISAParallelState), 513 VMSTATE_UINT8(state.status, ISAParallelState), 514 VMSTATE_UINT8(state.control, ISAParallelState), 515 VMSTATE_INT32(state.irq_pending, ISAParallelState), 516 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 517 VMSTATE_END_OF_LIST() 518 } 519 }; 520 521 static int parallel_can_receive(void *opaque) 522 { 523 return 1; 524 } 525 526 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 527 { 528 static int index; 529 ISADevice *isadev = ISA_DEVICE(dev); 530 ISAParallelState *isa = ISA_PARALLEL(dev); 531 ParallelState *s = &isa->state; 532 int base; 533 uint8_t dummy; 534 535 if (!qemu_chr_fe_backend_connected(&s->chr)) { 536 error_setg(errp, "Can't create parallel device, empty char device"); 537 return; 538 } 539 540 if (isa->index == -1) { 541 isa->index = index; 542 } 543 if (isa->index >= MAX_PARALLEL_PORTS) { 544 error_setg(errp, "Max. supported number of parallel ports is %d.", 545 MAX_PARALLEL_PORTS); 546 return; 547 } 548 if (isa->iobase == -1) { 549 isa->iobase = isa_parallel_io[isa->index]; 550 } 551 index++; 552 553 base = isa->iobase; 554 isa_init_irq(isadev, &s->irq, isa->isairq); 555 qemu_register_reset(parallel_reset, s); 556 557 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, 558 NULL, NULL, s, NULL, true); 559 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 560 s->hw_driver = 1; 561 s->status = dummy; 562 } 563 564 isa_register_portio_list(isadev, &s->portio_list, base, 565 (s->hw_driver 566 ? &isa_parallel_portio_hw_list[0] 567 : &isa_parallel_portio_sw_list[0]), 568 s, "parallel"); 569 } 570 571 /* Memory mapped interface */ 572 static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) 573 { 574 ParallelState *s = opaque; 575 576 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 577 MAKE_64BIT_MASK(0, size * 8); 578 } 579 580 static void parallel_mm_writefn(void *opaque, hwaddr addr, 581 uint64_t value, unsigned size) 582 { 583 ParallelState *s = opaque; 584 585 parallel_ioport_write_sw(s, addr >> s->it_shift, 586 value & MAKE_64BIT_MASK(0, size * 8)); 587 } 588 589 static const MemoryRegionOps parallel_mm_ops = { 590 .read = parallel_mm_readfn, 591 .write = parallel_mm_writefn, 592 .valid.min_access_size = 1, 593 .valid.max_access_size = 4, 594 .endianness = DEVICE_NATIVE_ENDIAN, 595 }; 596 597 /* If fd is zero, it means that the parallel device uses the console */ 598 bool parallel_mm_init(MemoryRegion *address_space, 599 hwaddr base, int it_shift, qemu_irq irq, 600 Chardev *chr) 601 { 602 ParallelState *s; 603 604 s = g_malloc0(sizeof(ParallelState)); 605 s->irq = irq; 606 qemu_chr_fe_init(&s->chr, chr, &error_abort); 607 s->it_shift = it_shift; 608 qemu_register_reset(parallel_reset, s); 609 610 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 611 "parallel", 8 << it_shift); 612 memory_region_add_subregion(address_space, base, &s->iomem); 613 return true; 614 } 615 616 static Property parallel_isa_properties[] = { 617 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 618 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 619 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 620 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 621 DEFINE_PROP_END_OF_LIST(), 622 }; 623 624 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 625 { 626 DeviceClass *dc = DEVICE_CLASS(klass); 627 628 dc->realize = parallel_isa_realizefn; 629 dc->vmsd = &vmstate_parallel_isa; 630 device_class_set_props(dc, parallel_isa_properties); 631 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 632 } 633 634 static const TypeInfo parallel_isa_info = { 635 .name = TYPE_ISA_PARALLEL, 636 .parent = TYPE_ISA_DEVICE, 637 .instance_size = sizeof(ISAParallelState), 638 .class_init = parallel_isa_class_initfn, 639 }; 640 641 static void parallel_register_types(void) 642 { 643 type_register_static(¶llel_isa_info); 644 } 645 646 type_init(parallel_register_types) 647