1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu/module.h" 29 #include "chardev/char-parallel.h" 30 #include "chardev/char-fe.h" 31 #include "hw/acpi/aml-build.h" 32 #include "hw/irq.h" 33 #include "hw/isa/isa.h" 34 #include "hw/qdev-properties.h" 35 #include "migration/vmstate.h" 36 #include "hw/char/parallel.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/sysemu.h" 39 #include "trace.h" 40 #include "qom/object.h" 41 42 //#define DEBUG_PARALLEL 43 44 #ifdef DEBUG_PARALLEL 45 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 46 #else 47 #define pdebug(fmt, ...) ((void)0) 48 #endif 49 50 #define PARA_REG_DATA 0 51 #define PARA_REG_STS 1 52 #define PARA_REG_CTR 2 53 #define PARA_REG_EPP_ADDR 3 54 #define PARA_REG_EPP_DATA 4 55 56 /* 57 * These are the definitions for the Printer Status Register 58 */ 59 #define PARA_STS_BUSY 0x80 /* Busy complement */ 60 #define PARA_STS_ACK 0x40 /* Acknowledge */ 61 #define PARA_STS_PAPER 0x20 /* Out of paper */ 62 #define PARA_STS_ONLINE 0x10 /* Online */ 63 #define PARA_STS_ERROR 0x08 /* Error complement */ 64 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 65 66 /* 67 * These are the definitions for the Printer Control Register 68 */ 69 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 70 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 71 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 72 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 73 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 74 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 75 76 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 77 78 typedef struct ParallelState { 79 MemoryRegion iomem; 80 uint8_t dataw; 81 uint8_t datar; 82 uint8_t status; 83 uint8_t control; 84 qemu_irq irq; 85 int irq_pending; 86 CharBackend chr; 87 int hw_driver; 88 int epp_timeout; 89 uint32_t last_read_offset; /* For debugging */ 90 /* Memory-mapped interface */ 91 int it_shift; 92 PortioList portio_list; 93 } ParallelState; 94 95 #define TYPE_ISA_PARALLEL "isa-parallel" 96 typedef struct ISAParallelState ISAParallelState; 97 DECLARE_INSTANCE_CHECKER(ISAParallelState, ISA_PARALLEL, 98 TYPE_ISA_PARALLEL) 99 100 struct ISAParallelState { 101 ISADevice parent_obj; 102 103 uint32_t index; 104 uint32_t iobase; 105 uint32_t isairq; 106 ParallelState state; 107 }; 108 109 static void parallel_update_irq(ParallelState *s) 110 { 111 if (s->irq_pending) 112 qemu_irq_raise(s->irq); 113 else 114 qemu_irq_lower(s->irq); 115 } 116 117 static void 118 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 119 { 120 ParallelState *s = opaque; 121 122 addr &= 7; 123 trace_parallel_ioport_write("SW", addr, val); 124 switch(addr) { 125 case PARA_REG_DATA: 126 s->dataw = val; 127 parallel_update_irq(s); 128 break; 129 case PARA_REG_CTR: 130 val |= 0xc0; 131 if ((val & PARA_CTR_INIT) == 0 ) { 132 s->status = PARA_STS_BUSY; 133 s->status |= PARA_STS_ACK; 134 s->status |= PARA_STS_ONLINE; 135 s->status |= PARA_STS_ERROR; 136 } 137 else if (val & PARA_CTR_SELECT) { 138 if (val & PARA_CTR_STROBE) { 139 s->status &= ~PARA_STS_BUSY; 140 if ((s->control & PARA_CTR_STROBE) == 0) 141 /* XXX this blocks entire thread. Rewrite to use 142 * qemu_chr_fe_write and background I/O callbacks */ 143 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); 144 } else { 145 if (s->control & PARA_CTR_INTEN) { 146 s->irq_pending = 1; 147 } 148 } 149 } 150 parallel_update_irq(s); 151 s->control = val; 152 break; 153 } 154 } 155 156 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 157 { 158 ParallelState *s = opaque; 159 uint8_t parm = val; 160 int dir; 161 162 /* Sometimes programs do several writes for timing purposes on old 163 HW. Take care not to waste time on writes that do nothing. */ 164 165 s->last_read_offset = ~0U; 166 167 addr &= 7; 168 trace_parallel_ioport_write("HW", addr, val); 169 switch(addr) { 170 case PARA_REG_DATA: 171 if (s->dataw == val) 172 return; 173 pdebug("wd%02x\n", val); 174 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 175 s->dataw = val; 176 break; 177 case PARA_REG_STS: 178 pdebug("ws%02x\n", val); 179 if (val & PARA_STS_TMOUT) 180 s->epp_timeout = 0; 181 break; 182 case PARA_REG_CTR: 183 val |= 0xc0; 184 if (s->control == val) 185 return; 186 pdebug("wc%02x\n", val); 187 188 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 189 if (val & PARA_CTR_DIR) { 190 dir = 1; 191 } else { 192 dir = 0; 193 } 194 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 195 parm &= ~PARA_CTR_DIR; 196 } 197 198 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 199 s->control = val; 200 break; 201 case PARA_REG_EPP_ADDR: 202 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 203 /* Controls not correct for EPP address cycle, so do nothing */ 204 pdebug("wa%02x s\n", val); 205 else { 206 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 207 if (qemu_chr_fe_ioctl(&s->chr, 208 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 209 s->epp_timeout = 1; 210 pdebug("wa%02x t\n", val); 211 } 212 else 213 pdebug("wa%02x\n", val); 214 } 215 break; 216 case PARA_REG_EPP_DATA: 217 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 218 /* Controls not correct for EPP data cycle, so do nothing */ 219 pdebug("we%02x s\n", val); 220 else { 221 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 222 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 223 s->epp_timeout = 1; 224 pdebug("we%02x t\n", val); 225 } 226 else 227 pdebug("we%02x\n", val); 228 } 229 break; 230 } 231 } 232 233 static void 234 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 235 { 236 ParallelState *s = opaque; 237 uint16_t eppdata = cpu_to_le16(val); 238 int err; 239 struct ParallelIOArg ioarg = { 240 .buffer = &eppdata, .count = sizeof(eppdata) 241 }; 242 243 trace_parallel_ioport_write("EPP", addr, val); 244 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 245 /* Controls not correct for EPP data cycle, so do nothing */ 246 pdebug("we%04x s\n", val); 247 return; 248 } 249 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 250 if (err) { 251 s->epp_timeout = 1; 252 pdebug("we%04x t\n", val); 253 } 254 else 255 pdebug("we%04x\n", val); 256 } 257 258 static void 259 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 260 { 261 ParallelState *s = opaque; 262 uint32_t eppdata = cpu_to_le32(val); 263 int err; 264 struct ParallelIOArg ioarg = { 265 .buffer = &eppdata, .count = sizeof(eppdata) 266 }; 267 268 trace_parallel_ioport_write("EPP", addr, val); 269 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 270 /* Controls not correct for EPP data cycle, so do nothing */ 271 pdebug("we%08x s\n", val); 272 return; 273 } 274 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 275 if (err) { 276 s->epp_timeout = 1; 277 pdebug("we%08x t\n", val); 278 } 279 else 280 pdebug("we%08x\n", val); 281 } 282 283 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 284 { 285 ParallelState *s = opaque; 286 uint32_t ret = 0xff; 287 288 addr &= 7; 289 switch(addr) { 290 case PARA_REG_DATA: 291 if (s->control & PARA_CTR_DIR) 292 ret = s->datar; 293 else 294 ret = s->dataw; 295 break; 296 case PARA_REG_STS: 297 ret = s->status; 298 s->irq_pending = 0; 299 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 300 /* XXX Fixme: wait 5 microseconds */ 301 if (s->status & PARA_STS_ACK) 302 s->status &= ~PARA_STS_ACK; 303 else { 304 /* XXX Fixme: wait 5 microseconds */ 305 s->status |= PARA_STS_ACK; 306 s->status |= PARA_STS_BUSY; 307 } 308 } 309 parallel_update_irq(s); 310 break; 311 case PARA_REG_CTR: 312 ret = s->control; 313 break; 314 } 315 trace_parallel_ioport_read("SW", addr, ret); 316 return ret; 317 } 318 319 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 320 { 321 ParallelState *s = opaque; 322 uint8_t ret = 0xff; 323 addr &= 7; 324 switch(addr) { 325 case PARA_REG_DATA: 326 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 327 if (s->last_read_offset != addr || s->datar != ret) 328 pdebug("rd%02x\n", ret); 329 s->datar = ret; 330 break; 331 case PARA_REG_STS: 332 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 333 ret &= ~PARA_STS_TMOUT; 334 if (s->epp_timeout) 335 ret |= PARA_STS_TMOUT; 336 if (s->last_read_offset != addr || s->status != ret) 337 pdebug("rs%02x\n", ret); 338 s->status = ret; 339 break; 340 case PARA_REG_CTR: 341 /* s->control has some bits fixed to 1. It is zero only when 342 it has not been yet written to. */ 343 if (s->control == 0) { 344 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 345 if (s->last_read_offset != addr) 346 pdebug("rc%02x\n", ret); 347 s->control = ret; 348 } 349 else { 350 ret = s->control; 351 if (s->last_read_offset != addr) 352 pdebug("rc%02x\n", ret); 353 } 354 break; 355 case PARA_REG_EPP_ADDR: 356 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 357 (PARA_CTR_DIR | PARA_CTR_INIT)) 358 /* Controls not correct for EPP addr cycle, so do nothing */ 359 pdebug("ra%02x s\n", ret); 360 else { 361 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 362 if (qemu_chr_fe_ioctl(&s->chr, 363 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 364 s->epp_timeout = 1; 365 pdebug("ra%02x t\n", ret); 366 } 367 else 368 pdebug("ra%02x\n", ret); 369 } 370 break; 371 case PARA_REG_EPP_DATA: 372 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 373 (PARA_CTR_DIR | PARA_CTR_INIT)) 374 /* Controls not correct for EPP data cycle, so do nothing */ 375 pdebug("re%02x s\n", ret); 376 else { 377 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 378 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 379 s->epp_timeout = 1; 380 pdebug("re%02x t\n", ret); 381 } 382 else 383 pdebug("re%02x\n", ret); 384 } 385 break; 386 } 387 trace_parallel_ioport_read("HW", addr, ret); 388 s->last_read_offset = addr; 389 return ret; 390 } 391 392 static uint32_t 393 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 394 { 395 ParallelState *s = opaque; 396 uint32_t ret; 397 uint16_t eppdata = ~0; 398 int err; 399 struct ParallelIOArg ioarg = { 400 .buffer = &eppdata, .count = sizeof(eppdata) 401 }; 402 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 403 /* Controls not correct for EPP data cycle, so do nothing */ 404 pdebug("re%04x s\n", eppdata); 405 return eppdata; 406 } 407 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 408 ret = le16_to_cpu(eppdata); 409 410 if (err) { 411 s->epp_timeout = 1; 412 pdebug("re%04x t\n", ret); 413 } 414 else 415 pdebug("re%04x\n", ret); 416 trace_parallel_ioport_read("EPP", addr, ret); 417 return ret; 418 } 419 420 static uint32_t 421 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 422 { 423 ParallelState *s = opaque; 424 uint32_t ret; 425 uint32_t eppdata = ~0U; 426 int err; 427 struct ParallelIOArg ioarg = { 428 .buffer = &eppdata, .count = sizeof(eppdata) 429 }; 430 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 431 /* Controls not correct for EPP data cycle, so do nothing */ 432 pdebug("re%08x s\n", eppdata); 433 return eppdata; 434 } 435 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 436 ret = le32_to_cpu(eppdata); 437 438 if (err) { 439 s->epp_timeout = 1; 440 pdebug("re%08x t\n", ret); 441 } 442 else 443 pdebug("re%08x\n", ret); 444 trace_parallel_ioport_read("EPP", addr, ret); 445 return ret; 446 } 447 448 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 449 { 450 trace_parallel_ioport_write("ECP", addr & 7, val); 451 pdebug("wecp%d=%02x\n", addr & 7, val); 452 } 453 454 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 455 { 456 uint8_t ret = 0xff; 457 458 trace_parallel_ioport_read("ECP", addr & 7, ret); 459 pdebug("recp%d:%02x\n", addr & 7, ret); 460 return ret; 461 } 462 463 static void parallel_reset(void *opaque) 464 { 465 ParallelState *s = opaque; 466 467 s->datar = ~0; 468 s->dataw = ~0; 469 s->status = PARA_STS_BUSY; 470 s->status |= PARA_STS_ACK; 471 s->status |= PARA_STS_ONLINE; 472 s->status |= PARA_STS_ERROR; 473 s->status |= PARA_STS_TMOUT; 474 s->control = PARA_CTR_SELECT; 475 s->control |= PARA_CTR_INIT; 476 s->control |= 0xc0; 477 s->irq_pending = 0; 478 s->hw_driver = 0; 479 s->epp_timeout = 0; 480 s->last_read_offset = ~0U; 481 } 482 483 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 484 485 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 486 { 0, 8, 1, 487 .read = parallel_ioport_read_hw, 488 .write = parallel_ioport_write_hw }, 489 { 4, 1, 2, 490 .read = parallel_ioport_eppdata_read_hw2, 491 .write = parallel_ioport_eppdata_write_hw2 }, 492 { 4, 1, 4, 493 .read = parallel_ioport_eppdata_read_hw4, 494 .write = parallel_ioport_eppdata_write_hw4 }, 495 { 0x400, 8, 1, 496 .read = parallel_ioport_ecp_read, 497 .write = parallel_ioport_ecp_write }, 498 PORTIO_END_OF_LIST(), 499 }; 500 501 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 502 { 0, 8, 1, 503 .read = parallel_ioport_read_sw, 504 .write = parallel_ioport_write_sw }, 505 PORTIO_END_OF_LIST(), 506 }; 507 508 509 static const VMStateDescription vmstate_parallel_isa = { 510 .name = "parallel_isa", 511 .version_id = 1, 512 .minimum_version_id = 1, 513 .fields = (VMStateField[]) { 514 VMSTATE_UINT8(state.dataw, ISAParallelState), 515 VMSTATE_UINT8(state.datar, ISAParallelState), 516 VMSTATE_UINT8(state.status, ISAParallelState), 517 VMSTATE_UINT8(state.control, ISAParallelState), 518 VMSTATE_INT32(state.irq_pending, ISAParallelState), 519 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 520 VMSTATE_END_OF_LIST() 521 } 522 }; 523 524 static int parallel_can_receive(void *opaque) 525 { 526 return 1; 527 } 528 529 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 530 { 531 static int index; 532 ISADevice *isadev = ISA_DEVICE(dev); 533 ISAParallelState *isa = ISA_PARALLEL(dev); 534 ParallelState *s = &isa->state; 535 int base; 536 uint8_t dummy; 537 538 if (!qemu_chr_fe_backend_connected(&s->chr)) { 539 error_setg(errp, "Can't create parallel device, empty char device"); 540 return; 541 } 542 543 if (isa->index == -1) { 544 isa->index = index; 545 } 546 if (isa->index >= MAX_PARALLEL_PORTS) { 547 error_setg(errp, "Max. supported number of parallel ports is %d.", 548 MAX_PARALLEL_PORTS); 549 return; 550 } 551 if (isa->iobase == -1) { 552 isa->iobase = isa_parallel_io[isa->index]; 553 } 554 index++; 555 556 base = isa->iobase; 557 isa_init_irq(isadev, &s->irq, isa->isairq); 558 qemu_register_reset(parallel_reset, s); 559 560 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, 561 NULL, NULL, s, NULL, true); 562 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 563 s->hw_driver = 1; 564 s->status = dummy; 565 } 566 567 isa_register_portio_list(isadev, &s->portio_list, base, 568 (s->hw_driver 569 ? &isa_parallel_portio_hw_list[0] 570 : &isa_parallel_portio_sw_list[0]), 571 s, "parallel"); 572 } 573 574 static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope) 575 { 576 ISAParallelState *isa = ISA_PARALLEL(isadev); 577 Aml *dev; 578 Aml *crs; 579 580 crs = aml_resource_template(); 581 aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08)); 582 aml_append(crs, aml_irq_no_flags(isa->isairq)); 583 584 dev = aml_device("LPT%d", isa->index + 1); 585 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 586 aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1))); 587 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 588 aml_append(dev, aml_name_decl("_CRS", crs)); 589 590 aml_append(scope, dev); 591 } 592 593 /* Memory mapped interface */ 594 static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) 595 { 596 ParallelState *s = opaque; 597 598 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 599 MAKE_64BIT_MASK(0, size * 8); 600 } 601 602 static void parallel_mm_writefn(void *opaque, hwaddr addr, 603 uint64_t value, unsigned size) 604 { 605 ParallelState *s = opaque; 606 607 parallel_ioport_write_sw(s, addr >> s->it_shift, 608 value & MAKE_64BIT_MASK(0, size * 8)); 609 } 610 611 static const MemoryRegionOps parallel_mm_ops = { 612 .read = parallel_mm_readfn, 613 .write = parallel_mm_writefn, 614 .valid.min_access_size = 1, 615 .valid.max_access_size = 4, 616 .endianness = DEVICE_NATIVE_ENDIAN, 617 }; 618 619 /* If fd is zero, it means that the parallel device uses the console */ 620 bool parallel_mm_init(MemoryRegion *address_space, 621 hwaddr base, int it_shift, qemu_irq irq, 622 Chardev *chr) 623 { 624 ParallelState *s; 625 626 s = g_malloc0(sizeof(ParallelState)); 627 s->irq = irq; 628 qemu_chr_fe_init(&s->chr, chr, &error_abort); 629 s->it_shift = it_shift; 630 qemu_register_reset(parallel_reset, s); 631 632 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 633 "parallel", 8 << it_shift); 634 memory_region_add_subregion(address_space, base, &s->iomem); 635 return true; 636 } 637 638 static Property parallel_isa_properties[] = { 639 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 640 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 641 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 642 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 643 DEFINE_PROP_END_OF_LIST(), 644 }; 645 646 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 647 { 648 DeviceClass *dc = DEVICE_CLASS(klass); 649 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass); 650 651 dc->realize = parallel_isa_realizefn; 652 dc->vmsd = &vmstate_parallel_isa; 653 isa->build_aml = parallel_isa_build_aml; 654 device_class_set_props(dc, parallel_isa_properties); 655 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 656 } 657 658 static const TypeInfo parallel_isa_info = { 659 .name = TYPE_ISA_PARALLEL, 660 .parent = TYPE_ISA_DEVICE, 661 .instance_size = sizeof(ISAParallelState), 662 .class_init = parallel_isa_class_initfn, 663 }; 664 665 static void parallel_register_types(void) 666 { 667 type_register_static(¶llel_isa_info); 668 } 669 670 type_init(parallel_register_types) 671