1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu/module.h" 29 #include "hw/hw.h" 30 #include "chardev/char-parallel.h" 31 #include "chardev/char-fe.h" 32 #include "hw/irq.h" 33 #include "hw/isa/isa.h" 34 #include "hw/char/parallel.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/sysemu.h" 37 #include "trace.h" 38 39 //#define DEBUG_PARALLEL 40 41 #ifdef DEBUG_PARALLEL 42 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 43 #else 44 #define pdebug(fmt, ...) ((void)0) 45 #endif 46 47 #define PARA_REG_DATA 0 48 #define PARA_REG_STS 1 49 #define PARA_REG_CTR 2 50 #define PARA_REG_EPP_ADDR 3 51 #define PARA_REG_EPP_DATA 4 52 53 /* 54 * These are the definitions for the Printer Status Register 55 */ 56 #define PARA_STS_BUSY 0x80 /* Busy complement */ 57 #define PARA_STS_ACK 0x40 /* Acknowledge */ 58 #define PARA_STS_PAPER 0x20 /* Out of paper */ 59 #define PARA_STS_ONLINE 0x10 /* Online */ 60 #define PARA_STS_ERROR 0x08 /* Error complement */ 61 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 62 63 /* 64 * These are the definitions for the Printer Control Register 65 */ 66 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 67 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 68 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 69 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 70 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 71 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 72 73 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 74 75 typedef struct ParallelState { 76 MemoryRegion iomem; 77 uint8_t dataw; 78 uint8_t datar; 79 uint8_t status; 80 uint8_t control; 81 qemu_irq irq; 82 int irq_pending; 83 CharBackend chr; 84 int hw_driver; 85 int epp_timeout; 86 uint32_t last_read_offset; /* For debugging */ 87 /* Memory-mapped interface */ 88 int it_shift; 89 PortioList portio_list; 90 } ParallelState; 91 92 #define TYPE_ISA_PARALLEL "isa-parallel" 93 #define ISA_PARALLEL(obj) \ 94 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) 95 96 typedef struct ISAParallelState { 97 ISADevice parent_obj; 98 99 uint32_t index; 100 uint32_t iobase; 101 uint32_t isairq; 102 ParallelState state; 103 } ISAParallelState; 104 105 static void parallel_update_irq(ParallelState *s) 106 { 107 if (s->irq_pending) 108 qemu_irq_raise(s->irq); 109 else 110 qemu_irq_lower(s->irq); 111 } 112 113 static void 114 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 115 { 116 ParallelState *s = opaque; 117 118 addr &= 7; 119 trace_parallel_ioport_write("SW", addr, val); 120 switch(addr) { 121 case PARA_REG_DATA: 122 s->dataw = val; 123 parallel_update_irq(s); 124 break; 125 case PARA_REG_CTR: 126 val |= 0xc0; 127 if ((val & PARA_CTR_INIT) == 0 ) { 128 s->status = PARA_STS_BUSY; 129 s->status |= PARA_STS_ACK; 130 s->status |= PARA_STS_ONLINE; 131 s->status |= PARA_STS_ERROR; 132 } 133 else if (val & PARA_CTR_SELECT) { 134 if (val & PARA_CTR_STROBE) { 135 s->status &= ~PARA_STS_BUSY; 136 if ((s->control & PARA_CTR_STROBE) == 0) 137 /* XXX this blocks entire thread. Rewrite to use 138 * qemu_chr_fe_write and background I/O callbacks */ 139 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); 140 } else { 141 if (s->control & PARA_CTR_INTEN) { 142 s->irq_pending = 1; 143 } 144 } 145 } 146 parallel_update_irq(s); 147 s->control = val; 148 break; 149 } 150 } 151 152 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 153 { 154 ParallelState *s = opaque; 155 uint8_t parm = val; 156 int dir; 157 158 /* Sometimes programs do several writes for timing purposes on old 159 HW. Take care not to waste time on writes that do nothing. */ 160 161 s->last_read_offset = ~0U; 162 163 addr &= 7; 164 trace_parallel_ioport_write("HW", addr, val); 165 switch(addr) { 166 case PARA_REG_DATA: 167 if (s->dataw == val) 168 return; 169 pdebug("wd%02x\n", val); 170 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 171 s->dataw = val; 172 break; 173 case PARA_REG_STS: 174 pdebug("ws%02x\n", val); 175 if (val & PARA_STS_TMOUT) 176 s->epp_timeout = 0; 177 break; 178 case PARA_REG_CTR: 179 val |= 0xc0; 180 if (s->control == val) 181 return; 182 pdebug("wc%02x\n", val); 183 184 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 185 if (val & PARA_CTR_DIR) { 186 dir = 1; 187 } else { 188 dir = 0; 189 } 190 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 191 parm &= ~PARA_CTR_DIR; 192 } 193 194 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 195 s->control = val; 196 break; 197 case PARA_REG_EPP_ADDR: 198 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 199 /* Controls not correct for EPP address cycle, so do nothing */ 200 pdebug("wa%02x s\n", val); 201 else { 202 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 203 if (qemu_chr_fe_ioctl(&s->chr, 204 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 205 s->epp_timeout = 1; 206 pdebug("wa%02x t\n", val); 207 } 208 else 209 pdebug("wa%02x\n", val); 210 } 211 break; 212 case PARA_REG_EPP_DATA: 213 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 214 /* Controls not correct for EPP data cycle, so do nothing */ 215 pdebug("we%02x s\n", val); 216 else { 217 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 218 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 219 s->epp_timeout = 1; 220 pdebug("we%02x t\n", val); 221 } 222 else 223 pdebug("we%02x\n", val); 224 } 225 break; 226 } 227 } 228 229 static void 230 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 231 { 232 ParallelState *s = opaque; 233 uint16_t eppdata = cpu_to_le16(val); 234 int err; 235 struct ParallelIOArg ioarg = { 236 .buffer = &eppdata, .count = sizeof(eppdata) 237 }; 238 239 trace_parallel_ioport_write("EPP", addr, val); 240 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 241 /* Controls not correct for EPP data cycle, so do nothing */ 242 pdebug("we%04x s\n", val); 243 return; 244 } 245 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 246 if (err) { 247 s->epp_timeout = 1; 248 pdebug("we%04x t\n", val); 249 } 250 else 251 pdebug("we%04x\n", val); 252 } 253 254 static void 255 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 256 { 257 ParallelState *s = opaque; 258 uint32_t eppdata = cpu_to_le32(val); 259 int err; 260 struct ParallelIOArg ioarg = { 261 .buffer = &eppdata, .count = sizeof(eppdata) 262 }; 263 264 trace_parallel_ioport_write("EPP", addr, val); 265 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 266 /* Controls not correct for EPP data cycle, so do nothing */ 267 pdebug("we%08x s\n", val); 268 return; 269 } 270 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 271 if (err) { 272 s->epp_timeout = 1; 273 pdebug("we%08x t\n", val); 274 } 275 else 276 pdebug("we%08x\n", val); 277 } 278 279 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 280 { 281 ParallelState *s = opaque; 282 uint32_t ret = 0xff; 283 284 addr &= 7; 285 switch(addr) { 286 case PARA_REG_DATA: 287 if (s->control & PARA_CTR_DIR) 288 ret = s->datar; 289 else 290 ret = s->dataw; 291 break; 292 case PARA_REG_STS: 293 ret = s->status; 294 s->irq_pending = 0; 295 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 296 /* XXX Fixme: wait 5 microseconds */ 297 if (s->status & PARA_STS_ACK) 298 s->status &= ~PARA_STS_ACK; 299 else { 300 /* XXX Fixme: wait 5 microseconds */ 301 s->status |= PARA_STS_ACK; 302 s->status |= PARA_STS_BUSY; 303 } 304 } 305 parallel_update_irq(s); 306 break; 307 case PARA_REG_CTR: 308 ret = s->control; 309 break; 310 } 311 trace_parallel_ioport_read("SW", addr, ret); 312 return ret; 313 } 314 315 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 316 { 317 ParallelState *s = opaque; 318 uint8_t ret = 0xff; 319 addr &= 7; 320 switch(addr) { 321 case PARA_REG_DATA: 322 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 323 if (s->last_read_offset != addr || s->datar != ret) 324 pdebug("rd%02x\n", ret); 325 s->datar = ret; 326 break; 327 case PARA_REG_STS: 328 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 329 ret &= ~PARA_STS_TMOUT; 330 if (s->epp_timeout) 331 ret |= PARA_STS_TMOUT; 332 if (s->last_read_offset != addr || s->status != ret) 333 pdebug("rs%02x\n", ret); 334 s->status = ret; 335 break; 336 case PARA_REG_CTR: 337 /* s->control has some bits fixed to 1. It is zero only when 338 it has not been yet written to. */ 339 if (s->control == 0) { 340 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 341 if (s->last_read_offset != addr) 342 pdebug("rc%02x\n", ret); 343 s->control = ret; 344 } 345 else { 346 ret = s->control; 347 if (s->last_read_offset != addr) 348 pdebug("rc%02x\n", ret); 349 } 350 break; 351 case PARA_REG_EPP_ADDR: 352 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 353 (PARA_CTR_DIR | PARA_CTR_INIT)) 354 /* Controls not correct for EPP addr cycle, so do nothing */ 355 pdebug("ra%02x s\n", ret); 356 else { 357 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 358 if (qemu_chr_fe_ioctl(&s->chr, 359 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 360 s->epp_timeout = 1; 361 pdebug("ra%02x t\n", ret); 362 } 363 else 364 pdebug("ra%02x\n", ret); 365 } 366 break; 367 case PARA_REG_EPP_DATA: 368 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != 369 (PARA_CTR_DIR | PARA_CTR_INIT)) 370 /* Controls not correct for EPP data cycle, so do nothing */ 371 pdebug("re%02x s\n", ret); 372 else { 373 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 374 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 375 s->epp_timeout = 1; 376 pdebug("re%02x t\n", ret); 377 } 378 else 379 pdebug("re%02x\n", ret); 380 } 381 break; 382 } 383 trace_parallel_ioport_read("HW", addr, ret); 384 s->last_read_offset = addr; 385 return ret; 386 } 387 388 static uint32_t 389 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 390 { 391 ParallelState *s = opaque; 392 uint32_t ret; 393 uint16_t eppdata = ~0; 394 int err; 395 struct ParallelIOArg ioarg = { 396 .buffer = &eppdata, .count = sizeof(eppdata) 397 }; 398 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 399 /* Controls not correct for EPP data cycle, so do nothing */ 400 pdebug("re%04x s\n", eppdata); 401 return eppdata; 402 } 403 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 404 ret = le16_to_cpu(eppdata); 405 406 if (err) { 407 s->epp_timeout = 1; 408 pdebug("re%04x t\n", ret); 409 } 410 else 411 pdebug("re%04x\n", ret); 412 trace_parallel_ioport_read("EPP", addr, ret); 413 return ret; 414 } 415 416 static uint32_t 417 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 418 { 419 ParallelState *s = opaque; 420 uint32_t ret; 421 uint32_t eppdata = ~0U; 422 int err; 423 struct ParallelIOArg ioarg = { 424 .buffer = &eppdata, .count = sizeof(eppdata) 425 }; 426 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 427 /* Controls not correct for EPP data cycle, so do nothing */ 428 pdebug("re%08x s\n", eppdata); 429 return eppdata; 430 } 431 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 432 ret = le32_to_cpu(eppdata); 433 434 if (err) { 435 s->epp_timeout = 1; 436 pdebug("re%08x t\n", ret); 437 } 438 else 439 pdebug("re%08x\n", ret); 440 trace_parallel_ioport_read("EPP", addr, ret); 441 return ret; 442 } 443 444 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 445 { 446 trace_parallel_ioport_write("ECP", addr & 7, val); 447 pdebug("wecp%d=%02x\n", addr & 7, val); 448 } 449 450 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 451 { 452 uint8_t ret = 0xff; 453 454 trace_parallel_ioport_read("ECP", addr & 7, ret); 455 pdebug("recp%d:%02x\n", addr & 7, ret); 456 return ret; 457 } 458 459 static void parallel_reset(void *opaque) 460 { 461 ParallelState *s = opaque; 462 463 s->datar = ~0; 464 s->dataw = ~0; 465 s->status = PARA_STS_BUSY; 466 s->status |= PARA_STS_ACK; 467 s->status |= PARA_STS_ONLINE; 468 s->status |= PARA_STS_ERROR; 469 s->status |= PARA_STS_TMOUT; 470 s->control = PARA_CTR_SELECT; 471 s->control |= PARA_CTR_INIT; 472 s->control |= 0xc0; 473 s->irq_pending = 0; 474 s->hw_driver = 0; 475 s->epp_timeout = 0; 476 s->last_read_offset = ~0U; 477 } 478 479 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 480 481 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 482 { 0, 8, 1, 483 .read = parallel_ioport_read_hw, 484 .write = parallel_ioport_write_hw }, 485 { 4, 1, 2, 486 .read = parallel_ioport_eppdata_read_hw2, 487 .write = parallel_ioport_eppdata_write_hw2 }, 488 { 4, 1, 4, 489 .read = parallel_ioport_eppdata_read_hw4, 490 .write = parallel_ioport_eppdata_write_hw4 }, 491 { 0x400, 8, 1, 492 .read = parallel_ioport_ecp_read, 493 .write = parallel_ioport_ecp_write }, 494 PORTIO_END_OF_LIST(), 495 }; 496 497 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 498 { 0, 8, 1, 499 .read = parallel_ioport_read_sw, 500 .write = parallel_ioport_write_sw }, 501 PORTIO_END_OF_LIST(), 502 }; 503 504 505 static const VMStateDescription vmstate_parallel_isa = { 506 .name = "parallel_isa", 507 .version_id = 1, 508 .minimum_version_id = 1, 509 .fields = (VMStateField[]) { 510 VMSTATE_UINT8(state.dataw, ISAParallelState), 511 VMSTATE_UINT8(state.datar, ISAParallelState), 512 VMSTATE_UINT8(state.status, ISAParallelState), 513 VMSTATE_UINT8(state.control, ISAParallelState), 514 VMSTATE_INT32(state.irq_pending, ISAParallelState), 515 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 516 VMSTATE_END_OF_LIST() 517 } 518 }; 519 520 static int parallel_can_receive(void *opaque) 521 { 522 return 1; 523 } 524 525 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 526 { 527 static int index; 528 ISADevice *isadev = ISA_DEVICE(dev); 529 ISAParallelState *isa = ISA_PARALLEL(dev); 530 ParallelState *s = &isa->state; 531 int base; 532 uint8_t dummy; 533 534 if (!qemu_chr_fe_backend_connected(&s->chr)) { 535 error_setg(errp, "Can't create parallel device, empty char device"); 536 return; 537 } 538 539 if (isa->index == -1) { 540 isa->index = index; 541 } 542 if (isa->index >= MAX_PARALLEL_PORTS) { 543 error_setg(errp, "Max. supported number of parallel ports is %d.", 544 MAX_PARALLEL_PORTS); 545 return; 546 } 547 if (isa->iobase == -1) { 548 isa->iobase = isa_parallel_io[isa->index]; 549 } 550 index++; 551 552 base = isa->iobase; 553 isa_init_irq(isadev, &s->irq, isa->isairq); 554 qemu_register_reset(parallel_reset, s); 555 556 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, 557 NULL, NULL, s, NULL, true); 558 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 559 s->hw_driver = 1; 560 s->status = dummy; 561 } 562 563 isa_register_portio_list(isadev, &s->portio_list, base, 564 (s->hw_driver 565 ? &isa_parallel_portio_hw_list[0] 566 : &isa_parallel_portio_sw_list[0]), 567 s, "parallel"); 568 } 569 570 /* Memory mapped interface */ 571 static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) 572 { 573 ParallelState *s = opaque; 574 575 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 576 MAKE_64BIT_MASK(0, size * 8); 577 } 578 579 static void parallel_mm_writefn(void *opaque, hwaddr addr, 580 uint64_t value, unsigned size) 581 { 582 ParallelState *s = opaque; 583 584 parallel_ioport_write_sw(s, addr >> s->it_shift, 585 value & MAKE_64BIT_MASK(0, size * 8)); 586 } 587 588 static const MemoryRegionOps parallel_mm_ops = { 589 .read = parallel_mm_readfn, 590 .write = parallel_mm_writefn, 591 .valid.min_access_size = 1, 592 .valid.max_access_size = 4, 593 .endianness = DEVICE_NATIVE_ENDIAN, 594 }; 595 596 /* If fd is zero, it means that the parallel device uses the console */ 597 bool parallel_mm_init(MemoryRegion *address_space, 598 hwaddr base, int it_shift, qemu_irq irq, 599 Chardev *chr) 600 { 601 ParallelState *s; 602 603 s = g_malloc0(sizeof(ParallelState)); 604 s->irq = irq; 605 qemu_chr_fe_init(&s->chr, chr, &error_abort); 606 s->it_shift = it_shift; 607 qemu_register_reset(parallel_reset, s); 608 609 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 610 "parallel", 8 << it_shift); 611 memory_region_add_subregion(address_space, base, &s->iomem); 612 return true; 613 } 614 615 static Property parallel_isa_properties[] = { 616 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 617 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 618 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 619 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 620 DEFINE_PROP_END_OF_LIST(), 621 }; 622 623 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 624 { 625 DeviceClass *dc = DEVICE_CLASS(klass); 626 627 dc->realize = parallel_isa_realizefn; 628 dc->vmsd = &vmstate_parallel_isa; 629 dc->props = parallel_isa_properties; 630 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 631 } 632 633 static const TypeInfo parallel_isa_info = { 634 .name = TYPE_ISA_PARALLEL, 635 .parent = TYPE_ISA_DEVICE, 636 .instance_size = sizeof(ISAParallelState), 637 .class_init = parallel_isa_class_initfn, 638 }; 639 640 static void parallel_register_types(void) 641 { 642 type_register_static(¶llel_isa_info); 643 } 644 645 type_init(parallel_register_types) 646