149ab747fSPaolo Bonzini /* 249ab747fSPaolo Bonzini * QEMU Parallel PORT emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2003-2005 Fabrice Bellard 549ab747fSPaolo Bonzini * Copyright (c) 2007 Marko Kohtala 649ab747fSPaolo Bonzini * 749ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 849ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 949ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 1049ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1149ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1249ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1349ab747fSPaolo Bonzini * 1449ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1549ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1649ab747fSPaolo Bonzini * 1749ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1849ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1949ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2049ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2149ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2249ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2349ab747fSPaolo Bonzini * THE SOFTWARE. 2449ab747fSPaolo Bonzini */ 2549ab747fSPaolo Bonzini #include "hw/hw.h" 26*dccfcd0eSPaolo Bonzini #include "sysemu/char.h" 2749ab747fSPaolo Bonzini #include "hw/isa/isa.h" 2849ab747fSPaolo Bonzini #include "hw/i386/pc.h" 2949ab747fSPaolo Bonzini #include "sysemu/sysemu.h" 3049ab747fSPaolo Bonzini 3149ab747fSPaolo Bonzini //#define DEBUG_PARALLEL 3249ab747fSPaolo Bonzini 3349ab747fSPaolo Bonzini #ifdef DEBUG_PARALLEL 3449ab747fSPaolo Bonzini #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 3549ab747fSPaolo Bonzini #else 3649ab747fSPaolo Bonzini #define pdebug(fmt, ...) ((void)0) 3749ab747fSPaolo Bonzini #endif 3849ab747fSPaolo Bonzini 3949ab747fSPaolo Bonzini #define PARA_REG_DATA 0 4049ab747fSPaolo Bonzini #define PARA_REG_STS 1 4149ab747fSPaolo Bonzini #define PARA_REG_CTR 2 4249ab747fSPaolo Bonzini #define PARA_REG_EPP_ADDR 3 4349ab747fSPaolo Bonzini #define PARA_REG_EPP_DATA 4 4449ab747fSPaolo Bonzini 4549ab747fSPaolo Bonzini /* 4649ab747fSPaolo Bonzini * These are the definitions for the Printer Status Register 4749ab747fSPaolo Bonzini */ 4849ab747fSPaolo Bonzini #define PARA_STS_BUSY 0x80 /* Busy complement */ 4949ab747fSPaolo Bonzini #define PARA_STS_ACK 0x40 /* Acknowledge */ 5049ab747fSPaolo Bonzini #define PARA_STS_PAPER 0x20 /* Out of paper */ 5149ab747fSPaolo Bonzini #define PARA_STS_ONLINE 0x10 /* Online */ 5249ab747fSPaolo Bonzini #define PARA_STS_ERROR 0x08 /* Error complement */ 5349ab747fSPaolo Bonzini #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 5449ab747fSPaolo Bonzini 5549ab747fSPaolo Bonzini /* 5649ab747fSPaolo Bonzini * These are the definitions for the Printer Control Register 5749ab747fSPaolo Bonzini */ 5849ab747fSPaolo Bonzini #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 5949ab747fSPaolo Bonzini #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 6049ab747fSPaolo Bonzini #define PARA_CTR_SELECT 0x08 /* Select In complement */ 6149ab747fSPaolo Bonzini #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 6249ab747fSPaolo Bonzini #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 6349ab747fSPaolo Bonzini #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 6449ab747fSPaolo Bonzini 6549ab747fSPaolo Bonzini #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 6649ab747fSPaolo Bonzini 6749ab747fSPaolo Bonzini typedef struct ParallelState { 6849ab747fSPaolo Bonzini MemoryRegion iomem; 6949ab747fSPaolo Bonzini uint8_t dataw; 7049ab747fSPaolo Bonzini uint8_t datar; 7149ab747fSPaolo Bonzini uint8_t status; 7249ab747fSPaolo Bonzini uint8_t control; 7349ab747fSPaolo Bonzini qemu_irq irq; 7449ab747fSPaolo Bonzini int irq_pending; 7549ab747fSPaolo Bonzini CharDriverState *chr; 7649ab747fSPaolo Bonzini int hw_driver; 7749ab747fSPaolo Bonzini int epp_timeout; 7849ab747fSPaolo Bonzini uint32_t last_read_offset; /* For debugging */ 7949ab747fSPaolo Bonzini /* Memory-mapped interface */ 8049ab747fSPaolo Bonzini int it_shift; 8149ab747fSPaolo Bonzini } ParallelState; 8249ab747fSPaolo Bonzini 8349ab747fSPaolo Bonzini typedef struct ISAParallelState { 8449ab747fSPaolo Bonzini ISADevice dev; 8549ab747fSPaolo Bonzini uint32_t index; 8649ab747fSPaolo Bonzini uint32_t iobase; 8749ab747fSPaolo Bonzini uint32_t isairq; 8849ab747fSPaolo Bonzini ParallelState state; 8949ab747fSPaolo Bonzini } ISAParallelState; 9049ab747fSPaolo Bonzini 9149ab747fSPaolo Bonzini static void parallel_update_irq(ParallelState *s) 9249ab747fSPaolo Bonzini { 9349ab747fSPaolo Bonzini if (s->irq_pending) 9449ab747fSPaolo Bonzini qemu_irq_raise(s->irq); 9549ab747fSPaolo Bonzini else 9649ab747fSPaolo Bonzini qemu_irq_lower(s->irq); 9749ab747fSPaolo Bonzini } 9849ab747fSPaolo Bonzini 9949ab747fSPaolo Bonzini static void 10049ab747fSPaolo Bonzini parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 10149ab747fSPaolo Bonzini { 10249ab747fSPaolo Bonzini ParallelState *s = opaque; 10349ab747fSPaolo Bonzini 10449ab747fSPaolo Bonzini pdebug("write addr=0x%02x val=0x%02x\n", addr, val); 10549ab747fSPaolo Bonzini 10649ab747fSPaolo Bonzini addr &= 7; 10749ab747fSPaolo Bonzini switch(addr) { 10849ab747fSPaolo Bonzini case PARA_REG_DATA: 10949ab747fSPaolo Bonzini s->dataw = val; 11049ab747fSPaolo Bonzini parallel_update_irq(s); 11149ab747fSPaolo Bonzini break; 11249ab747fSPaolo Bonzini case PARA_REG_CTR: 11349ab747fSPaolo Bonzini val |= 0xc0; 11449ab747fSPaolo Bonzini if ((val & PARA_CTR_INIT) == 0 ) { 11549ab747fSPaolo Bonzini s->status = PARA_STS_BUSY; 11649ab747fSPaolo Bonzini s->status |= PARA_STS_ACK; 11749ab747fSPaolo Bonzini s->status |= PARA_STS_ONLINE; 11849ab747fSPaolo Bonzini s->status |= PARA_STS_ERROR; 11949ab747fSPaolo Bonzini } 12049ab747fSPaolo Bonzini else if (val & PARA_CTR_SELECT) { 12149ab747fSPaolo Bonzini if (val & PARA_CTR_STROBE) { 12249ab747fSPaolo Bonzini s->status &= ~PARA_STS_BUSY; 12349ab747fSPaolo Bonzini if ((s->control & PARA_CTR_STROBE) == 0) 12449ab747fSPaolo Bonzini qemu_chr_fe_write(s->chr, &s->dataw, 1); 12549ab747fSPaolo Bonzini } else { 12649ab747fSPaolo Bonzini if (s->control & PARA_CTR_INTEN) { 12749ab747fSPaolo Bonzini s->irq_pending = 1; 12849ab747fSPaolo Bonzini } 12949ab747fSPaolo Bonzini } 13049ab747fSPaolo Bonzini } 13149ab747fSPaolo Bonzini parallel_update_irq(s); 13249ab747fSPaolo Bonzini s->control = val; 13349ab747fSPaolo Bonzini break; 13449ab747fSPaolo Bonzini } 13549ab747fSPaolo Bonzini } 13649ab747fSPaolo Bonzini 13749ab747fSPaolo Bonzini static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 13849ab747fSPaolo Bonzini { 13949ab747fSPaolo Bonzini ParallelState *s = opaque; 14049ab747fSPaolo Bonzini uint8_t parm = val; 14149ab747fSPaolo Bonzini int dir; 14249ab747fSPaolo Bonzini 14349ab747fSPaolo Bonzini /* Sometimes programs do several writes for timing purposes on old 14449ab747fSPaolo Bonzini HW. Take care not to waste time on writes that do nothing. */ 14549ab747fSPaolo Bonzini 14649ab747fSPaolo Bonzini s->last_read_offset = ~0U; 14749ab747fSPaolo Bonzini 14849ab747fSPaolo Bonzini addr &= 7; 14949ab747fSPaolo Bonzini switch(addr) { 15049ab747fSPaolo Bonzini case PARA_REG_DATA: 15149ab747fSPaolo Bonzini if (s->dataw == val) 15249ab747fSPaolo Bonzini return; 15349ab747fSPaolo Bonzini pdebug("wd%02x\n", val); 15449ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 15549ab747fSPaolo Bonzini s->dataw = val; 15649ab747fSPaolo Bonzini break; 15749ab747fSPaolo Bonzini case PARA_REG_STS: 15849ab747fSPaolo Bonzini pdebug("ws%02x\n", val); 15949ab747fSPaolo Bonzini if (val & PARA_STS_TMOUT) 16049ab747fSPaolo Bonzini s->epp_timeout = 0; 16149ab747fSPaolo Bonzini break; 16249ab747fSPaolo Bonzini case PARA_REG_CTR: 16349ab747fSPaolo Bonzini val |= 0xc0; 16449ab747fSPaolo Bonzini if (s->control == val) 16549ab747fSPaolo Bonzini return; 16649ab747fSPaolo Bonzini pdebug("wc%02x\n", val); 16749ab747fSPaolo Bonzini 16849ab747fSPaolo Bonzini if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 16949ab747fSPaolo Bonzini if (val & PARA_CTR_DIR) { 17049ab747fSPaolo Bonzini dir = 1; 17149ab747fSPaolo Bonzini } else { 17249ab747fSPaolo Bonzini dir = 0; 17349ab747fSPaolo Bonzini } 17449ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 17549ab747fSPaolo Bonzini parm &= ~PARA_CTR_DIR; 17649ab747fSPaolo Bonzini } 17749ab747fSPaolo Bonzini 17849ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 17949ab747fSPaolo Bonzini s->control = val; 18049ab747fSPaolo Bonzini break; 18149ab747fSPaolo Bonzini case PARA_REG_EPP_ADDR: 18249ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 18349ab747fSPaolo Bonzini /* Controls not correct for EPP address cycle, so do nothing */ 18449ab747fSPaolo Bonzini pdebug("wa%02x s\n", val); 18549ab747fSPaolo Bonzini else { 18649ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 18749ab747fSPaolo Bonzini if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 18849ab747fSPaolo Bonzini s->epp_timeout = 1; 18949ab747fSPaolo Bonzini pdebug("wa%02x t\n", val); 19049ab747fSPaolo Bonzini } 19149ab747fSPaolo Bonzini else 19249ab747fSPaolo Bonzini pdebug("wa%02x\n", val); 19349ab747fSPaolo Bonzini } 19449ab747fSPaolo Bonzini break; 19549ab747fSPaolo Bonzini case PARA_REG_EPP_DATA: 19649ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 19749ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 19849ab747fSPaolo Bonzini pdebug("we%02x s\n", val); 19949ab747fSPaolo Bonzini else { 20049ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 20149ab747fSPaolo Bonzini if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 20249ab747fSPaolo Bonzini s->epp_timeout = 1; 20349ab747fSPaolo Bonzini pdebug("we%02x t\n", val); 20449ab747fSPaolo Bonzini } 20549ab747fSPaolo Bonzini else 20649ab747fSPaolo Bonzini pdebug("we%02x\n", val); 20749ab747fSPaolo Bonzini } 20849ab747fSPaolo Bonzini break; 20949ab747fSPaolo Bonzini } 21049ab747fSPaolo Bonzini } 21149ab747fSPaolo Bonzini 21249ab747fSPaolo Bonzini static void 21349ab747fSPaolo Bonzini parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 21449ab747fSPaolo Bonzini { 21549ab747fSPaolo Bonzini ParallelState *s = opaque; 21649ab747fSPaolo Bonzini uint16_t eppdata = cpu_to_le16(val); 21749ab747fSPaolo Bonzini int err; 21849ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { 21949ab747fSPaolo Bonzini .buffer = &eppdata, .count = sizeof(eppdata) 22049ab747fSPaolo Bonzini }; 22149ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 22249ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 22349ab747fSPaolo Bonzini pdebug("we%04x s\n", val); 22449ab747fSPaolo Bonzini return; 22549ab747fSPaolo Bonzini } 22649ab747fSPaolo Bonzini err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 22749ab747fSPaolo Bonzini if (err) { 22849ab747fSPaolo Bonzini s->epp_timeout = 1; 22949ab747fSPaolo Bonzini pdebug("we%04x t\n", val); 23049ab747fSPaolo Bonzini } 23149ab747fSPaolo Bonzini else 23249ab747fSPaolo Bonzini pdebug("we%04x\n", val); 23349ab747fSPaolo Bonzini } 23449ab747fSPaolo Bonzini 23549ab747fSPaolo Bonzini static void 23649ab747fSPaolo Bonzini parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 23749ab747fSPaolo Bonzini { 23849ab747fSPaolo Bonzini ParallelState *s = opaque; 23949ab747fSPaolo Bonzini uint32_t eppdata = cpu_to_le32(val); 24049ab747fSPaolo Bonzini int err; 24149ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { 24249ab747fSPaolo Bonzini .buffer = &eppdata, .count = sizeof(eppdata) 24349ab747fSPaolo Bonzini }; 24449ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 24549ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 24649ab747fSPaolo Bonzini pdebug("we%08x s\n", val); 24749ab747fSPaolo Bonzini return; 24849ab747fSPaolo Bonzini } 24949ab747fSPaolo Bonzini err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 25049ab747fSPaolo Bonzini if (err) { 25149ab747fSPaolo Bonzini s->epp_timeout = 1; 25249ab747fSPaolo Bonzini pdebug("we%08x t\n", val); 25349ab747fSPaolo Bonzini } 25449ab747fSPaolo Bonzini else 25549ab747fSPaolo Bonzini pdebug("we%08x\n", val); 25649ab747fSPaolo Bonzini } 25749ab747fSPaolo Bonzini 25849ab747fSPaolo Bonzini static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 25949ab747fSPaolo Bonzini { 26049ab747fSPaolo Bonzini ParallelState *s = opaque; 26149ab747fSPaolo Bonzini uint32_t ret = 0xff; 26249ab747fSPaolo Bonzini 26349ab747fSPaolo Bonzini addr &= 7; 26449ab747fSPaolo Bonzini switch(addr) { 26549ab747fSPaolo Bonzini case PARA_REG_DATA: 26649ab747fSPaolo Bonzini if (s->control & PARA_CTR_DIR) 26749ab747fSPaolo Bonzini ret = s->datar; 26849ab747fSPaolo Bonzini else 26949ab747fSPaolo Bonzini ret = s->dataw; 27049ab747fSPaolo Bonzini break; 27149ab747fSPaolo Bonzini case PARA_REG_STS: 27249ab747fSPaolo Bonzini ret = s->status; 27349ab747fSPaolo Bonzini s->irq_pending = 0; 27449ab747fSPaolo Bonzini if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 27549ab747fSPaolo Bonzini /* XXX Fixme: wait 5 microseconds */ 27649ab747fSPaolo Bonzini if (s->status & PARA_STS_ACK) 27749ab747fSPaolo Bonzini s->status &= ~PARA_STS_ACK; 27849ab747fSPaolo Bonzini else { 27949ab747fSPaolo Bonzini /* XXX Fixme: wait 5 microseconds */ 28049ab747fSPaolo Bonzini s->status |= PARA_STS_ACK; 28149ab747fSPaolo Bonzini s->status |= PARA_STS_BUSY; 28249ab747fSPaolo Bonzini } 28349ab747fSPaolo Bonzini } 28449ab747fSPaolo Bonzini parallel_update_irq(s); 28549ab747fSPaolo Bonzini break; 28649ab747fSPaolo Bonzini case PARA_REG_CTR: 28749ab747fSPaolo Bonzini ret = s->control; 28849ab747fSPaolo Bonzini break; 28949ab747fSPaolo Bonzini } 29049ab747fSPaolo Bonzini pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); 29149ab747fSPaolo Bonzini return ret; 29249ab747fSPaolo Bonzini } 29349ab747fSPaolo Bonzini 29449ab747fSPaolo Bonzini static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 29549ab747fSPaolo Bonzini { 29649ab747fSPaolo Bonzini ParallelState *s = opaque; 29749ab747fSPaolo Bonzini uint8_t ret = 0xff; 29849ab747fSPaolo Bonzini addr &= 7; 29949ab747fSPaolo Bonzini switch(addr) { 30049ab747fSPaolo Bonzini case PARA_REG_DATA: 30149ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 30249ab747fSPaolo Bonzini if (s->last_read_offset != addr || s->datar != ret) 30349ab747fSPaolo Bonzini pdebug("rd%02x\n", ret); 30449ab747fSPaolo Bonzini s->datar = ret; 30549ab747fSPaolo Bonzini break; 30649ab747fSPaolo Bonzini case PARA_REG_STS: 30749ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 30849ab747fSPaolo Bonzini ret &= ~PARA_STS_TMOUT; 30949ab747fSPaolo Bonzini if (s->epp_timeout) 31049ab747fSPaolo Bonzini ret |= PARA_STS_TMOUT; 31149ab747fSPaolo Bonzini if (s->last_read_offset != addr || s->status != ret) 31249ab747fSPaolo Bonzini pdebug("rs%02x\n", ret); 31349ab747fSPaolo Bonzini s->status = ret; 31449ab747fSPaolo Bonzini break; 31549ab747fSPaolo Bonzini case PARA_REG_CTR: 31649ab747fSPaolo Bonzini /* s->control has some bits fixed to 1. It is zero only when 31749ab747fSPaolo Bonzini it has not been yet written to. */ 31849ab747fSPaolo Bonzini if (s->control == 0) { 31949ab747fSPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 32049ab747fSPaolo Bonzini if (s->last_read_offset != addr) 32149ab747fSPaolo Bonzini pdebug("rc%02x\n", ret); 32249ab747fSPaolo Bonzini s->control = ret; 32349ab747fSPaolo Bonzini } 32449ab747fSPaolo Bonzini else { 32549ab747fSPaolo Bonzini ret = s->control; 32649ab747fSPaolo Bonzini if (s->last_read_offset != addr) 32749ab747fSPaolo Bonzini pdebug("rc%02x\n", ret); 32849ab747fSPaolo Bonzini } 32949ab747fSPaolo Bonzini break; 33049ab747fSPaolo Bonzini case PARA_REG_EPP_ADDR: 33149ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 33249ab747fSPaolo Bonzini /* Controls not correct for EPP addr cycle, so do nothing */ 33349ab747fSPaolo Bonzini pdebug("ra%02x s\n", ret); 33449ab747fSPaolo Bonzini else { 33549ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 33649ab747fSPaolo Bonzini if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 33749ab747fSPaolo Bonzini s->epp_timeout = 1; 33849ab747fSPaolo Bonzini pdebug("ra%02x t\n", ret); 33949ab747fSPaolo Bonzini } 34049ab747fSPaolo Bonzini else 34149ab747fSPaolo Bonzini pdebug("ra%02x\n", ret); 34249ab747fSPaolo Bonzini } 34349ab747fSPaolo Bonzini break; 34449ab747fSPaolo Bonzini case PARA_REG_EPP_DATA: 34549ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 34649ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 34749ab747fSPaolo Bonzini pdebug("re%02x s\n", ret); 34849ab747fSPaolo Bonzini else { 34949ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 35049ab747fSPaolo Bonzini if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 35149ab747fSPaolo Bonzini s->epp_timeout = 1; 35249ab747fSPaolo Bonzini pdebug("re%02x t\n", ret); 35349ab747fSPaolo Bonzini } 35449ab747fSPaolo Bonzini else 35549ab747fSPaolo Bonzini pdebug("re%02x\n", ret); 35649ab747fSPaolo Bonzini } 35749ab747fSPaolo Bonzini break; 35849ab747fSPaolo Bonzini } 35949ab747fSPaolo Bonzini s->last_read_offset = addr; 36049ab747fSPaolo Bonzini return ret; 36149ab747fSPaolo Bonzini } 36249ab747fSPaolo Bonzini 36349ab747fSPaolo Bonzini static uint32_t 36449ab747fSPaolo Bonzini parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 36549ab747fSPaolo Bonzini { 36649ab747fSPaolo Bonzini ParallelState *s = opaque; 36749ab747fSPaolo Bonzini uint32_t ret; 36849ab747fSPaolo Bonzini uint16_t eppdata = ~0; 36949ab747fSPaolo Bonzini int err; 37049ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { 37149ab747fSPaolo Bonzini .buffer = &eppdata, .count = sizeof(eppdata) 37249ab747fSPaolo Bonzini }; 37349ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 37449ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 37549ab747fSPaolo Bonzini pdebug("re%04x s\n", eppdata); 37649ab747fSPaolo Bonzini return eppdata; 37749ab747fSPaolo Bonzini } 37849ab747fSPaolo Bonzini err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 37949ab747fSPaolo Bonzini ret = le16_to_cpu(eppdata); 38049ab747fSPaolo Bonzini 38149ab747fSPaolo Bonzini if (err) { 38249ab747fSPaolo Bonzini s->epp_timeout = 1; 38349ab747fSPaolo Bonzini pdebug("re%04x t\n", ret); 38449ab747fSPaolo Bonzini } 38549ab747fSPaolo Bonzini else 38649ab747fSPaolo Bonzini pdebug("re%04x\n", ret); 38749ab747fSPaolo Bonzini return ret; 38849ab747fSPaolo Bonzini } 38949ab747fSPaolo Bonzini 39049ab747fSPaolo Bonzini static uint32_t 39149ab747fSPaolo Bonzini parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 39249ab747fSPaolo Bonzini { 39349ab747fSPaolo Bonzini ParallelState *s = opaque; 39449ab747fSPaolo Bonzini uint32_t ret; 39549ab747fSPaolo Bonzini uint32_t eppdata = ~0U; 39649ab747fSPaolo Bonzini int err; 39749ab747fSPaolo Bonzini struct ParallelIOArg ioarg = { 39849ab747fSPaolo Bonzini .buffer = &eppdata, .count = sizeof(eppdata) 39949ab747fSPaolo Bonzini }; 40049ab747fSPaolo Bonzini if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 40149ab747fSPaolo Bonzini /* Controls not correct for EPP data cycle, so do nothing */ 40249ab747fSPaolo Bonzini pdebug("re%08x s\n", eppdata); 40349ab747fSPaolo Bonzini return eppdata; 40449ab747fSPaolo Bonzini } 40549ab747fSPaolo Bonzini err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 40649ab747fSPaolo Bonzini ret = le32_to_cpu(eppdata); 40749ab747fSPaolo Bonzini 40849ab747fSPaolo Bonzini if (err) { 40949ab747fSPaolo Bonzini s->epp_timeout = 1; 41049ab747fSPaolo Bonzini pdebug("re%08x t\n", ret); 41149ab747fSPaolo Bonzini } 41249ab747fSPaolo Bonzini else 41349ab747fSPaolo Bonzini pdebug("re%08x\n", ret); 41449ab747fSPaolo Bonzini return ret; 41549ab747fSPaolo Bonzini } 41649ab747fSPaolo Bonzini 41749ab747fSPaolo Bonzini static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 41849ab747fSPaolo Bonzini { 41949ab747fSPaolo Bonzini pdebug("wecp%d=%02x\n", addr & 7, val); 42049ab747fSPaolo Bonzini } 42149ab747fSPaolo Bonzini 42249ab747fSPaolo Bonzini static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 42349ab747fSPaolo Bonzini { 42449ab747fSPaolo Bonzini uint8_t ret = 0xff; 42549ab747fSPaolo Bonzini 42649ab747fSPaolo Bonzini pdebug("recp%d:%02x\n", addr & 7, ret); 42749ab747fSPaolo Bonzini return ret; 42849ab747fSPaolo Bonzini } 42949ab747fSPaolo Bonzini 43049ab747fSPaolo Bonzini static void parallel_reset(void *opaque) 43149ab747fSPaolo Bonzini { 43249ab747fSPaolo Bonzini ParallelState *s = opaque; 43349ab747fSPaolo Bonzini 43449ab747fSPaolo Bonzini s->datar = ~0; 43549ab747fSPaolo Bonzini s->dataw = ~0; 43649ab747fSPaolo Bonzini s->status = PARA_STS_BUSY; 43749ab747fSPaolo Bonzini s->status |= PARA_STS_ACK; 43849ab747fSPaolo Bonzini s->status |= PARA_STS_ONLINE; 43949ab747fSPaolo Bonzini s->status |= PARA_STS_ERROR; 44049ab747fSPaolo Bonzini s->status |= PARA_STS_TMOUT; 44149ab747fSPaolo Bonzini s->control = PARA_CTR_SELECT; 44249ab747fSPaolo Bonzini s->control |= PARA_CTR_INIT; 44349ab747fSPaolo Bonzini s->control |= 0xc0; 44449ab747fSPaolo Bonzini s->irq_pending = 0; 44549ab747fSPaolo Bonzini s->hw_driver = 0; 44649ab747fSPaolo Bonzini s->epp_timeout = 0; 44749ab747fSPaolo Bonzini s->last_read_offset = ~0U; 44849ab747fSPaolo Bonzini } 44949ab747fSPaolo Bonzini 45049ab747fSPaolo Bonzini static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 45149ab747fSPaolo Bonzini 45249ab747fSPaolo Bonzini static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 45349ab747fSPaolo Bonzini { 0, 8, 1, 45449ab747fSPaolo Bonzini .read = parallel_ioport_read_hw, 45549ab747fSPaolo Bonzini .write = parallel_ioport_write_hw }, 45649ab747fSPaolo Bonzini { 4, 1, 2, 45749ab747fSPaolo Bonzini .read = parallel_ioport_eppdata_read_hw2, 45849ab747fSPaolo Bonzini .write = parallel_ioport_eppdata_write_hw2 }, 45949ab747fSPaolo Bonzini { 4, 1, 4, 46049ab747fSPaolo Bonzini .read = parallel_ioport_eppdata_read_hw4, 46149ab747fSPaolo Bonzini .write = parallel_ioport_eppdata_write_hw4 }, 46249ab747fSPaolo Bonzini { 0x400, 8, 1, 46349ab747fSPaolo Bonzini .read = parallel_ioport_ecp_read, 46449ab747fSPaolo Bonzini .write = parallel_ioport_ecp_write }, 46549ab747fSPaolo Bonzini PORTIO_END_OF_LIST(), 46649ab747fSPaolo Bonzini }; 46749ab747fSPaolo Bonzini 46849ab747fSPaolo Bonzini static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 46949ab747fSPaolo Bonzini { 0, 8, 1, 47049ab747fSPaolo Bonzini .read = parallel_ioport_read_sw, 47149ab747fSPaolo Bonzini .write = parallel_ioport_write_sw }, 47249ab747fSPaolo Bonzini PORTIO_END_OF_LIST(), 47349ab747fSPaolo Bonzini }; 47449ab747fSPaolo Bonzini 47549ab747fSPaolo Bonzini static int parallel_isa_initfn(ISADevice *dev) 47649ab747fSPaolo Bonzini { 47749ab747fSPaolo Bonzini static int index; 47849ab747fSPaolo Bonzini ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev); 47949ab747fSPaolo Bonzini ParallelState *s = &isa->state; 48049ab747fSPaolo Bonzini int base; 48149ab747fSPaolo Bonzini uint8_t dummy; 48249ab747fSPaolo Bonzini 48349ab747fSPaolo Bonzini if (!s->chr) { 48449ab747fSPaolo Bonzini fprintf(stderr, "Can't create parallel device, empty char device\n"); 48549ab747fSPaolo Bonzini exit(1); 48649ab747fSPaolo Bonzini } 48749ab747fSPaolo Bonzini 48849ab747fSPaolo Bonzini if (isa->index == -1) 48949ab747fSPaolo Bonzini isa->index = index; 49049ab747fSPaolo Bonzini if (isa->index >= MAX_PARALLEL_PORTS) 49149ab747fSPaolo Bonzini return -1; 49249ab747fSPaolo Bonzini if (isa->iobase == -1) 49349ab747fSPaolo Bonzini isa->iobase = isa_parallel_io[isa->index]; 49449ab747fSPaolo Bonzini index++; 49549ab747fSPaolo Bonzini 49649ab747fSPaolo Bonzini base = isa->iobase; 49749ab747fSPaolo Bonzini isa_init_irq(dev, &s->irq, isa->isairq); 49849ab747fSPaolo Bonzini qemu_register_reset(parallel_reset, s); 49949ab747fSPaolo Bonzini 50049ab747fSPaolo Bonzini if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 50149ab747fSPaolo Bonzini s->hw_driver = 1; 50249ab747fSPaolo Bonzini s->status = dummy; 50349ab747fSPaolo Bonzini } 50449ab747fSPaolo Bonzini 50549ab747fSPaolo Bonzini isa_register_portio_list(dev, base, 50649ab747fSPaolo Bonzini (s->hw_driver 50749ab747fSPaolo Bonzini ? &isa_parallel_portio_hw_list[0] 50849ab747fSPaolo Bonzini : &isa_parallel_portio_sw_list[0]), 50949ab747fSPaolo Bonzini s, "parallel"); 51049ab747fSPaolo Bonzini return 0; 51149ab747fSPaolo Bonzini } 51249ab747fSPaolo Bonzini 51349ab747fSPaolo Bonzini /* Memory mapped interface */ 51449ab747fSPaolo Bonzini static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) 51549ab747fSPaolo Bonzini { 51649ab747fSPaolo Bonzini ParallelState *s = opaque; 51749ab747fSPaolo Bonzini 51849ab747fSPaolo Bonzini return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; 51949ab747fSPaolo Bonzini } 52049ab747fSPaolo Bonzini 52149ab747fSPaolo Bonzini static void parallel_mm_writeb (void *opaque, 52249ab747fSPaolo Bonzini hwaddr addr, uint32_t value) 52349ab747fSPaolo Bonzini { 52449ab747fSPaolo Bonzini ParallelState *s = opaque; 52549ab747fSPaolo Bonzini 52649ab747fSPaolo Bonzini parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); 52749ab747fSPaolo Bonzini } 52849ab747fSPaolo Bonzini 52949ab747fSPaolo Bonzini static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) 53049ab747fSPaolo Bonzini { 53149ab747fSPaolo Bonzini ParallelState *s = opaque; 53249ab747fSPaolo Bonzini 53349ab747fSPaolo Bonzini return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; 53449ab747fSPaolo Bonzini } 53549ab747fSPaolo Bonzini 53649ab747fSPaolo Bonzini static void parallel_mm_writew (void *opaque, 53749ab747fSPaolo Bonzini hwaddr addr, uint32_t value) 53849ab747fSPaolo Bonzini { 53949ab747fSPaolo Bonzini ParallelState *s = opaque; 54049ab747fSPaolo Bonzini 54149ab747fSPaolo Bonzini parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); 54249ab747fSPaolo Bonzini } 54349ab747fSPaolo Bonzini 54449ab747fSPaolo Bonzini static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) 54549ab747fSPaolo Bonzini { 54649ab747fSPaolo Bonzini ParallelState *s = opaque; 54749ab747fSPaolo Bonzini 54849ab747fSPaolo Bonzini return parallel_ioport_read_sw(s, addr >> s->it_shift); 54949ab747fSPaolo Bonzini } 55049ab747fSPaolo Bonzini 55149ab747fSPaolo Bonzini static void parallel_mm_writel (void *opaque, 55249ab747fSPaolo Bonzini hwaddr addr, uint32_t value) 55349ab747fSPaolo Bonzini { 55449ab747fSPaolo Bonzini ParallelState *s = opaque; 55549ab747fSPaolo Bonzini 55649ab747fSPaolo Bonzini parallel_ioport_write_sw(s, addr >> s->it_shift, value); 55749ab747fSPaolo Bonzini } 55849ab747fSPaolo Bonzini 55949ab747fSPaolo Bonzini static const MemoryRegionOps parallel_mm_ops = { 56049ab747fSPaolo Bonzini .old_mmio = { 56149ab747fSPaolo Bonzini .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, 56249ab747fSPaolo Bonzini .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, 56349ab747fSPaolo Bonzini }, 56449ab747fSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 56549ab747fSPaolo Bonzini }; 56649ab747fSPaolo Bonzini 56749ab747fSPaolo Bonzini /* If fd is zero, it means that the parallel device uses the console */ 56849ab747fSPaolo Bonzini bool parallel_mm_init(MemoryRegion *address_space, 56949ab747fSPaolo Bonzini hwaddr base, int it_shift, qemu_irq irq, 57049ab747fSPaolo Bonzini CharDriverState *chr) 57149ab747fSPaolo Bonzini { 57249ab747fSPaolo Bonzini ParallelState *s; 57349ab747fSPaolo Bonzini 57449ab747fSPaolo Bonzini s = g_malloc0(sizeof(ParallelState)); 57549ab747fSPaolo Bonzini s->irq = irq; 57649ab747fSPaolo Bonzini s->chr = chr; 57749ab747fSPaolo Bonzini s->it_shift = it_shift; 57849ab747fSPaolo Bonzini qemu_register_reset(parallel_reset, s); 57949ab747fSPaolo Bonzini 58049ab747fSPaolo Bonzini memory_region_init_io(&s->iomem, ¶llel_mm_ops, s, 58149ab747fSPaolo Bonzini "parallel", 8 << it_shift); 58249ab747fSPaolo Bonzini memory_region_add_subregion(address_space, base, &s->iomem); 58349ab747fSPaolo Bonzini return true; 58449ab747fSPaolo Bonzini } 58549ab747fSPaolo Bonzini 58649ab747fSPaolo Bonzini static Property parallel_isa_properties[] = { 58749ab747fSPaolo Bonzini DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 58849ab747fSPaolo Bonzini DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1), 58949ab747fSPaolo Bonzini DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 59049ab747fSPaolo Bonzini DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 59149ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 59249ab747fSPaolo Bonzini }; 59349ab747fSPaolo Bonzini 59449ab747fSPaolo Bonzini static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 59549ab747fSPaolo Bonzini { 59649ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 59749ab747fSPaolo Bonzini ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); 59849ab747fSPaolo Bonzini ic->init = parallel_isa_initfn; 59949ab747fSPaolo Bonzini dc->props = parallel_isa_properties; 60049ab747fSPaolo Bonzini } 60149ab747fSPaolo Bonzini 60249ab747fSPaolo Bonzini static const TypeInfo parallel_isa_info = { 60349ab747fSPaolo Bonzini .name = "isa-parallel", 60449ab747fSPaolo Bonzini .parent = TYPE_ISA_DEVICE, 60549ab747fSPaolo Bonzini .instance_size = sizeof(ISAParallelState), 60649ab747fSPaolo Bonzini .class_init = parallel_isa_class_initfn, 60749ab747fSPaolo Bonzini }; 60849ab747fSPaolo Bonzini 60949ab747fSPaolo Bonzini static void parallel_register_types(void) 61049ab747fSPaolo Bonzini { 61149ab747fSPaolo Bonzini type_register_static(¶llel_isa_info); 61249ab747fSPaolo Bonzini } 61349ab747fSPaolo Bonzini 61449ab747fSPaolo Bonzini type_init(parallel_register_types) 615