xref: /openbmc/qemu/hw/char/nrf51_uart.c (revision 64552b6b)
1 /*
2  * nRF51 SoC UART emulation
3  *
4  * See nRF51 Series Reference Manual, "29 Universal Asynchronous
5  * Receiver/Transmitter" for hardware specifications:
6  * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
7  *
8  * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 or
12  * (at your option) any later version.
13  */
14 
15 #include "qemu/osdep.h"
16 #include "qemu/log.h"
17 #include "qemu/module.h"
18 #include "hw/char/nrf51_uart.h"
19 #include "hw/irq.h"
20 #include "trace.h"
21 
22 static void nrf51_uart_update_irq(NRF51UARTState *s)
23 {
24     bool irq = false;
25 
26     irq |= (s->reg[R_UART_RXDRDY] &&
27             (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
28     irq |= (s->reg[R_UART_TXDRDY] &&
29             (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
30     irq |= (s->reg[R_UART_ERROR]  &&
31             (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
32     irq |= (s->reg[R_UART_RXTO]   &&
33             (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
34 
35     qemu_set_irq(s->irq, irq);
36 }
37 
38 static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
39 {
40     NRF51UARTState *s = NRF51_UART(opaque);
41     uint64_t r;
42 
43     if (!s->enabled) {
44         return 0;
45     }
46 
47     switch (addr) {
48     case A_UART_RXD:
49         r = s->rx_fifo[s->rx_fifo_pos];
50         if (s->rx_started && s->rx_fifo_len) {
51             s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
52             s->rx_fifo_len--;
53             if (s->rx_fifo_len) {
54                 s->reg[R_UART_RXDRDY] = 1;
55                 nrf51_uart_update_irq(s);
56             }
57             qemu_chr_fe_accept_input(&s->chr);
58         }
59         break;
60     case A_UART_INTENSET:
61     case A_UART_INTENCLR:
62     case A_UART_INTEN:
63         r = s->reg[R_UART_INTEN];
64         break;
65     default:
66         r = s->reg[addr / 4];
67         break;
68     }
69 
70     trace_nrf51_uart_read(addr, r, size);
71 
72     return r;
73 }
74 
75 static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
76 {
77     NRF51UARTState *s = NRF51_UART(opaque);
78     int r;
79     uint8_t c = s->reg[R_UART_TXD];
80 
81     s->watch_tag = 0;
82 
83     r = qemu_chr_fe_write(&s->chr, &c, 1);
84     if (r <= 0) {
85         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
86                                              uart_transmit, s);
87         if (!s->watch_tag) {
88             /* The hardware has no transmit error reporting,
89              * so silently drop the byte
90              */
91             goto buffer_drained;
92         }
93         return FALSE;
94     }
95 
96 buffer_drained:
97     s->reg[R_UART_TXDRDY] = 1;
98     s->pending_tx_byte = false;
99     return FALSE;
100 }
101 
102 static void uart_cancel_transmit(NRF51UARTState *s)
103 {
104     if (s->watch_tag) {
105         g_source_remove(s->watch_tag);
106         s->watch_tag = 0;
107     }
108 }
109 
110 static void uart_write(void *opaque, hwaddr addr,
111                        uint64_t value, unsigned int size)
112 {
113     NRF51UARTState *s = NRF51_UART(opaque);
114 
115     trace_nrf51_uart_write(addr, value, size);
116 
117     if (!s->enabled && (addr != A_UART_ENABLE)) {
118         return;
119     }
120 
121     switch (addr) {
122     case A_UART_TXD:
123         if (!s->pending_tx_byte && s->tx_started) {
124             s->reg[R_UART_TXD] = value;
125             s->pending_tx_byte = true;
126             uart_transmit(NULL, G_IO_OUT, s);
127         }
128         break;
129     case A_UART_INTEN:
130         s->reg[R_UART_INTEN] = value;
131         break;
132     case A_UART_INTENSET:
133         s->reg[R_UART_INTEN] |= value;
134         break;
135     case A_UART_INTENCLR:
136         s->reg[R_UART_INTEN] &= ~value;
137         break;
138     case A_UART_TXDRDY ... A_UART_RXTO:
139         s->reg[addr / 4] = value;
140         break;
141     case A_UART_ERRORSRC:
142         s->reg[addr / 4] &= ~value;
143         break;
144     case A_UART_RXD:
145         break;
146     case A_UART_RXDRDY:
147         if (value == 0) {
148             s->reg[R_UART_RXDRDY] = 0;
149         }
150         break;
151     case A_UART_STARTTX:
152         if (value == 1) {
153             s->tx_started = true;
154         }
155         break;
156     case A_UART_STARTRX:
157         if (value == 1) {
158             s->rx_started = true;
159         }
160         break;
161     case A_UART_ENABLE:
162         if (value) {
163             if (value == 4) {
164                 s->enabled = true;
165             }
166             break;
167         }
168         s->enabled = false;
169         value = 1;
170         /* fall through */
171     case A_UART_SUSPEND:
172     case A_UART_STOPTX:
173         if (value == 1) {
174             s->tx_started = false;
175         }
176         /* fall through */
177     case A_UART_STOPRX:
178         if (addr != A_UART_STOPTX && value == 1) {
179             s->rx_started = false;
180             s->reg[R_UART_RXTO] = 1;
181         }
182         break;
183     default:
184         s->reg[addr / 4] = value;
185         break;
186     }
187     nrf51_uart_update_irq(s);
188 }
189 
190 static const MemoryRegionOps uart_ops = {
191     .read =  uart_read,
192     .write = uart_write,
193     .endianness = DEVICE_LITTLE_ENDIAN,
194 };
195 
196 static void nrf51_uart_reset(DeviceState *dev)
197 {
198     NRF51UARTState *s = NRF51_UART(dev);
199 
200     s->pending_tx_byte = 0;
201 
202     uart_cancel_transmit(s);
203 
204     memset(s->reg, 0, sizeof(s->reg));
205 
206     s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
207     s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
208     s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
209     s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
210     s->reg[R_UART_BAUDRATE] = 0x4000000;
211 
212     s->rx_fifo_len = 0;
213     s->rx_fifo_pos = 0;
214     s->rx_started = false;
215     s->tx_started = false;
216     s->enabled = false;
217 }
218 
219 static void uart_receive(void *opaque, const uint8_t *buf, int size)
220 {
221 
222     NRF51UARTState *s = NRF51_UART(opaque);
223     int i;
224 
225     if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
226         return;
227     }
228 
229     for (i = 0; i < size; i++) {
230         uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
231         s->rx_fifo[pos] = buf[i];
232         s->rx_fifo_len++;
233     }
234 
235     s->reg[R_UART_RXDRDY] = 1;
236     nrf51_uart_update_irq(s);
237 }
238 
239 static int uart_can_receive(void *opaque)
240 {
241     NRF51UARTState *s = NRF51_UART(opaque);
242 
243     return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
244 }
245 
246 static void uart_event(void *opaque, int event)
247 {
248     NRF51UARTState *s = NRF51_UART(opaque);
249 
250     if (event == CHR_EVENT_BREAK) {
251         s->reg[R_UART_ERRORSRC] |= 3;
252         s->reg[R_UART_ERROR] = 1;
253         nrf51_uart_update_irq(s);
254     }
255 }
256 
257 static void nrf51_uart_realize(DeviceState *dev, Error **errp)
258 {
259     NRF51UARTState *s = NRF51_UART(dev);
260 
261     qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
262                              uart_event, NULL, s, NULL, true);
263 }
264 
265 static void nrf51_uart_init(Object *obj)
266 {
267     NRF51UARTState *s = NRF51_UART(obj);
268     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
269 
270     memory_region_init_io(&s->iomem, obj, &uart_ops, s,
271                           "nrf51_soc.uart", UART_SIZE);
272     sysbus_init_mmio(sbd, &s->iomem);
273     sysbus_init_irq(sbd, &s->irq);
274 }
275 
276 static int nrf51_uart_post_load(void *opaque, int version_id)
277 {
278     NRF51UARTState *s = NRF51_UART(opaque);
279 
280     if (s->pending_tx_byte) {
281         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
282                                              uart_transmit, s);
283     }
284 
285     return 0;
286 }
287 
288 static const VMStateDescription nrf51_uart_vmstate = {
289     .name = "nrf51_soc.uart",
290     .post_load = nrf51_uart_post_load,
291     .fields = (VMStateField[]) {
292         VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
293         VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
294         VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
295         VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
296         VMSTATE_BOOL(rx_started, NRF51UARTState),
297         VMSTATE_BOOL(tx_started, NRF51UARTState),
298         VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
299         VMSTATE_BOOL(enabled, NRF51UARTState),
300         VMSTATE_END_OF_LIST()
301     }
302 };
303 
304 static Property nrf51_uart_properties[] = {
305     DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
306     DEFINE_PROP_END_OF_LIST(),
307 };
308 
309 static void nrf51_uart_class_init(ObjectClass *klass, void *data)
310 {
311     DeviceClass *dc = DEVICE_CLASS(klass);
312 
313     dc->reset = nrf51_uart_reset;
314     dc->realize = nrf51_uart_realize;
315     dc->props = nrf51_uart_properties;
316     dc->vmsd = &nrf51_uart_vmstate;
317 }
318 
319 static const TypeInfo nrf51_uart_info = {
320     .name = TYPE_NRF51_UART,
321     .parent = TYPE_SYS_BUS_DEVICE,
322     .instance_size = sizeof(NRF51UARTState),
323     .instance_init = nrf51_uart_init,
324     .class_init = nrf51_uart_class_init
325 };
326 
327 static void nrf51_uart_register_types(void)
328 {
329     type_register_static(&nrf51_uart_info);
330 }
331 
332 type_init(nrf51_uart_register_types)
333