1 /* 2 * Microchip PolarFire SoC MMUART emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/log.h" 25 #include "chardev/char.h" 26 #include "exec/address-spaces.h" 27 #include "hw/char/mchp_pfsoc_mmuart.h" 28 29 static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) 30 { 31 MchpPfSoCMMUartState *s = opaque; 32 33 if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { 34 qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", 35 __func__, addr); 36 return 0; 37 } 38 39 return s->reg[addr / sizeof(uint32_t)]; 40 } 41 42 static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, 43 uint64_t value, unsigned size) 44 { 45 MchpPfSoCMMUartState *s = opaque; 46 uint32_t val32 = (uint32_t)value; 47 48 if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { 49 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx 50 " v=0x%x\n", __func__, addr, val32); 51 return; 52 } 53 54 s->reg[addr / sizeof(uint32_t)] = val32; 55 } 56 57 static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { 58 .read = mchp_pfsoc_mmuart_read, 59 .write = mchp_pfsoc_mmuart_write, 60 .endianness = DEVICE_LITTLE_ENDIAN, 61 .impl = { 62 .min_access_size = 4, 63 .max_access_size = 4, 64 }, 65 }; 66 67 MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, 68 hwaddr base, qemu_irq irq, Chardev *chr) 69 { 70 MchpPfSoCMMUartState *s; 71 72 s = g_new0(MchpPfSoCMMUartState, 1); 73 74 memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, 75 "mchp.pfsoc.mmuart", 0x1000); 76 77 s->base = base; 78 s->irq = irq; 79 80 s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr, 81 DEVICE_LITTLE_ENDIAN); 82 83 memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); 84 85 return s; 86 } 87