1 /* 2 * QEMU GE IP-Octal 232 IndustryPack emulation 3 * 4 * Copyright (C) 2012 Igalia, S.L. 5 * Author: Alberto Garcia <berto@igalia.com> 6 * 7 * This code is licensed under the GNU GPL v2 or (at your option) any 8 * later version. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/ipack/ipack.h" 13 #include "hw/irq.h" 14 #include "migration/vmstate.h" 15 #include "qemu/bitops.h" 16 #include "qemu/module.h" 17 #include "chardev/char-fe.h" 18 19 /* #define DEBUG_IPOCTAL */ 20 21 #ifdef DEBUG_IPOCTAL 22 #define DPRINTF2(fmt, ...) \ 23 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 24 #else 25 #define DPRINTF2(fmt, ...) do { } while (0) 26 #endif 27 28 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__) 29 30 #define RX_FIFO_SIZE 3 31 32 /* The IP-Octal has 8 channels (a-h) 33 divided into 4 blocks (A-D) */ 34 #define N_CHANNELS 8 35 #define N_BLOCKS 4 36 37 #define REG_MRa 0x01 38 #define REG_MRb 0x11 39 #define REG_SRa 0x03 40 #define REG_SRb 0x13 41 #define REG_CSRa 0x03 42 #define REG_CSRb 0x13 43 #define REG_CRa 0x05 44 #define REG_CRb 0x15 45 #define REG_RHRa 0x07 46 #define REG_RHRb 0x17 47 #define REG_THRa 0x07 48 #define REG_THRb 0x17 49 #define REG_ACR 0x09 50 #define REG_ISR 0x0B 51 #define REG_IMR 0x0B 52 #define REG_OPCR 0x1B 53 54 #define CR_ENABLE_RX BIT(0) 55 #define CR_DISABLE_RX BIT(1) 56 #define CR_ENABLE_TX BIT(2) 57 #define CR_DISABLE_TX BIT(3) 58 #define CR_CMD(cr) ((cr) >> 4) 59 #define CR_NO_OP 0 60 #define CR_RESET_MR 1 61 #define CR_RESET_RX 2 62 #define CR_RESET_TX 3 63 #define CR_RESET_ERR 4 64 #define CR_RESET_BRKINT 5 65 #define CR_START_BRK 6 66 #define CR_STOP_BRK 7 67 #define CR_ASSERT_RTSN 8 68 #define CR_NEGATE_RTSN 9 69 #define CR_TIMEOUT_ON 10 70 #define CR_TIMEOUT_OFF 12 71 72 #define SR_RXRDY BIT(0) 73 #define SR_FFULL BIT(1) 74 #define SR_TXRDY BIT(2) 75 #define SR_TXEMT BIT(3) 76 #define SR_OVERRUN BIT(4) 77 #define SR_PARITY BIT(5) 78 #define SR_FRAMING BIT(6) 79 #define SR_BREAK BIT(7) 80 81 #define ISR_TXRDYA BIT(0) 82 #define ISR_RXRDYA BIT(1) 83 #define ISR_BREAKA BIT(2) 84 #define ISR_CNTRDY BIT(3) 85 #define ISR_TXRDYB BIT(4) 86 #define ISR_RXRDYB BIT(5) 87 #define ISR_BREAKB BIT(6) 88 #define ISR_MPICHG BIT(7) 89 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0)) 90 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1)) 91 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2)) 92 93 typedef struct IPOctalState IPOctalState; 94 typedef struct SCC2698Channel SCC2698Channel; 95 typedef struct SCC2698Block SCC2698Block; 96 97 struct SCC2698Channel { 98 IPOctalState *ipoctal; 99 CharBackend dev; 100 bool rx_enabled; 101 uint8_t mr[2]; 102 uint8_t mr_idx; 103 uint8_t sr; 104 uint8_t rhr[RX_FIFO_SIZE]; 105 uint8_t rhr_idx; 106 uint8_t rx_pending; 107 }; 108 109 struct SCC2698Block { 110 uint8_t imr; 111 uint8_t isr; 112 }; 113 114 struct IPOctalState { 115 IPackDevice parent_obj; 116 117 SCC2698Channel ch[N_CHANNELS]; 118 SCC2698Block blk[N_BLOCKS]; 119 uint8_t irq_vector; 120 }; 121 122 #define TYPE_IPOCTAL "ipoctal232" 123 124 #define IPOCTAL(obj) \ 125 OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL) 126 127 static const VMStateDescription vmstate_scc2698_channel = { 128 .name = "scc2698_channel", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .fields = (VMStateField[]) { 132 VMSTATE_BOOL(rx_enabled, SCC2698Channel), 133 VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2), 134 VMSTATE_UINT8(mr_idx, SCC2698Channel), 135 VMSTATE_UINT8(sr, SCC2698Channel), 136 VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE), 137 VMSTATE_UINT8(rhr_idx, SCC2698Channel), 138 VMSTATE_UINT8(rx_pending, SCC2698Channel), 139 VMSTATE_END_OF_LIST() 140 } 141 }; 142 143 static const VMStateDescription vmstate_scc2698_block = { 144 .name = "scc2698_block", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .fields = (VMStateField[]) { 148 VMSTATE_UINT8(imr, SCC2698Block), 149 VMSTATE_UINT8(isr, SCC2698Block), 150 VMSTATE_END_OF_LIST() 151 } 152 }; 153 154 static const VMStateDescription vmstate_ipoctal = { 155 .name = "ipoctal232", 156 .version_id = 1, 157 .minimum_version_id = 1, 158 .fields = (VMStateField[]) { 159 VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState), 160 VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1, 161 vmstate_scc2698_channel, SCC2698Channel), 162 VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1, 163 vmstate_scc2698_block, SCC2698Block), 164 VMSTATE_UINT8(irq_vector, IPOctalState), 165 VMSTATE_END_OF_LIST() 166 } 167 }; 168 169 /* data[10] is 0x0C, not 0x0B as the doc says */ 170 static const uint8_t id_prom_data[] = { 171 0x49, 0x50, 0x41, 0x43, 0xF0, 0x22, 172 0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC 173 }; 174 175 static void update_irq(IPOctalState *dev, unsigned block) 176 { 177 IPackDevice *idev = IPACK_DEVICE(dev); 178 /* Blocks A and B interrupt on INT0#, C and D on INT1#. 179 Thus, to get the status we have to check two blocks. */ 180 SCC2698Block *blk0 = &dev->blk[block]; 181 SCC2698Block *blk1 = &dev->blk[block^1]; 182 unsigned intno = block / 2; 183 184 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { 185 qemu_irq_raise(idev->irq[intno]); 186 } else { 187 qemu_irq_lower(idev->irq[intno]); 188 } 189 } 190 191 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val) 192 { 193 SCC2698Channel *ch = &dev->ch[channel]; 194 SCC2698Block *blk = &dev->blk[channel / 2]; 195 196 DPRINTF("Write CR%c %u: ", channel + 'a', val); 197 198 /* The lower 4 bits are used to enable and disable Tx and Rx */ 199 if (val & CR_ENABLE_RX) { 200 DPRINTF2("Rx on, "); 201 ch->rx_enabled = true; 202 } 203 if (val & CR_DISABLE_RX) { 204 DPRINTF2("Rx off, "); 205 ch->rx_enabled = false; 206 } 207 if (val & CR_ENABLE_TX) { 208 DPRINTF2("Tx on, "); 209 ch->sr |= SR_TXRDY | SR_TXEMT; 210 blk->isr |= ISR_TXRDY(channel); 211 } 212 if (val & CR_DISABLE_TX) { 213 DPRINTF2("Tx off, "); 214 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 215 blk->isr &= ~ISR_TXRDY(channel); 216 } 217 218 DPRINTF2("cmd: "); 219 220 /* The rest of the bits implement different commands */ 221 switch (CR_CMD(val)) { 222 case CR_NO_OP: 223 DPRINTF2("none"); 224 break; 225 case CR_RESET_MR: 226 DPRINTF2("reset MR"); 227 ch->mr_idx = 0; 228 break; 229 case CR_RESET_RX: 230 DPRINTF2("reset Rx"); 231 ch->rx_enabled = false; 232 ch->rx_pending = 0; 233 ch->sr &= ~SR_RXRDY; 234 blk->isr &= ~ISR_RXRDY(channel); 235 break; 236 case CR_RESET_TX: 237 DPRINTF2("reset Tx"); 238 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 239 blk->isr &= ~ISR_TXRDY(channel); 240 break; 241 case CR_RESET_ERR: 242 DPRINTF2("reset err"); 243 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK); 244 break; 245 case CR_RESET_BRKINT: 246 DPRINTF2("reset brk ch int"); 247 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); 248 break; 249 default: 250 DPRINTF2("unsupported 0x%x", CR_CMD(val)); 251 } 252 253 DPRINTF2("\n"); 254 } 255 256 static uint16_t io_read(IPackDevice *ip, uint8_t addr) 257 { 258 IPOctalState *dev = IPOCTAL(ip); 259 uint16_t ret = 0; 260 /* addr[7:6]: block (A-D) 261 addr[7:5]: channel (a-h) 262 addr[5:0]: register */ 263 unsigned block = addr >> 5; 264 unsigned channel = addr >> 4; 265 /* Big endian, accessed using 8-bit bytes at odd locations */ 266 unsigned offset = (addr & 0x1F) ^ 1; 267 SCC2698Channel *ch = &dev->ch[channel]; 268 SCC2698Block *blk = &dev->blk[block]; 269 uint8_t old_isr = blk->isr; 270 271 switch (offset) { 272 273 case REG_MRa: 274 case REG_MRb: 275 ret = ch->mr[ch->mr_idx]; 276 DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret); 277 ch->mr_idx = 1; 278 break; 279 280 case REG_SRa: 281 case REG_SRb: 282 ret = ch->sr; 283 DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret); 284 break; 285 286 case REG_RHRa: 287 case REG_RHRb: 288 ret = ch->rhr[ch->rhr_idx]; 289 if (ch->rx_pending > 0) { 290 ch->rx_pending--; 291 if (ch->rx_pending == 0) { 292 ch->sr &= ~SR_RXRDY; 293 blk->isr &= ~ISR_RXRDY(channel); 294 qemu_chr_fe_accept_input(&ch->dev); 295 } else { 296 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE; 297 } 298 if (ch->sr & SR_BREAK) { 299 ch->sr &= ~SR_BREAK; 300 blk->isr |= ISR_BREAK(channel); 301 } 302 } 303 DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret); 304 break; 305 306 case REG_ISR: 307 ret = blk->isr; 308 DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret); 309 break; 310 311 default: 312 DPRINTF("Read unknown/unsupported register 0x%02x\n", offset); 313 } 314 315 if (old_isr != blk->isr) { 316 update_irq(dev, block); 317 } 318 319 return ret; 320 } 321 322 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val) 323 { 324 IPOctalState *dev = IPOCTAL(ip); 325 unsigned reg = val & 0xFF; 326 /* addr[7:6]: block (A-D) 327 addr[7:5]: channel (a-h) 328 addr[5:0]: register */ 329 unsigned block = addr >> 5; 330 unsigned channel = addr >> 4; 331 /* Big endian, accessed using 8-bit bytes at odd locations */ 332 unsigned offset = (addr & 0x1F) ^ 1; 333 SCC2698Channel *ch = &dev->ch[channel]; 334 SCC2698Block *blk = &dev->blk[block]; 335 uint8_t old_isr = blk->isr; 336 uint8_t old_imr = blk->imr; 337 338 switch (offset) { 339 340 case REG_MRa: 341 case REG_MRb: 342 ch->mr[ch->mr_idx] = reg; 343 DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg); 344 ch->mr_idx = 1; 345 break; 346 347 /* Not implemented */ 348 case REG_CSRa: 349 case REG_CSRb: 350 DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg); 351 break; 352 353 case REG_CRa: 354 case REG_CRb: 355 write_cr(dev, channel, reg); 356 break; 357 358 case REG_THRa: 359 case REG_THRb: 360 if (ch->sr & SR_TXRDY) { 361 uint8_t thr = reg; 362 DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg); 363 /* XXX this blocks entire thread. Rewrite to use 364 * qemu_chr_fe_write and background I/O callbacks */ 365 qemu_chr_fe_write_all(&ch->dev, &thr, 1); 366 } else { 367 DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg); 368 } 369 break; 370 371 /* Not implemented */ 372 case REG_ACR: 373 DPRINTF("Write ACR%c 0x%x\n", block + 'A', val); 374 break; 375 376 case REG_IMR: 377 DPRINTF("Write IMR%c 0x%x\n", block + 'A', val); 378 blk->imr = reg; 379 break; 380 381 /* Not implemented */ 382 case REG_OPCR: 383 DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val); 384 break; 385 386 default: 387 DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val); 388 } 389 390 if (old_isr != blk->isr || old_imr != blk->imr) { 391 update_irq(dev, block); 392 } 393 } 394 395 static uint16_t id_read(IPackDevice *ip, uint8_t addr) 396 { 397 uint16_t ret = 0; 398 unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */ 399 400 if (pos < ARRAY_SIZE(id_prom_data)) { 401 ret = id_prom_data[pos]; 402 } else { 403 DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr); 404 } 405 406 return ret; 407 } 408 409 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val) 410 { 411 IPOctalState *dev = IPOCTAL(ip); 412 if (addr == 1) { 413 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 414 dev->irq_vector = val; /* Undocumented, but the hw works like that */ 415 } else { 416 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 417 } 418 } 419 420 static uint16_t int_read(IPackDevice *ip, uint8_t addr) 421 { 422 IPOctalState *dev = IPOCTAL(ip); 423 /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */ 424 if (addr != 0 && addr != 2) { 425 DPRINTF("Attempt to read from 0x%x\n", addr); 426 return 0; 427 } else { 428 /* Update interrupts if necessary */ 429 update_irq(dev, addr); 430 return dev->irq_vector; 431 } 432 } 433 434 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val) 435 { 436 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 437 } 438 439 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr) 440 { 441 DPRINTF("Attempt to read from 0x%x\n", addr); 442 return 0; 443 } 444 445 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val) 446 { 447 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 448 } 449 450 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr) 451 { 452 DPRINTF("Attempt to read from 0x%x\n", addr); 453 return 0; 454 } 455 456 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val) 457 { 458 IPOctalState *dev = IPOCTAL(ip); 459 if (addr == 1) { 460 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 461 dev->irq_vector = val; 462 } else { 463 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 464 } 465 } 466 467 static int hostdev_can_receive(void *opaque) 468 { 469 SCC2698Channel *ch = opaque; 470 int available_bytes = RX_FIFO_SIZE - ch->rx_pending; 471 return ch->rx_enabled ? available_bytes : 0; 472 } 473 474 static void hostdev_receive(void *opaque, const uint8_t *buf, int size) 475 { 476 SCC2698Channel *ch = opaque; 477 IPOctalState *dev = ch->ipoctal; 478 unsigned pos = ch->rhr_idx + ch->rx_pending; 479 int i; 480 481 assert(size + ch->rx_pending <= RX_FIFO_SIZE); 482 483 /* Copy data to the RxFIFO */ 484 for (i = 0; i < size; i++) { 485 pos %= RX_FIFO_SIZE; 486 ch->rhr[pos++] = buf[i]; 487 } 488 489 ch->rx_pending += size; 490 491 /* If the RxFIFO was empty raise an interrupt */ 492 if (!(ch->sr & SR_RXRDY)) { 493 unsigned block, channel = 0; 494 /* Find channel number to update the ISR register */ 495 while (&dev->ch[channel] != ch) { 496 channel++; 497 } 498 block = channel / 2; 499 dev->blk[block].isr |= ISR_RXRDY(channel); 500 ch->sr |= SR_RXRDY; 501 update_irq(dev, block); 502 } 503 } 504 505 static void hostdev_event(void *opaque, int event) 506 { 507 SCC2698Channel *ch = opaque; 508 switch (event) { 509 case CHR_EVENT_OPENED: 510 DPRINTF("Device %s opened\n", ch->dev->label); 511 break; 512 case CHR_EVENT_BREAK: { 513 uint8_t zero = 0; 514 DPRINTF("Device %s received break\n", ch->dev->label); 515 516 if (!(ch->sr & SR_BREAK)) { 517 IPOctalState *dev = ch->ipoctal; 518 unsigned block, channel = 0; 519 520 while (&dev->ch[channel] != ch) { 521 channel++; 522 } 523 block = channel / 2; 524 525 ch->sr |= SR_BREAK; 526 dev->blk[block].isr |= ISR_BREAK(channel); 527 } 528 529 /* Put a zero character in the buffer */ 530 hostdev_receive(ch, &zero, 1); 531 } 532 break; 533 default: 534 DPRINTF("Device %s received event %d\n", ch->dev->label, event); 535 } 536 } 537 538 static void ipoctal_realize(DeviceState *dev, Error **errp) 539 { 540 IPOctalState *s = IPOCTAL(dev); 541 unsigned i; 542 543 for (i = 0; i < N_CHANNELS; i++) { 544 SCC2698Channel *ch = &s->ch[i]; 545 ch->ipoctal = s; 546 547 /* Redirect IP-Octal channels to host character devices */ 548 if (qemu_chr_fe_backend_connected(&ch->dev)) { 549 qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive, 550 hostdev_receive, hostdev_event, 551 NULL, ch, NULL, true); 552 DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label); 553 } else { 554 DPRINTF("Could not redirect channel %u, no chardev set\n", i); 555 } 556 } 557 } 558 559 static Property ipoctal_properties[] = { 560 DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev), 561 DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev), 562 DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev), 563 DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev), 564 DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev), 565 DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev), 566 DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev), 567 DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev), 568 DEFINE_PROP_END_OF_LIST(), 569 }; 570 571 static void ipoctal_class_init(ObjectClass *klass, void *data) 572 { 573 DeviceClass *dc = DEVICE_CLASS(klass); 574 IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass); 575 576 ic->realize = ipoctal_realize; 577 ic->io_read = io_read; 578 ic->io_write = io_write; 579 ic->id_read = id_read; 580 ic->id_write = id_write; 581 ic->int_read = int_read; 582 ic->int_write = int_write; 583 ic->mem_read16 = mem_read16; 584 ic->mem_write16 = mem_write16; 585 ic->mem_read8 = mem_read8; 586 ic->mem_write8 = mem_write8; 587 588 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 589 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack"; 590 dc->props = ipoctal_properties; 591 dc->vmsd = &vmstate_ipoctal; 592 } 593 594 static const TypeInfo ipoctal_info = { 595 .name = TYPE_IPOCTAL, 596 .parent = TYPE_IPACK_DEVICE, 597 .instance_size = sizeof(IPOctalState), 598 .class_init = ipoctal_class_init, 599 }; 600 601 static void ipoctal_register_types(void) 602 { 603 type_register_static(&ipoctal_info); 604 } 605 606 type_init(ipoctal_register_types) 607