1 /* 2 * QEMU GE IP-Octal 232 IndustryPack emulation 3 * 4 * Copyright (C) 2012 Igalia, S.L. 5 * Author: Alberto Garcia <agarcia@igalia.com> 6 * 7 * This code is licensed under the GNU GPL v2 or (at your option) any 8 * later version. 9 */ 10 11 #include "hw/ipack/ipack.h" 12 #include "qemu/bitops.h" 13 #include "sysemu/char.h" 14 15 /* #define DEBUG_IPOCTAL */ 16 17 #ifdef DEBUG_IPOCTAL 18 #define DPRINTF2(fmt, ...) \ 19 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 20 #else 21 #define DPRINTF2(fmt, ...) do { } while (0) 22 #endif 23 24 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__) 25 26 #define RX_FIFO_SIZE 3 27 28 /* The IP-Octal has 8 channels (a-h) 29 divided into 4 blocks (A-D) */ 30 #define N_CHANNELS 8 31 #define N_BLOCKS 4 32 33 #define REG_MRa 0x01 34 #define REG_MRb 0x11 35 #define REG_SRa 0x03 36 #define REG_SRb 0x13 37 #define REG_CSRa 0x03 38 #define REG_CSRb 0x13 39 #define REG_CRa 0x05 40 #define REG_CRb 0x15 41 #define REG_RHRa 0x07 42 #define REG_RHRb 0x17 43 #define REG_THRa 0x07 44 #define REG_THRb 0x17 45 #define REG_ACR 0x09 46 #define REG_ISR 0x0B 47 #define REG_IMR 0x0B 48 #define REG_OPCR 0x1B 49 50 #define CR_ENABLE_RX BIT(0) 51 #define CR_DISABLE_RX BIT(1) 52 #define CR_ENABLE_TX BIT(2) 53 #define CR_DISABLE_TX BIT(3) 54 #define CR_CMD(cr) ((cr) >> 4) 55 #define CR_NO_OP 0 56 #define CR_RESET_MR 1 57 #define CR_RESET_RX 2 58 #define CR_RESET_TX 3 59 #define CR_RESET_ERR 4 60 #define CR_RESET_BRKINT 5 61 #define CR_START_BRK 6 62 #define CR_STOP_BRK 7 63 #define CR_ASSERT_RTSN 8 64 #define CR_NEGATE_RTSN 9 65 #define CR_TIMEOUT_ON 10 66 #define CR_TIMEOUT_OFF 12 67 68 #define SR_RXRDY BIT(0) 69 #define SR_FFULL BIT(1) 70 #define SR_TXRDY BIT(2) 71 #define SR_TXEMT BIT(3) 72 #define SR_OVERRUN BIT(4) 73 #define SR_PARITY BIT(5) 74 #define SR_FRAMING BIT(6) 75 #define SR_BREAK BIT(7) 76 77 #define ISR_TXRDYA BIT(0) 78 #define ISR_RXRDYA BIT(1) 79 #define ISR_BREAKA BIT(2) 80 #define ISR_CNTRDY BIT(3) 81 #define ISR_TXRDYB BIT(4) 82 #define ISR_RXRDYB BIT(5) 83 #define ISR_BREAKB BIT(6) 84 #define ISR_MPICHG BIT(7) 85 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0)) 86 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1)) 87 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2)) 88 89 typedef struct IPOctalState IPOctalState; 90 typedef struct SCC2698Channel SCC2698Channel; 91 typedef struct SCC2698Block SCC2698Block; 92 93 struct SCC2698Channel { 94 IPOctalState *ipoctal; 95 CharDriverState *dev; 96 bool rx_enabled; 97 uint8_t mr[2]; 98 uint8_t mr_idx; 99 uint8_t sr; 100 uint8_t rhr[RX_FIFO_SIZE]; 101 uint8_t rhr_idx; 102 uint8_t rx_pending; 103 }; 104 105 struct SCC2698Block { 106 uint8_t imr; 107 uint8_t isr; 108 }; 109 110 struct IPOctalState { 111 IPackDevice parent_obj; 112 113 SCC2698Channel ch[N_CHANNELS]; 114 SCC2698Block blk[N_BLOCKS]; 115 uint8_t irq_vector; 116 }; 117 118 #define TYPE_IPOCTAL "ipoctal232" 119 120 #define IPOCTAL(obj) \ 121 OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL) 122 123 static const VMStateDescription vmstate_scc2698_channel = { 124 .name = "scc2698_channel", 125 .version_id = 1, 126 .minimum_version_id = 1, 127 .fields = (VMStateField[]) { 128 VMSTATE_BOOL(rx_enabled, SCC2698Channel), 129 VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2), 130 VMSTATE_UINT8(mr_idx, SCC2698Channel), 131 VMSTATE_UINT8(sr, SCC2698Channel), 132 VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE), 133 VMSTATE_UINT8(rhr_idx, SCC2698Channel), 134 VMSTATE_UINT8(rx_pending, SCC2698Channel), 135 VMSTATE_END_OF_LIST() 136 } 137 }; 138 139 static const VMStateDescription vmstate_scc2698_block = { 140 .name = "scc2698_block", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT8(imr, SCC2698Block), 145 VMSTATE_UINT8(isr, SCC2698Block), 146 VMSTATE_END_OF_LIST() 147 } 148 }; 149 150 static const VMStateDescription vmstate_ipoctal = { 151 .name = "ipoctal232", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .fields = (VMStateField[]) { 155 VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState), 156 VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1, 157 vmstate_scc2698_channel, SCC2698Channel), 158 VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1, 159 vmstate_scc2698_block, SCC2698Block), 160 VMSTATE_UINT8(irq_vector, IPOctalState), 161 VMSTATE_END_OF_LIST() 162 } 163 }; 164 165 /* data[10] is 0x0C, not 0x0B as the doc says */ 166 static const uint8_t id_prom_data[] = { 167 0x49, 0x50, 0x41, 0x43, 0xF0, 0x22, 168 0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC 169 }; 170 171 static void update_irq(IPOctalState *dev, unsigned block) 172 { 173 IPackDevice *idev = IPACK_DEVICE(dev); 174 /* Blocks A and B interrupt on INT0#, C and D on INT1#. 175 Thus, to get the status we have to check two blocks. */ 176 SCC2698Block *blk0 = &dev->blk[block]; 177 SCC2698Block *blk1 = &dev->blk[block^1]; 178 unsigned intno = block / 2; 179 180 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { 181 qemu_irq_raise(idev->irq[intno]); 182 } else { 183 qemu_irq_lower(idev->irq[intno]); 184 } 185 } 186 187 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val) 188 { 189 SCC2698Channel *ch = &dev->ch[channel]; 190 SCC2698Block *blk = &dev->blk[channel / 2]; 191 192 DPRINTF("Write CR%c %u: ", channel + 'a', val); 193 194 /* The lower 4 bits are used to enable and disable Tx and Rx */ 195 if (val & CR_ENABLE_RX) { 196 DPRINTF2("Rx on, "); 197 ch->rx_enabled = true; 198 } 199 if (val & CR_DISABLE_RX) { 200 DPRINTF2("Rx off, "); 201 ch->rx_enabled = false; 202 } 203 if (val & CR_ENABLE_TX) { 204 DPRINTF2("Tx on, "); 205 ch->sr |= SR_TXRDY | SR_TXEMT; 206 blk->isr |= ISR_TXRDY(channel); 207 } 208 if (val & CR_DISABLE_TX) { 209 DPRINTF2("Tx off, "); 210 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 211 blk->isr &= ~ISR_TXRDY(channel); 212 } 213 214 DPRINTF2("cmd: "); 215 216 /* The rest of the bits implement different commands */ 217 switch (CR_CMD(val)) { 218 case CR_NO_OP: 219 DPRINTF2("none"); 220 break; 221 case CR_RESET_MR: 222 DPRINTF2("reset MR"); 223 ch->mr_idx = 0; 224 break; 225 case CR_RESET_RX: 226 DPRINTF2("reset Rx"); 227 ch->rx_enabled = false; 228 ch->rx_pending = 0; 229 ch->sr &= ~SR_RXRDY; 230 blk->isr &= ~ISR_RXRDY(channel); 231 break; 232 case CR_RESET_TX: 233 DPRINTF2("reset Tx"); 234 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 235 blk->isr &= ~ISR_TXRDY(channel); 236 break; 237 case CR_RESET_ERR: 238 DPRINTF2("reset err"); 239 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK); 240 break; 241 case CR_RESET_BRKINT: 242 DPRINTF2("reset brk ch int"); 243 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); 244 break; 245 default: 246 DPRINTF2("unsupported 0x%x", CR_CMD(val)); 247 } 248 249 DPRINTF2("\n"); 250 } 251 252 static uint16_t io_read(IPackDevice *ip, uint8_t addr) 253 { 254 IPOctalState *dev = IPOCTAL(ip); 255 uint16_t ret = 0; 256 /* addr[7:6]: block (A-D) 257 addr[7:5]: channel (a-h) 258 addr[5:0]: register */ 259 unsigned block = addr >> 5; 260 unsigned channel = addr >> 4; 261 /* Big endian, accessed using 8-bit bytes at odd locations */ 262 unsigned offset = (addr & 0x1F) ^ 1; 263 SCC2698Channel *ch = &dev->ch[channel]; 264 SCC2698Block *blk = &dev->blk[block]; 265 uint8_t old_isr = blk->isr; 266 267 switch (offset) { 268 269 case REG_MRa: 270 case REG_MRb: 271 ret = ch->mr[ch->mr_idx]; 272 DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret); 273 ch->mr_idx = 1; 274 break; 275 276 case REG_SRa: 277 case REG_SRb: 278 ret = ch->sr; 279 DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret); 280 break; 281 282 case REG_RHRa: 283 case REG_RHRb: 284 ret = ch->rhr[ch->rhr_idx]; 285 if (ch->rx_pending > 0) { 286 ch->rx_pending--; 287 if (ch->rx_pending == 0) { 288 ch->sr &= ~SR_RXRDY; 289 blk->isr &= ~ISR_RXRDY(channel); 290 if (ch->dev) { 291 qemu_chr_accept_input(ch->dev); 292 } 293 } else { 294 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE; 295 } 296 if (ch->sr & SR_BREAK) { 297 ch->sr &= ~SR_BREAK; 298 blk->isr |= ISR_BREAK(channel); 299 } 300 } 301 DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret); 302 break; 303 304 case REG_ISR: 305 ret = blk->isr; 306 DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret); 307 break; 308 309 default: 310 DPRINTF("Read unknown/unsupported register 0x%02x\n", offset); 311 } 312 313 if (old_isr != blk->isr) { 314 update_irq(dev, block); 315 } 316 317 return ret; 318 } 319 320 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val) 321 { 322 IPOctalState *dev = IPOCTAL(ip); 323 unsigned reg = val & 0xFF; 324 /* addr[7:6]: block (A-D) 325 addr[7:5]: channel (a-h) 326 addr[5:0]: register */ 327 unsigned block = addr >> 5; 328 unsigned channel = addr >> 4; 329 /* Big endian, accessed using 8-bit bytes at odd locations */ 330 unsigned offset = (addr & 0x1F) ^ 1; 331 SCC2698Channel *ch = &dev->ch[channel]; 332 SCC2698Block *blk = &dev->blk[block]; 333 uint8_t old_isr = blk->isr; 334 uint8_t old_imr = blk->imr; 335 336 switch (offset) { 337 338 case REG_MRa: 339 case REG_MRb: 340 ch->mr[ch->mr_idx] = reg; 341 DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg); 342 ch->mr_idx = 1; 343 break; 344 345 /* Not implemented */ 346 case REG_CSRa: 347 case REG_CSRb: 348 DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg); 349 break; 350 351 case REG_CRa: 352 case REG_CRb: 353 write_cr(dev, channel, reg); 354 break; 355 356 case REG_THRa: 357 case REG_THRb: 358 if (ch->sr & SR_TXRDY) { 359 DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg); 360 if (ch->dev) { 361 uint8_t thr = reg; 362 qemu_chr_fe_write(ch->dev, &thr, 1); 363 } 364 } else { 365 DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg); 366 } 367 break; 368 369 /* Not implemented */ 370 case REG_ACR: 371 DPRINTF("Write ACR%c 0x%x\n", block + 'A', val); 372 break; 373 374 case REG_IMR: 375 DPRINTF("Write IMR%c 0x%x\n", block + 'A', val); 376 blk->imr = reg; 377 break; 378 379 /* Not implemented */ 380 case REG_OPCR: 381 DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val); 382 break; 383 384 default: 385 DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val); 386 } 387 388 if (old_isr != blk->isr || old_imr != blk->imr) { 389 update_irq(dev, block); 390 } 391 } 392 393 static uint16_t id_read(IPackDevice *ip, uint8_t addr) 394 { 395 uint16_t ret = 0; 396 unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */ 397 398 if (pos < ARRAY_SIZE(id_prom_data)) { 399 ret = id_prom_data[pos]; 400 } else { 401 DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr); 402 } 403 404 return ret; 405 } 406 407 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val) 408 { 409 IPOctalState *dev = IPOCTAL(ip); 410 if (addr == 1) { 411 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 412 dev->irq_vector = val; /* Undocumented, but the hw works like that */ 413 } else { 414 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 415 } 416 } 417 418 static uint16_t int_read(IPackDevice *ip, uint8_t addr) 419 { 420 IPOctalState *dev = IPOCTAL(ip); 421 /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */ 422 if (addr != 0 && addr != 2) { 423 DPRINTF("Attempt to read from 0x%x\n", addr); 424 return 0; 425 } else { 426 /* Update interrupts if necessary */ 427 update_irq(dev, addr); 428 return dev->irq_vector; 429 } 430 } 431 432 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val) 433 { 434 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 435 } 436 437 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr) 438 { 439 DPRINTF("Attempt to read from 0x%x\n", addr); 440 return 0; 441 } 442 443 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val) 444 { 445 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 446 } 447 448 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr) 449 { 450 DPRINTF("Attempt to read from 0x%x\n", addr); 451 return 0; 452 } 453 454 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val) 455 { 456 IPOctalState *dev = IPOCTAL(ip); 457 if (addr == 1) { 458 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 459 dev->irq_vector = val; 460 } else { 461 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 462 } 463 } 464 465 static int hostdev_can_receive(void *opaque) 466 { 467 SCC2698Channel *ch = opaque; 468 int available_bytes = RX_FIFO_SIZE - ch->rx_pending; 469 return ch->rx_enabled ? available_bytes : 0; 470 } 471 472 static void hostdev_receive(void *opaque, const uint8_t *buf, int size) 473 { 474 SCC2698Channel *ch = opaque; 475 IPOctalState *dev = ch->ipoctal; 476 unsigned pos = ch->rhr_idx + ch->rx_pending; 477 int i; 478 479 assert(size + ch->rx_pending <= RX_FIFO_SIZE); 480 481 /* Copy data to the RxFIFO */ 482 for (i = 0; i < size; i++) { 483 pos %= RX_FIFO_SIZE; 484 ch->rhr[pos++] = buf[i]; 485 } 486 487 ch->rx_pending += size; 488 489 /* If the RxFIFO was empty raise an interrupt */ 490 if (!(ch->sr & SR_RXRDY)) { 491 unsigned block, channel = 0; 492 /* Find channel number to update the ISR register */ 493 while (&dev->ch[channel] != ch) { 494 channel++; 495 } 496 block = channel / 2; 497 dev->blk[block].isr |= ISR_RXRDY(channel); 498 ch->sr |= SR_RXRDY; 499 update_irq(dev, block); 500 } 501 } 502 503 static void hostdev_event(void *opaque, int event) 504 { 505 SCC2698Channel *ch = opaque; 506 switch (event) { 507 case CHR_EVENT_OPENED: 508 DPRINTF("Device %s opened\n", ch->dev->label); 509 break; 510 case CHR_EVENT_BREAK: { 511 uint8_t zero = 0; 512 DPRINTF("Device %s received break\n", ch->dev->label); 513 514 if (!(ch->sr & SR_BREAK)) { 515 IPOctalState *dev = ch->ipoctal; 516 unsigned block, channel = 0; 517 518 while (&dev->ch[channel] != ch) { 519 channel++; 520 } 521 block = channel / 2; 522 523 ch->sr |= SR_BREAK; 524 dev->blk[block].isr |= ISR_BREAK(channel); 525 } 526 527 /* Put a zero character in the buffer */ 528 hostdev_receive(ch, &zero, 1); 529 } 530 break; 531 default: 532 DPRINTF("Device %s received event %d\n", ch->dev->label, event); 533 } 534 } 535 536 static void ipoctal_realize(DeviceState *dev, Error **errp) 537 { 538 IPOctalState *s = IPOCTAL(dev); 539 unsigned i; 540 541 for (i = 0; i < N_CHANNELS; i++) { 542 SCC2698Channel *ch = &s->ch[i]; 543 ch->ipoctal = s; 544 545 /* Redirect IP-Octal channels to host character devices */ 546 if (ch->dev) { 547 qemu_chr_add_handlers(ch->dev, hostdev_can_receive, 548 hostdev_receive, hostdev_event, ch); 549 DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label); 550 } else { 551 DPRINTF("Could not redirect channel %u, no chardev set\n", i); 552 } 553 } 554 } 555 556 static Property ipoctal_properties[] = { 557 DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev), 558 DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev), 559 DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev), 560 DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev), 561 DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev), 562 DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev), 563 DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev), 564 DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev), 565 DEFINE_PROP_END_OF_LIST(), 566 }; 567 568 static void ipoctal_class_init(ObjectClass *klass, void *data) 569 { 570 DeviceClass *dc = DEVICE_CLASS(klass); 571 IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass); 572 573 ic->realize = ipoctal_realize; 574 ic->io_read = io_read; 575 ic->io_write = io_write; 576 ic->id_read = id_read; 577 ic->id_write = id_write; 578 ic->int_read = int_read; 579 ic->int_write = int_write; 580 ic->mem_read16 = mem_read16; 581 ic->mem_write16 = mem_write16; 582 ic->mem_read8 = mem_read8; 583 ic->mem_write8 = mem_write8; 584 585 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 586 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack"; 587 dc->props = ipoctal_properties; 588 dc->vmsd = &vmstate_ipoctal; 589 } 590 591 static const TypeInfo ipoctal_info = { 592 .name = TYPE_IPOCTAL, 593 .parent = TYPE_IPACK_DEVICE, 594 .instance_size = sizeof(IPOctalState), 595 .class_init = ipoctal_class_init, 596 }; 597 598 static void ipoctal_register_types(void) 599 { 600 type_register_static(&ipoctal_info); 601 } 602 603 type_init(ipoctal_register_types) 604