xref: /openbmc/qemu/hw/char/ipoctal232.c (revision 9c4218e9)
1 /*
2  * QEMU GE IP-Octal 232 IndustryPack emulation
3  *
4  * Copyright (C) 2012 Igalia, S.L.
5  * Author: Alberto Garcia <agarcia@igalia.com>
6  *
7  * This code is licensed under the GNU GPL v2 or (at your option) any
8  * later version.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "hw/ipack/ipack.h"
13 #include "qemu/bitops.h"
14 #include "sysemu/char.h"
15 
16 /* #define DEBUG_IPOCTAL */
17 
18 #ifdef DEBUG_IPOCTAL
19 #define DPRINTF2(fmt, ...) \
20     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
21 #else
22 #define DPRINTF2(fmt, ...) do { } while (0)
23 #endif
24 
25 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
26 
27 #define RX_FIFO_SIZE 3
28 
29 /* The IP-Octal has 8 channels (a-h)
30    divided into 4 blocks (A-D) */
31 #define N_CHANNELS 8
32 #define N_BLOCKS   4
33 
34 #define REG_MRa  0x01
35 #define REG_MRb  0x11
36 #define REG_SRa  0x03
37 #define REG_SRb  0x13
38 #define REG_CSRa 0x03
39 #define REG_CSRb 0x13
40 #define REG_CRa  0x05
41 #define REG_CRb  0x15
42 #define REG_RHRa 0x07
43 #define REG_RHRb 0x17
44 #define REG_THRa 0x07
45 #define REG_THRb 0x17
46 #define REG_ACR  0x09
47 #define REG_ISR  0x0B
48 #define REG_IMR  0x0B
49 #define REG_OPCR 0x1B
50 
51 #define CR_ENABLE_RX    BIT(0)
52 #define CR_DISABLE_RX   BIT(1)
53 #define CR_ENABLE_TX    BIT(2)
54 #define CR_DISABLE_TX   BIT(3)
55 #define CR_CMD(cr)      ((cr) >> 4)
56 #define CR_NO_OP        0
57 #define CR_RESET_MR     1
58 #define CR_RESET_RX     2
59 #define CR_RESET_TX     3
60 #define CR_RESET_ERR    4
61 #define CR_RESET_BRKINT 5
62 #define CR_START_BRK    6
63 #define CR_STOP_BRK     7
64 #define CR_ASSERT_RTSN  8
65 #define CR_NEGATE_RTSN  9
66 #define CR_TIMEOUT_ON   10
67 #define CR_TIMEOUT_OFF  12
68 
69 #define SR_RXRDY   BIT(0)
70 #define SR_FFULL   BIT(1)
71 #define SR_TXRDY   BIT(2)
72 #define SR_TXEMT   BIT(3)
73 #define SR_OVERRUN BIT(4)
74 #define SR_PARITY  BIT(5)
75 #define SR_FRAMING BIT(6)
76 #define SR_BREAK   BIT(7)
77 
78 #define ISR_TXRDYA BIT(0)
79 #define ISR_RXRDYA BIT(1)
80 #define ISR_BREAKA BIT(2)
81 #define ISR_CNTRDY BIT(3)
82 #define ISR_TXRDYB BIT(4)
83 #define ISR_RXRDYB BIT(5)
84 #define ISR_BREAKB BIT(6)
85 #define ISR_MPICHG BIT(7)
86 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
87 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
88 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
89 
90 typedef struct IPOctalState IPOctalState;
91 typedef struct SCC2698Channel SCC2698Channel;
92 typedef struct SCC2698Block SCC2698Block;
93 
94 struct SCC2698Channel {
95     IPOctalState *ipoctal;
96     CharDriverState *dev;
97     bool rx_enabled;
98     uint8_t mr[2];
99     uint8_t mr_idx;
100     uint8_t sr;
101     uint8_t rhr[RX_FIFO_SIZE];
102     uint8_t rhr_idx;
103     uint8_t rx_pending;
104 };
105 
106 struct SCC2698Block {
107     uint8_t imr;
108     uint8_t isr;
109 };
110 
111 struct IPOctalState {
112     IPackDevice parent_obj;
113 
114     SCC2698Channel ch[N_CHANNELS];
115     SCC2698Block blk[N_BLOCKS];
116     uint8_t irq_vector;
117 };
118 
119 #define TYPE_IPOCTAL "ipoctal232"
120 
121 #define IPOCTAL(obj) \
122     OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
123 
124 static const VMStateDescription vmstate_scc2698_channel = {
125     .name = "scc2698_channel",
126     .version_id = 1,
127     .minimum_version_id = 1,
128     .fields = (VMStateField[]) {
129         VMSTATE_BOOL(rx_enabled, SCC2698Channel),
130         VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
131         VMSTATE_UINT8(mr_idx, SCC2698Channel),
132         VMSTATE_UINT8(sr, SCC2698Channel),
133         VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
134         VMSTATE_UINT8(rhr_idx, SCC2698Channel),
135         VMSTATE_UINT8(rx_pending, SCC2698Channel),
136         VMSTATE_END_OF_LIST()
137     }
138 };
139 
140 static const VMStateDescription vmstate_scc2698_block = {
141     .name = "scc2698_block",
142     .version_id = 1,
143     .minimum_version_id = 1,
144     .fields = (VMStateField[]) {
145         VMSTATE_UINT8(imr, SCC2698Block),
146         VMSTATE_UINT8(isr, SCC2698Block),
147         VMSTATE_END_OF_LIST()
148     }
149 };
150 
151 static const VMStateDescription vmstate_ipoctal = {
152     .name = "ipoctal232",
153     .version_id = 1,
154     .minimum_version_id = 1,
155     .fields = (VMStateField[]) {
156         VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
157         VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
158                              vmstate_scc2698_channel, SCC2698Channel),
159         VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
160                              vmstate_scc2698_block, SCC2698Block),
161         VMSTATE_UINT8(irq_vector, IPOctalState),
162         VMSTATE_END_OF_LIST()
163     }
164 };
165 
166 /* data[10] is 0x0C, not 0x0B as the doc says */
167 static const uint8_t id_prom_data[] = {
168     0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
169     0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
170 };
171 
172 static void update_irq(IPOctalState *dev, unsigned block)
173 {
174     IPackDevice *idev = IPACK_DEVICE(dev);
175     /* Blocks A and B interrupt on INT0#, C and D on INT1#.
176        Thus, to get the status we have to check two blocks. */
177     SCC2698Block *blk0 = &dev->blk[block];
178     SCC2698Block *blk1 = &dev->blk[block^1];
179     unsigned intno = block / 2;
180 
181     if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
182         qemu_irq_raise(idev->irq[intno]);
183     } else {
184         qemu_irq_lower(idev->irq[intno]);
185     }
186 }
187 
188 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
189 {
190     SCC2698Channel *ch = &dev->ch[channel];
191     SCC2698Block *blk = &dev->blk[channel / 2];
192 
193     DPRINTF("Write CR%c %u: ", channel + 'a', val);
194 
195     /* The lower 4 bits are used to enable and disable Tx and Rx */
196     if (val & CR_ENABLE_RX) {
197         DPRINTF2("Rx on, ");
198         ch->rx_enabled = true;
199     }
200     if (val & CR_DISABLE_RX) {
201         DPRINTF2("Rx off, ");
202         ch->rx_enabled = false;
203     }
204     if (val & CR_ENABLE_TX) {
205         DPRINTF2("Tx on, ");
206         ch->sr |= SR_TXRDY | SR_TXEMT;
207         blk->isr |= ISR_TXRDY(channel);
208     }
209     if (val & CR_DISABLE_TX) {
210         DPRINTF2("Tx off, ");
211         ch->sr &= ~(SR_TXRDY | SR_TXEMT);
212         blk->isr &= ~ISR_TXRDY(channel);
213     }
214 
215     DPRINTF2("cmd: ");
216 
217     /* The rest of the bits implement different commands */
218     switch (CR_CMD(val)) {
219     case CR_NO_OP:
220         DPRINTF2("none");
221         break;
222     case CR_RESET_MR:
223         DPRINTF2("reset MR");
224         ch->mr_idx = 0;
225         break;
226     case CR_RESET_RX:
227         DPRINTF2("reset Rx");
228         ch->rx_enabled = false;
229         ch->rx_pending = 0;
230         ch->sr &= ~SR_RXRDY;
231         blk->isr &= ~ISR_RXRDY(channel);
232         break;
233     case CR_RESET_TX:
234         DPRINTF2("reset Tx");
235         ch->sr &= ~(SR_TXRDY | SR_TXEMT);
236         blk->isr &= ~ISR_TXRDY(channel);
237         break;
238     case CR_RESET_ERR:
239         DPRINTF2("reset err");
240         ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
241         break;
242     case CR_RESET_BRKINT:
243         DPRINTF2("reset brk ch int");
244         blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
245         break;
246     default:
247         DPRINTF2("unsupported 0x%x", CR_CMD(val));
248     }
249 
250     DPRINTF2("\n");
251 }
252 
253 static uint16_t io_read(IPackDevice *ip, uint8_t addr)
254 {
255     IPOctalState *dev = IPOCTAL(ip);
256     uint16_t ret = 0;
257     /* addr[7:6]: block   (A-D)
258        addr[7:5]: channel (a-h)
259        addr[5:0]: register */
260     unsigned block = addr >> 5;
261     unsigned channel = addr >> 4;
262     /* Big endian, accessed using 8-bit bytes at odd locations */
263     unsigned offset = (addr & 0x1F) ^ 1;
264     SCC2698Channel *ch = &dev->ch[channel];
265     SCC2698Block *blk = &dev->blk[block];
266     uint8_t old_isr = blk->isr;
267 
268     switch (offset) {
269 
270     case REG_MRa:
271     case REG_MRb:
272         ret = ch->mr[ch->mr_idx];
273         DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
274         ch->mr_idx = 1;
275         break;
276 
277     case REG_SRa:
278     case REG_SRb:
279         ret = ch->sr;
280         DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
281         break;
282 
283     case REG_RHRa:
284     case REG_RHRb:
285         ret = ch->rhr[ch->rhr_idx];
286         if (ch->rx_pending > 0) {
287             ch->rx_pending--;
288             if (ch->rx_pending == 0) {
289                 ch->sr &= ~SR_RXRDY;
290                 blk->isr &= ~ISR_RXRDY(channel);
291                 if (ch->dev) {
292                     qemu_chr_accept_input(ch->dev);
293                 }
294             } else {
295                 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
296             }
297             if (ch->sr & SR_BREAK) {
298                 ch->sr &= ~SR_BREAK;
299                 blk->isr |= ISR_BREAK(channel);
300             }
301         }
302         DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
303         break;
304 
305     case REG_ISR:
306         ret = blk->isr;
307         DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
308         break;
309 
310     default:
311         DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
312     }
313 
314     if (old_isr != blk->isr) {
315         update_irq(dev, block);
316     }
317 
318     return ret;
319 }
320 
321 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
322 {
323     IPOctalState *dev = IPOCTAL(ip);
324     unsigned reg = val & 0xFF;
325     /* addr[7:6]: block   (A-D)
326        addr[7:5]: channel (a-h)
327        addr[5:0]: register */
328     unsigned block = addr >> 5;
329     unsigned channel = addr >> 4;
330     /* Big endian, accessed using 8-bit bytes at odd locations */
331     unsigned offset = (addr & 0x1F) ^ 1;
332     SCC2698Channel *ch = &dev->ch[channel];
333     SCC2698Block *blk = &dev->blk[block];
334     uint8_t old_isr = blk->isr;
335     uint8_t old_imr = blk->imr;
336 
337     switch (offset) {
338 
339     case REG_MRa:
340     case REG_MRb:
341         ch->mr[ch->mr_idx] = reg;
342         DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
343         ch->mr_idx = 1;
344         break;
345 
346     /* Not implemented */
347     case REG_CSRa:
348     case REG_CSRb:
349         DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
350         break;
351 
352     case REG_CRa:
353     case REG_CRb:
354         write_cr(dev, channel, reg);
355         break;
356 
357     case REG_THRa:
358     case REG_THRb:
359         if (ch->sr & SR_TXRDY) {
360             DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
361             if (ch->dev) {
362                 uint8_t thr = reg;
363                 qemu_chr_fe_write(ch->dev, &thr, 1);
364             }
365         } else {
366             DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
367         }
368         break;
369 
370     /* Not implemented */
371     case REG_ACR:
372         DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
373         break;
374 
375     case REG_IMR:
376         DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
377         blk->imr = reg;
378         break;
379 
380     /* Not implemented */
381     case REG_OPCR:
382         DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
383         break;
384 
385     default:
386         DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
387     }
388 
389     if (old_isr != blk->isr || old_imr != blk->imr) {
390         update_irq(dev, block);
391     }
392 }
393 
394 static uint16_t id_read(IPackDevice *ip, uint8_t addr)
395 {
396     uint16_t ret = 0;
397     unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
398 
399     if (pos < ARRAY_SIZE(id_prom_data)) {
400         ret = id_prom_data[pos];
401     } else {
402         DPRINTF("Attempt to read unavailable PROM data at 0x%x\n",  addr);
403     }
404 
405     return ret;
406 }
407 
408 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
409 {
410     IPOctalState *dev = IPOCTAL(ip);
411     if (addr == 1) {
412         DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
413         dev->irq_vector = val; /* Undocumented, but the hw works like that */
414     } else {
415         DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
416     }
417 }
418 
419 static uint16_t int_read(IPackDevice *ip, uint8_t addr)
420 {
421     IPOctalState *dev = IPOCTAL(ip);
422     /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
423     if (addr != 0 && addr != 2) {
424         DPRINTF("Attempt to read from 0x%x\n", addr);
425         return 0;
426     } else {
427         /* Update interrupts if necessary */
428         update_irq(dev, addr);
429         return dev->irq_vector;
430     }
431 }
432 
433 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
434 {
435     DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
436 }
437 
438 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
439 {
440     DPRINTF("Attempt to read from 0x%x\n", addr);
441     return 0;
442 }
443 
444 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
445 {
446     DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
447 }
448 
449 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
450 {
451     DPRINTF("Attempt to read from 0x%x\n", addr);
452     return 0;
453 }
454 
455 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
456 {
457     IPOctalState *dev = IPOCTAL(ip);
458     if (addr == 1) {
459         DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
460         dev->irq_vector = val;
461     } else {
462         DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
463     }
464 }
465 
466 static int hostdev_can_receive(void *opaque)
467 {
468     SCC2698Channel *ch = opaque;
469     int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
470     return ch->rx_enabled ? available_bytes : 0;
471 }
472 
473 static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
474 {
475     SCC2698Channel *ch = opaque;
476     IPOctalState *dev = ch->ipoctal;
477     unsigned pos = ch->rhr_idx + ch->rx_pending;
478     int i;
479 
480     assert(size + ch->rx_pending <= RX_FIFO_SIZE);
481 
482     /* Copy data to the RxFIFO */
483     for (i = 0; i < size; i++) {
484         pos %= RX_FIFO_SIZE;
485         ch->rhr[pos++] = buf[i];
486     }
487 
488     ch->rx_pending += size;
489 
490     /* If the RxFIFO was empty raise an interrupt */
491     if (!(ch->sr & SR_RXRDY)) {
492         unsigned block, channel = 0;
493         /* Find channel number to update the ISR register */
494         while (&dev->ch[channel] != ch) {
495             channel++;
496         }
497         block = channel / 2;
498         dev->blk[block].isr |= ISR_RXRDY(channel);
499         ch->sr |= SR_RXRDY;
500         update_irq(dev, block);
501     }
502 }
503 
504 static void hostdev_event(void *opaque, int event)
505 {
506     SCC2698Channel *ch = opaque;
507     switch (event) {
508     case CHR_EVENT_OPENED:
509         DPRINTF("Device %s opened\n", ch->dev->label);
510         break;
511     case CHR_EVENT_BREAK: {
512         uint8_t zero = 0;
513         DPRINTF("Device %s received break\n", ch->dev->label);
514 
515         if (!(ch->sr & SR_BREAK)) {
516             IPOctalState *dev = ch->ipoctal;
517             unsigned block, channel = 0;
518 
519             while (&dev->ch[channel] != ch) {
520                 channel++;
521             }
522             block = channel / 2;
523 
524             ch->sr |= SR_BREAK;
525             dev->blk[block].isr |= ISR_BREAK(channel);
526         }
527 
528         /* Put a zero character in the buffer */
529         hostdev_receive(ch, &zero, 1);
530     }
531         break;
532     default:
533         DPRINTF("Device %s received event %d\n", ch->dev->label, event);
534     }
535 }
536 
537 static void ipoctal_realize(DeviceState *dev, Error **errp)
538 {
539     IPOctalState *s = IPOCTAL(dev);
540     unsigned i;
541 
542     for (i = 0; i < N_CHANNELS; i++) {
543         SCC2698Channel *ch = &s->ch[i];
544         ch->ipoctal = s;
545 
546         /* Redirect IP-Octal channels to host character devices */
547         if (ch->dev) {
548             qemu_chr_add_handlers(ch->dev, hostdev_can_receive,
549                                   hostdev_receive, hostdev_event, ch);
550             DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
551         } else {
552             DPRINTF("Could not redirect channel %u, no chardev set\n", i);
553         }
554     }
555 }
556 
557 static Property ipoctal_properties[] = {
558     DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
559     DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
560     DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
561     DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
562     DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
563     DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
564     DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
565     DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
566     DEFINE_PROP_END_OF_LIST(),
567 };
568 
569 static void ipoctal_class_init(ObjectClass *klass, void *data)
570 {
571     DeviceClass *dc = DEVICE_CLASS(klass);
572     IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
573 
574     ic->realize     = ipoctal_realize;
575     ic->io_read     = io_read;
576     ic->io_write    = io_write;
577     ic->id_read     = id_read;
578     ic->id_write    = id_write;
579     ic->int_read    = int_read;
580     ic->int_write   = int_write;
581     ic->mem_read16  = mem_read16;
582     ic->mem_write16 = mem_write16;
583     ic->mem_read8   = mem_read8;
584     ic->mem_write8  = mem_write8;
585 
586     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
587     dc->desc    = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
588     dc->props   = ipoctal_properties;
589     dc->vmsd    = &vmstate_ipoctal;
590 }
591 
592 static const TypeInfo ipoctal_info = {
593     .name          = TYPE_IPOCTAL,
594     .parent        = TYPE_IPACK_DEVICE,
595     .instance_size = sizeof(IPOctalState),
596     .class_init    = ipoctal_class_init,
597 };
598 
599 static void ipoctal_register_types(void)
600 {
601     type_register_static(&ipoctal_info);
602 }
603 
604 type_init(ipoctal_register_types)
605