1 /* 2 * QEMU GE IP-Octal 232 IndustryPack emulation 3 * 4 * Copyright (C) 2012 Igalia, S.L. 5 * Author: Alberto Garcia <berto@igalia.com> 6 * 7 * This code is licensed under the GNU GPL v2 or (at your option) any 8 * later version. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/ipack/ipack.h" 13 #include "hw/irq.h" 14 #include "hw/qdev-properties.h" 15 #include "migration/vmstate.h" 16 #include "qemu/bitops.h" 17 #include "qemu/module.h" 18 #include "chardev/char-fe.h" 19 #include "qom/object.h" 20 21 /* #define DEBUG_IPOCTAL */ 22 23 #ifdef DEBUG_IPOCTAL 24 #define DPRINTF2(fmt, ...) \ 25 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 26 #else 27 #define DPRINTF2(fmt, ...) do { } while (0) 28 #endif 29 30 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__) 31 32 #define RX_FIFO_SIZE 3 33 34 /* The IP-Octal has 8 channels (a-h) 35 divided into 4 blocks (A-D) */ 36 #define N_CHANNELS 8 37 #define N_BLOCKS 4 38 39 #define REG_MRa 0x01 40 #define REG_MRb 0x11 41 #define REG_SRa 0x03 42 #define REG_SRb 0x13 43 #define REG_CSRa 0x03 44 #define REG_CSRb 0x13 45 #define REG_CRa 0x05 46 #define REG_CRb 0x15 47 #define REG_RHRa 0x07 48 #define REG_RHRb 0x17 49 #define REG_THRa 0x07 50 #define REG_THRb 0x17 51 #define REG_ACR 0x09 52 #define REG_ISR 0x0B 53 #define REG_IMR 0x0B 54 #define REG_OPCR 0x1B 55 56 #define CR_ENABLE_RX BIT(0) 57 #define CR_DISABLE_RX BIT(1) 58 #define CR_ENABLE_TX BIT(2) 59 #define CR_DISABLE_TX BIT(3) 60 #define CR_CMD(cr) ((cr) >> 4) 61 #define CR_NO_OP 0 62 #define CR_RESET_MR 1 63 #define CR_RESET_RX 2 64 #define CR_RESET_TX 3 65 #define CR_RESET_ERR 4 66 #define CR_RESET_BRKINT 5 67 #define CR_START_BRK 6 68 #define CR_STOP_BRK 7 69 #define CR_ASSERT_RTSN 8 70 #define CR_NEGATE_RTSN 9 71 #define CR_TIMEOUT_ON 10 72 #define CR_TIMEOUT_OFF 12 73 74 #define SR_RXRDY BIT(0) 75 #define SR_FFULL BIT(1) 76 #define SR_TXRDY BIT(2) 77 #define SR_TXEMT BIT(3) 78 #define SR_OVERRUN BIT(4) 79 #define SR_PARITY BIT(5) 80 #define SR_FRAMING BIT(6) 81 #define SR_BREAK BIT(7) 82 83 #define ISR_TXRDYA BIT(0) 84 #define ISR_RXRDYA BIT(1) 85 #define ISR_BREAKA BIT(2) 86 #define ISR_CNTRDY BIT(3) 87 #define ISR_TXRDYB BIT(4) 88 #define ISR_RXRDYB BIT(5) 89 #define ISR_BREAKB BIT(6) 90 #define ISR_MPICHG BIT(7) 91 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0)) 92 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1)) 93 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2)) 94 95 typedef struct IPOctalState IPOctalState; 96 typedef struct SCC2698Channel SCC2698Channel; 97 typedef struct SCC2698Block SCC2698Block; 98 99 struct SCC2698Channel { 100 IPOctalState *ipoctal; 101 CharBackend dev; 102 bool rx_enabled; 103 uint8_t mr[2]; 104 uint8_t mr_idx; 105 uint8_t sr; 106 uint8_t rhr[RX_FIFO_SIZE]; 107 uint8_t rhr_idx; 108 uint8_t rx_pending; 109 }; 110 111 struct SCC2698Block { 112 uint8_t imr; 113 uint8_t isr; 114 }; 115 116 struct IPOctalState { 117 IPackDevice parent_obj; 118 119 SCC2698Channel ch[N_CHANNELS]; 120 SCC2698Block blk[N_BLOCKS]; 121 uint8_t irq_vector; 122 }; 123 124 #define TYPE_IPOCTAL "ipoctal232" 125 126 OBJECT_DECLARE_SIMPLE_TYPE(IPOctalState, IPOCTAL) 127 128 static const VMStateDescription vmstate_scc2698_channel = { 129 .name = "scc2698_channel", 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .fields = (VMStateField[]) { 133 VMSTATE_BOOL(rx_enabled, SCC2698Channel), 134 VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2), 135 VMSTATE_UINT8(mr_idx, SCC2698Channel), 136 VMSTATE_UINT8(sr, SCC2698Channel), 137 VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE), 138 VMSTATE_UINT8(rhr_idx, SCC2698Channel), 139 VMSTATE_UINT8(rx_pending, SCC2698Channel), 140 VMSTATE_END_OF_LIST() 141 } 142 }; 143 144 static const VMStateDescription vmstate_scc2698_block = { 145 .name = "scc2698_block", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .fields = (VMStateField[]) { 149 VMSTATE_UINT8(imr, SCC2698Block), 150 VMSTATE_UINT8(isr, SCC2698Block), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 static const VMStateDescription vmstate_ipoctal = { 156 .name = "ipoctal232", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .fields = (VMStateField[]) { 160 VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState), 161 VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1, 162 vmstate_scc2698_channel, SCC2698Channel), 163 VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1, 164 vmstate_scc2698_block, SCC2698Block), 165 VMSTATE_UINT8(irq_vector, IPOctalState), 166 VMSTATE_END_OF_LIST() 167 } 168 }; 169 170 /* data[10] is 0x0C, not 0x0B as the doc says */ 171 static const uint8_t id_prom_data[] = { 172 0x49, 0x50, 0x41, 0x43, 0xF0, 0x22, 173 0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC 174 }; 175 176 static void update_irq(IPOctalState *dev, unsigned block) 177 { 178 IPackDevice *idev = IPACK_DEVICE(dev); 179 /* Blocks A and B interrupt on INT0#, C and D on INT1#. 180 Thus, to get the status we have to check two blocks. */ 181 SCC2698Block *blk0 = &dev->blk[block]; 182 SCC2698Block *blk1 = &dev->blk[block^1]; 183 unsigned intno = block / 2; 184 185 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { 186 qemu_irq_raise(idev->irq[intno]); 187 } else { 188 qemu_irq_lower(idev->irq[intno]); 189 } 190 } 191 192 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val) 193 { 194 SCC2698Channel *ch = &dev->ch[channel]; 195 SCC2698Block *blk = &dev->blk[channel / 2]; 196 197 DPRINTF("Write CR%c %u: ", channel + 'a', val); 198 199 /* The lower 4 bits are used to enable and disable Tx and Rx */ 200 if (val & CR_ENABLE_RX) { 201 DPRINTF2("Rx on, "); 202 ch->rx_enabled = true; 203 } 204 if (val & CR_DISABLE_RX) { 205 DPRINTF2("Rx off, "); 206 ch->rx_enabled = false; 207 } 208 if (val & CR_ENABLE_TX) { 209 DPRINTF2("Tx on, "); 210 ch->sr |= SR_TXRDY | SR_TXEMT; 211 blk->isr |= ISR_TXRDY(channel); 212 } 213 if (val & CR_DISABLE_TX) { 214 DPRINTF2("Tx off, "); 215 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 216 blk->isr &= ~ISR_TXRDY(channel); 217 } 218 219 DPRINTF2("cmd: "); 220 221 /* The rest of the bits implement different commands */ 222 switch (CR_CMD(val)) { 223 case CR_NO_OP: 224 DPRINTF2("none"); 225 break; 226 case CR_RESET_MR: 227 DPRINTF2("reset MR"); 228 ch->mr_idx = 0; 229 break; 230 case CR_RESET_RX: 231 DPRINTF2("reset Rx"); 232 ch->rx_enabled = false; 233 ch->rx_pending = 0; 234 ch->sr &= ~SR_RXRDY; 235 blk->isr &= ~ISR_RXRDY(channel); 236 break; 237 case CR_RESET_TX: 238 DPRINTF2("reset Tx"); 239 ch->sr &= ~(SR_TXRDY | SR_TXEMT); 240 blk->isr &= ~ISR_TXRDY(channel); 241 break; 242 case CR_RESET_ERR: 243 DPRINTF2("reset err"); 244 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK); 245 break; 246 case CR_RESET_BRKINT: 247 DPRINTF2("reset brk ch int"); 248 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); 249 break; 250 default: 251 DPRINTF2("unsupported 0x%x", CR_CMD(val)); 252 } 253 254 DPRINTF2("\n"); 255 } 256 257 static uint16_t io_read(IPackDevice *ip, uint8_t addr) 258 { 259 IPOctalState *dev = IPOCTAL(ip); 260 uint16_t ret = 0; 261 /* addr[7:6]: block (A-D) 262 addr[7:5]: channel (a-h) 263 addr[5:0]: register */ 264 unsigned block = addr >> 5; 265 unsigned channel = addr >> 4; 266 /* Big endian, accessed using 8-bit bytes at odd locations */ 267 unsigned offset = (addr & 0x1F) ^ 1; 268 SCC2698Channel *ch = &dev->ch[channel]; 269 SCC2698Block *blk = &dev->blk[block]; 270 uint8_t old_isr = blk->isr; 271 272 switch (offset) { 273 274 case REG_MRa: 275 case REG_MRb: 276 ret = ch->mr[ch->mr_idx]; 277 DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret); 278 ch->mr_idx = 1; 279 break; 280 281 case REG_SRa: 282 case REG_SRb: 283 ret = ch->sr; 284 DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret); 285 break; 286 287 case REG_RHRa: 288 case REG_RHRb: 289 ret = ch->rhr[ch->rhr_idx]; 290 if (ch->rx_pending > 0) { 291 ch->rx_pending--; 292 if (ch->rx_pending == 0) { 293 ch->sr &= ~SR_RXRDY; 294 blk->isr &= ~ISR_RXRDY(channel); 295 qemu_chr_fe_accept_input(&ch->dev); 296 } else { 297 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE; 298 } 299 if (ch->sr & SR_BREAK) { 300 ch->sr &= ~SR_BREAK; 301 blk->isr |= ISR_BREAK(channel); 302 } 303 } 304 DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret); 305 break; 306 307 case REG_ISR: 308 ret = blk->isr; 309 DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret); 310 break; 311 312 default: 313 DPRINTF("Read unknown/unsupported register 0x%02x\n", offset); 314 } 315 316 if (old_isr != blk->isr) { 317 update_irq(dev, block); 318 } 319 320 return ret; 321 } 322 323 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val) 324 { 325 IPOctalState *dev = IPOCTAL(ip); 326 unsigned reg = val & 0xFF; 327 /* addr[7:6]: block (A-D) 328 addr[7:5]: channel (a-h) 329 addr[5:0]: register */ 330 unsigned block = addr >> 5; 331 unsigned channel = addr >> 4; 332 /* Big endian, accessed using 8-bit bytes at odd locations */ 333 unsigned offset = (addr & 0x1F) ^ 1; 334 SCC2698Channel *ch = &dev->ch[channel]; 335 SCC2698Block *blk = &dev->blk[block]; 336 uint8_t old_isr = blk->isr; 337 uint8_t old_imr = blk->imr; 338 339 switch (offset) { 340 341 case REG_MRa: 342 case REG_MRb: 343 ch->mr[ch->mr_idx] = reg; 344 DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg); 345 ch->mr_idx = 1; 346 break; 347 348 /* Not implemented */ 349 case REG_CSRa: 350 case REG_CSRb: 351 DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg); 352 break; 353 354 case REG_CRa: 355 case REG_CRb: 356 write_cr(dev, channel, reg); 357 break; 358 359 case REG_THRa: 360 case REG_THRb: 361 if (ch->sr & SR_TXRDY) { 362 uint8_t thr = reg; 363 DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg); 364 /* XXX this blocks entire thread. Rewrite to use 365 * qemu_chr_fe_write and background I/O callbacks */ 366 qemu_chr_fe_write_all(&ch->dev, &thr, 1); 367 } else { 368 DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg); 369 } 370 break; 371 372 /* Not implemented */ 373 case REG_ACR: 374 DPRINTF("Write ACR%c 0x%x\n", block + 'A', val); 375 break; 376 377 case REG_IMR: 378 DPRINTF("Write IMR%c 0x%x\n", block + 'A', val); 379 blk->imr = reg; 380 break; 381 382 /* Not implemented */ 383 case REG_OPCR: 384 DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val); 385 break; 386 387 default: 388 DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val); 389 } 390 391 if (old_isr != blk->isr || old_imr != blk->imr) { 392 update_irq(dev, block); 393 } 394 } 395 396 static uint16_t id_read(IPackDevice *ip, uint8_t addr) 397 { 398 uint16_t ret = 0; 399 unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */ 400 401 if (pos < ARRAY_SIZE(id_prom_data)) { 402 ret = id_prom_data[pos]; 403 } else { 404 DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr); 405 } 406 407 return ret; 408 } 409 410 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val) 411 { 412 IPOctalState *dev = IPOCTAL(ip); 413 if (addr == 1) { 414 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 415 dev->irq_vector = val; /* Undocumented, but the hw works like that */ 416 } else { 417 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 418 } 419 } 420 421 static uint16_t int_read(IPackDevice *ip, uint8_t addr) 422 { 423 IPOctalState *dev = IPOCTAL(ip); 424 /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */ 425 if (addr != 0 && addr != 2) { 426 DPRINTF("Attempt to read from 0x%x\n", addr); 427 return 0; 428 } else { 429 /* Update interrupts if necessary */ 430 update_irq(dev, addr); 431 return dev->irq_vector; 432 } 433 } 434 435 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val) 436 { 437 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 438 } 439 440 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr) 441 { 442 DPRINTF("Attempt to read from 0x%x\n", addr); 443 return 0; 444 } 445 446 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val) 447 { 448 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 449 } 450 451 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr) 452 { 453 DPRINTF("Attempt to read from 0x%x\n", addr); 454 return 0; 455 } 456 457 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val) 458 { 459 IPOctalState *dev = IPOCTAL(ip); 460 if (addr == 1) { 461 DPRINTF("Write IRQ vector: %u\n", (unsigned) val); 462 dev->irq_vector = val; 463 } else { 464 DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr); 465 } 466 } 467 468 static int hostdev_can_receive(void *opaque) 469 { 470 SCC2698Channel *ch = opaque; 471 int available_bytes = RX_FIFO_SIZE - ch->rx_pending; 472 return ch->rx_enabled ? available_bytes : 0; 473 } 474 475 static void hostdev_receive(void *opaque, const uint8_t *buf, int size) 476 { 477 SCC2698Channel *ch = opaque; 478 IPOctalState *dev = ch->ipoctal; 479 unsigned pos = ch->rhr_idx + ch->rx_pending; 480 int i; 481 482 assert(size + ch->rx_pending <= RX_FIFO_SIZE); 483 484 /* Copy data to the RxFIFO */ 485 for (i = 0; i < size; i++) { 486 pos %= RX_FIFO_SIZE; 487 ch->rhr[pos++] = buf[i]; 488 } 489 490 ch->rx_pending += size; 491 492 /* If the RxFIFO was empty raise an interrupt */ 493 if (!(ch->sr & SR_RXRDY)) { 494 unsigned block, channel = 0; 495 /* Find channel number to update the ISR register */ 496 while (&dev->ch[channel] != ch) { 497 channel++; 498 } 499 block = channel / 2; 500 dev->blk[block].isr |= ISR_RXRDY(channel); 501 ch->sr |= SR_RXRDY; 502 update_irq(dev, block); 503 } 504 } 505 506 static void hostdev_event(void *opaque, QEMUChrEvent event) 507 { 508 SCC2698Channel *ch = opaque; 509 switch (event) { 510 case CHR_EVENT_OPENED: 511 DPRINTF("Device %s opened\n", ch->dev->label); 512 break; 513 case CHR_EVENT_BREAK: { 514 uint8_t zero = 0; 515 DPRINTF("Device %s received break\n", ch->dev->label); 516 517 if (!(ch->sr & SR_BREAK)) { 518 IPOctalState *dev = ch->ipoctal; 519 unsigned block, channel = 0; 520 521 while (&dev->ch[channel] != ch) { 522 channel++; 523 } 524 block = channel / 2; 525 526 ch->sr |= SR_BREAK; 527 dev->blk[block].isr |= ISR_BREAK(channel); 528 } 529 530 /* Put a zero character in the buffer */ 531 hostdev_receive(ch, &zero, 1); 532 } 533 break; 534 default: 535 DPRINTF("Device %s received event %d\n", ch->dev->label, event); 536 } 537 } 538 539 static void ipoctal_realize(DeviceState *dev, Error **errp) 540 { 541 IPOctalState *s = IPOCTAL(dev); 542 unsigned i; 543 544 for (i = 0; i < N_CHANNELS; i++) { 545 SCC2698Channel *ch = &s->ch[i]; 546 ch->ipoctal = s; 547 548 /* Redirect IP-Octal channels to host character devices */ 549 if (qemu_chr_fe_backend_connected(&ch->dev)) { 550 qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive, 551 hostdev_receive, hostdev_event, 552 NULL, ch, NULL, true); 553 DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label); 554 } else { 555 DPRINTF("Could not redirect channel %u, no chardev set\n", i); 556 } 557 } 558 } 559 560 static Property ipoctal_properties[] = { 561 DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev), 562 DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev), 563 DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev), 564 DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev), 565 DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev), 566 DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev), 567 DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev), 568 DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev), 569 DEFINE_PROP_END_OF_LIST(), 570 }; 571 572 static void ipoctal_class_init(ObjectClass *klass, void *data) 573 { 574 DeviceClass *dc = DEVICE_CLASS(klass); 575 IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass); 576 577 ic->realize = ipoctal_realize; 578 ic->io_read = io_read; 579 ic->io_write = io_write; 580 ic->id_read = id_read; 581 ic->id_write = id_write; 582 ic->int_read = int_read; 583 ic->int_write = int_write; 584 ic->mem_read16 = mem_read16; 585 ic->mem_write16 = mem_write16; 586 ic->mem_read8 = mem_read8; 587 ic->mem_write8 = mem_write8; 588 589 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 590 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack"; 591 device_class_set_props(dc, ipoctal_properties); 592 dc->vmsd = &vmstate_ipoctal; 593 } 594 595 static const TypeInfo ipoctal_info = { 596 .name = TYPE_IPOCTAL, 597 .parent = TYPE_IPACK_DEVICE, 598 .instance_size = sizeof(IPOctalState), 599 .class_init = ipoctal_class_init, 600 }; 601 602 static void ipoctal_register_types(void) 603 { 604 type_register_static(&ipoctal_info); 605 } 606 607 type_init(ipoctal_register_types) 608