1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/char.h" 25 #include "qemu/log.h" 26 27 #ifndef DEBUG_IMX_UART 28 #define DEBUG_IMX_UART 0 29 #endif 30 31 #define DPRINTF(fmt, args...) \ 32 do { \ 33 if (DEBUG_IMX_UART) { \ 34 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 35 __func__, ##args); \ 36 } \ 37 } while (0) 38 39 static const VMStateDescription vmstate_imx_serial = { 40 .name = TYPE_IMX_SERIAL, 41 .version_id = 1, 42 .minimum_version_id = 1, 43 .fields = (VMStateField[]) { 44 VMSTATE_INT32(readbuff, IMXSerialState), 45 VMSTATE_UINT32(usr1, IMXSerialState), 46 VMSTATE_UINT32(usr2, IMXSerialState), 47 VMSTATE_UINT32(ucr1, IMXSerialState), 48 VMSTATE_UINT32(uts1, IMXSerialState), 49 VMSTATE_UINT32(onems, IMXSerialState), 50 VMSTATE_UINT32(ufcr, IMXSerialState), 51 VMSTATE_UINT32(ubmr, IMXSerialState), 52 VMSTATE_UINT32(ubrc, IMXSerialState), 53 VMSTATE_UINT32(ucr3, IMXSerialState), 54 VMSTATE_END_OF_LIST() 55 }, 56 }; 57 58 static void imx_update(IMXSerialState *s) 59 { 60 uint32_t flags; 61 62 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 63 if (s->ucr1 & UCR1_TXMPTYEN) { 64 flags |= (s->uts1 & UTS1_TXEMPTY); 65 } else { 66 flags &= ~USR1_TRDY; 67 } 68 69 qemu_set_irq(s->irq, !!flags); 70 } 71 72 static void imx_serial_reset(IMXSerialState *s) 73 { 74 75 s->usr1 = USR1_TRDY | USR1_RXDS; 76 /* 77 * Fake attachment of a terminal: assert RTS. 78 */ 79 s->usr1 |= USR1_RTSS; 80 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 81 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 82 s->ucr1 = 0; 83 s->ucr2 = UCR2_SRST; 84 s->ucr3 = 0x700; 85 s->ubmr = 0; 86 s->ubrc = 4; 87 s->readbuff = URXD_ERR; 88 } 89 90 static void imx_serial_reset_at_boot(DeviceState *dev) 91 { 92 IMXSerialState *s = IMX_SERIAL(dev); 93 94 imx_serial_reset(s); 95 96 /* 97 * enable the uart on boot, so messages from the linux decompresser 98 * are visible. On real hardware this is done by the boot rom 99 * before anything else is loaded. 100 */ 101 s->ucr1 = UCR1_UARTEN; 102 s->ucr2 = UCR2_TXEN; 103 104 } 105 106 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 107 unsigned size) 108 { 109 IMXSerialState *s = (IMXSerialState *)opaque; 110 uint32_t c; 111 112 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 113 114 switch (offset >> 2) { 115 case 0x0: /* URXD */ 116 c = s->readbuff; 117 if (!(s->uts1 & UTS1_RXEMPTY)) { 118 /* Character is valid */ 119 c |= URXD_CHARRDY; 120 s->usr1 &= ~USR1_RRDY; 121 s->usr2 &= ~USR2_RDR; 122 s->uts1 |= UTS1_RXEMPTY; 123 imx_update(s); 124 if (s->chr) { 125 qemu_chr_accept_input(s->chr); 126 } 127 } 128 return c; 129 130 case 0x20: /* UCR1 */ 131 return s->ucr1; 132 133 case 0x21: /* UCR2 */ 134 return s->ucr2; 135 136 case 0x25: /* USR1 */ 137 return s->usr1; 138 139 case 0x26: /* USR2 */ 140 return s->usr2; 141 142 case 0x2A: /* BRM Modulator */ 143 return s->ubmr; 144 145 case 0x2B: /* Baud Rate Count */ 146 return s->ubrc; 147 148 case 0x2d: /* Test register */ 149 return s->uts1; 150 151 case 0x24: /* UFCR */ 152 return s->ufcr; 153 154 case 0x2c: 155 return s->onems; 156 157 case 0x22: /* UCR3 */ 158 return s->ucr3; 159 160 case 0x23: /* UCR4 */ 161 case 0x29: /* BRM Incremental */ 162 return 0x0; /* TODO */ 163 164 default: 165 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 166 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 167 return 0; 168 } 169 } 170 171 static void imx_serial_write(void *opaque, hwaddr offset, 172 uint64_t value, unsigned size) 173 { 174 IMXSerialState *s = (IMXSerialState *)opaque; 175 unsigned char ch; 176 177 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 178 offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV"); 179 180 switch (offset >> 2) { 181 case 0x10: /* UTXD */ 182 ch = value; 183 if (s->ucr2 & UCR2_TXEN) { 184 if (s->chr) { 185 /* XXX this blocks entire thread. Rewrite to use 186 * qemu_chr_fe_write and background I/O callbacks */ 187 qemu_chr_fe_write_all(s->chr, &ch, 1); 188 } 189 s->usr1 &= ~USR1_TRDY; 190 imx_update(s); 191 s->usr1 |= USR1_TRDY; 192 imx_update(s); 193 } 194 break; 195 196 case 0x20: /* UCR1 */ 197 s->ucr1 = value & 0xffff; 198 199 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 200 201 imx_update(s); 202 break; 203 204 case 0x21: /* UCR2 */ 205 /* 206 * Only a few bits in control register 2 are implemented as yet. 207 * If it's intended to use a real serial device as a back-end, this 208 * register will have to be implemented more fully. 209 */ 210 if (!(value & UCR2_SRST)) { 211 imx_serial_reset(s); 212 imx_update(s); 213 value |= UCR2_SRST; 214 } 215 if (value & UCR2_RXEN) { 216 if (!(s->ucr2 & UCR2_RXEN)) { 217 if (s->chr) { 218 qemu_chr_accept_input(s->chr); 219 } 220 } 221 } 222 s->ucr2 = value & 0xffff; 223 break; 224 225 case 0x25: /* USR1 */ 226 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 227 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 228 s->usr1 &= ~value; 229 break; 230 231 case 0x26: /* USR2 */ 232 /* 233 * Writing 1 to some bits clears them; all other 234 * values are ignored 235 */ 236 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 237 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 238 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 239 s->usr2 &= ~value; 240 break; 241 242 /* 243 * Linux expects to see what it writes to these registers 244 * We don't currently alter the baud rate 245 */ 246 case 0x29: /* UBIR */ 247 s->ubrc = value & 0xffff; 248 break; 249 250 case 0x2a: /* UBMR */ 251 s->ubmr = value & 0xffff; 252 break; 253 254 case 0x2c: /* One ms reg */ 255 s->onems = value & 0xffff; 256 break; 257 258 case 0x24: /* FIFO control register */ 259 s->ufcr = value & 0xffff; 260 break; 261 262 case 0x22: /* UCR3 */ 263 s->ucr3 = value & 0xffff; 264 break; 265 266 case 0x2d: /* UTS1 */ 267 case 0x23: /* UCR4 */ 268 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 269 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 270 /* TODO */ 271 break; 272 273 default: 274 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 275 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 276 } 277 } 278 279 static int imx_can_receive(void *opaque) 280 { 281 IMXSerialState *s = (IMXSerialState *)opaque; 282 return !(s->usr1 & USR1_RRDY); 283 } 284 285 static void imx_put_data(void *opaque, uint32_t value) 286 { 287 IMXSerialState *s = (IMXSerialState *)opaque; 288 289 DPRINTF("received char\n"); 290 291 s->usr1 |= USR1_RRDY; 292 s->usr2 |= USR2_RDR; 293 s->uts1 &= ~UTS1_RXEMPTY; 294 s->readbuff = value; 295 imx_update(s); 296 } 297 298 static void imx_receive(void *opaque, const uint8_t *buf, int size) 299 { 300 imx_put_data(opaque, *buf); 301 } 302 303 static void imx_event(void *opaque, int event) 304 { 305 if (event == CHR_EVENT_BREAK) { 306 imx_put_data(opaque, URXD_BRK); 307 } 308 } 309 310 311 static const struct MemoryRegionOps imx_serial_ops = { 312 .read = imx_serial_read, 313 .write = imx_serial_write, 314 .endianness = DEVICE_NATIVE_ENDIAN, 315 }; 316 317 static void imx_serial_realize(DeviceState *dev, Error **errp) 318 { 319 IMXSerialState *s = IMX_SERIAL(dev); 320 321 if (s->chr) { 322 qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, 323 imx_event, s); 324 } else { 325 DPRINTF("No char dev for uart\n"); 326 } 327 } 328 329 static void imx_serial_init(Object *obj) 330 { 331 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 332 IMXSerialState *s = IMX_SERIAL(obj); 333 334 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 335 TYPE_IMX_SERIAL, 0x1000); 336 sysbus_init_mmio(sbd, &s->iomem); 337 sysbus_init_irq(sbd, &s->irq); 338 } 339 340 static Property imx_serial_properties[] = { 341 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 342 DEFINE_PROP_END_OF_LIST(), 343 }; 344 345 static void imx_serial_class_init(ObjectClass *klass, void *data) 346 { 347 DeviceClass *dc = DEVICE_CLASS(klass); 348 349 dc->realize = imx_serial_realize; 350 dc->vmsd = &vmstate_imx_serial; 351 dc->reset = imx_serial_reset_at_boot; 352 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 353 dc->desc = "i.MX series UART"; 354 dc->props = imx_serial_properties; 355 } 356 357 static const TypeInfo imx_serial_info = { 358 .name = TYPE_IMX_SERIAL, 359 .parent = TYPE_SYS_BUS_DEVICE, 360 .instance_size = sizeof(IMXSerialState), 361 .instance_init = imx_serial_init, 362 .class_init = imx_serial_class_init, 363 }; 364 365 static void imx_serial_register_types(void) 366 { 367 type_register_static(&imx_serial_info); 368 } 369 370 type_init(imx_serial_register_types) 371