1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "hw/char/imx_serial.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/char.h" 24 #include "hw/arm/imx.h" 25 26 //#define DEBUG_SERIAL 1 27 #ifdef DEBUG_SERIAL 28 #define DPRINTF(fmt, args...) \ 29 do { printf("%s: " fmt , TYPE_IMX_SERIAL, ##args); } while (0) 30 #else 31 #define DPRINTF(fmt, args...) do {} while (0) 32 #endif 33 34 /* 35 * Define to 1 for messages about attempts to 36 * access unimplemented registers or similar. 37 */ 38 //#define DEBUG_IMPLEMENTATION 1 39 #ifdef DEBUG_IMPLEMENTATION 40 # define IPRINTF(fmt, args...) \ 41 do { fprintf(stderr, "%s: " fmt, TYPE_IMX_SERIAL, ##args); } while (0) 42 #else 43 # define IPRINTF(fmt, args...) do {} while (0) 44 #endif 45 46 static const VMStateDescription vmstate_imx_serial = { 47 .name = TYPE_IMX_SERIAL, 48 .version_id = 1, 49 .minimum_version_id = 1, 50 .fields = (VMStateField[]) { 51 VMSTATE_INT32(readbuff, IMXSerialState), 52 VMSTATE_UINT32(usr1, IMXSerialState), 53 VMSTATE_UINT32(usr2, IMXSerialState), 54 VMSTATE_UINT32(ucr1, IMXSerialState), 55 VMSTATE_UINT32(uts1, IMXSerialState), 56 VMSTATE_UINT32(onems, IMXSerialState), 57 VMSTATE_UINT32(ufcr, IMXSerialState), 58 VMSTATE_UINT32(ubmr, IMXSerialState), 59 VMSTATE_UINT32(ubrc, IMXSerialState), 60 VMSTATE_UINT32(ucr3, IMXSerialState), 61 VMSTATE_END_OF_LIST() 62 }, 63 }; 64 65 static void imx_update(IMXSerialState *s) 66 { 67 uint32_t flags; 68 69 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 70 if (!(s->ucr1 & UCR1_TXMPTYEN)) { 71 flags &= ~USR1_TRDY; 72 } 73 74 qemu_set_irq(s->irq, !!flags); 75 } 76 77 static void imx_serial_reset(IMXSerialState *s) 78 { 79 80 s->usr1 = USR1_TRDY | USR1_RXDS; 81 /* 82 * Fake attachment of a terminal: assert RTS. 83 */ 84 s->usr1 |= USR1_RTSS; 85 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 86 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 87 s->ucr1 = 0; 88 s->ucr2 = UCR2_SRST; 89 s->ucr3 = 0x700; 90 s->ubmr = 0; 91 s->ubrc = 4; 92 s->readbuff = URXD_ERR; 93 } 94 95 static void imx_serial_reset_at_boot(DeviceState *dev) 96 { 97 IMXSerialState *s = IMX_SERIAL(dev); 98 99 imx_serial_reset(s); 100 101 /* 102 * enable the uart on boot, so messages from the linux decompresser 103 * are visible. On real hardware this is done by the boot rom 104 * before anything else is loaded. 105 */ 106 s->ucr1 = UCR1_UARTEN; 107 s->ucr2 = UCR2_TXEN; 108 109 } 110 111 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 112 unsigned size) 113 { 114 IMXSerialState *s = (IMXSerialState *)opaque; 115 uint32_t c; 116 117 DPRINTF("read(offset=%x)\n", offset >> 2); 118 switch (offset >> 2) { 119 case 0x0: /* URXD */ 120 c = s->readbuff; 121 if (!(s->uts1 & UTS1_RXEMPTY)) { 122 /* Character is valid */ 123 c |= URXD_CHARRDY; 124 s->usr1 &= ~USR1_RRDY; 125 s->usr2 &= ~USR2_RDR; 126 s->uts1 |= UTS1_RXEMPTY; 127 imx_update(s); 128 if (s->chr) { 129 qemu_chr_accept_input(s->chr); 130 } 131 } 132 return c; 133 134 case 0x20: /* UCR1 */ 135 return s->ucr1; 136 137 case 0x21: /* UCR2 */ 138 return s->ucr2; 139 140 case 0x25: /* USR1 */ 141 return s->usr1; 142 143 case 0x26: /* USR2 */ 144 return s->usr2; 145 146 case 0x2A: /* BRM Modulator */ 147 return s->ubmr; 148 149 case 0x2B: /* Baud Rate Count */ 150 return s->ubrc; 151 152 case 0x2d: /* Test register */ 153 return s->uts1; 154 155 case 0x24: /* UFCR */ 156 return s->ufcr; 157 158 case 0x2c: 159 return s->onems; 160 161 case 0x22: /* UCR3 */ 162 return s->ucr3; 163 164 case 0x23: /* UCR4 */ 165 case 0x29: /* BRM Incremental */ 166 return 0x0; /* TODO */ 167 168 default: 169 IPRINTF("%s: bad offset: 0x%x\n", __func__, (int)offset); 170 return 0; 171 } 172 } 173 174 static void imx_serial_write(void *opaque, hwaddr offset, 175 uint64_t value, unsigned size) 176 { 177 IMXSerialState *s = (IMXSerialState *)opaque; 178 unsigned char ch; 179 180 DPRINTF("write(offset=%x, value = %x) to %s\n", 181 offset >> 2, 182 (unsigned int)value, s->chr ? s->chr->label : "NODEV"); 183 184 switch (offset >> 2) { 185 case 0x10: /* UTXD */ 186 ch = value; 187 if (s->ucr2 & UCR2_TXEN) { 188 if (s->chr) { 189 qemu_chr_fe_write(s->chr, &ch, 1); 190 } 191 s->usr1 &= ~USR1_TRDY; 192 imx_update(s); 193 s->usr1 |= USR1_TRDY; 194 imx_update(s); 195 } 196 break; 197 198 case 0x20: /* UCR1 */ 199 s->ucr1 = value & 0xffff; 200 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 201 imx_update(s); 202 break; 203 204 case 0x21: /* UCR2 */ 205 /* 206 * Only a few bits in control register 2 are implemented as yet. 207 * If it's intended to use a real serial device as a back-end, this 208 * register will have to be implemented more fully. 209 */ 210 if (!(value & UCR2_SRST)) { 211 imx_serial_reset(s); 212 imx_update(s); 213 value |= UCR2_SRST; 214 } 215 if (value & UCR2_RXEN) { 216 if (!(s->ucr2 & UCR2_RXEN)) { 217 if (s->chr) { 218 qemu_chr_accept_input(s->chr); 219 } 220 } 221 } 222 s->ucr2 = value & 0xffff; 223 break; 224 225 case 0x25: /* USR1 */ 226 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 227 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 228 s->usr1 &= ~value; 229 break; 230 231 case 0x26: /* USR2 */ 232 /* 233 * Writing 1 to some bits clears them; all other 234 * values are ignored 235 */ 236 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 237 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 238 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 239 s->usr2 &= ~value; 240 break; 241 242 /* 243 * Linux expects to see what it writes to these registers 244 * We don't currently alter the baud rate 245 */ 246 case 0x29: /* UBIR */ 247 s->ubrc = value & 0xffff; 248 break; 249 250 case 0x2a: /* UBMR */ 251 s->ubmr = value & 0xffff; 252 break; 253 254 case 0x2c: /* One ms reg */ 255 s->onems = value & 0xffff; 256 break; 257 258 case 0x24: /* FIFO control register */ 259 s->ufcr = value & 0xffff; 260 break; 261 262 case 0x22: /* UCR3 */ 263 s->ucr3 = value & 0xffff; 264 break; 265 266 case 0x2d: /* UTS1 */ 267 case 0x23: /* UCR4 */ 268 IPRINTF("Unimplemented Register %x written to\n", offset >> 2); 269 /* TODO */ 270 break; 271 272 default: 273 IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset); 274 } 275 } 276 277 static int imx_can_receive(void *opaque) 278 { 279 IMXSerialState *s = (IMXSerialState *)opaque; 280 return !(s->usr1 & USR1_RRDY); 281 } 282 283 static void imx_put_data(void *opaque, uint32_t value) 284 { 285 IMXSerialState *s = (IMXSerialState *)opaque; 286 DPRINTF("received char\n"); 287 s->usr1 |= USR1_RRDY; 288 s->usr2 |= USR2_RDR; 289 s->uts1 &= ~UTS1_RXEMPTY; 290 s->readbuff = value; 291 imx_update(s); 292 } 293 294 static void imx_receive(void *opaque, const uint8_t *buf, int size) 295 { 296 imx_put_data(opaque, *buf); 297 } 298 299 static void imx_event(void *opaque, int event) 300 { 301 if (event == CHR_EVENT_BREAK) { 302 imx_put_data(opaque, URXD_BRK); 303 } 304 } 305 306 307 static const struct MemoryRegionOps imx_serial_ops = { 308 .read = imx_serial_read, 309 .write = imx_serial_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 }; 312 313 static void imx_serial_realize(DeviceState *dev, Error **errp) 314 { 315 IMXSerialState *s = IMX_SERIAL(dev); 316 317 if (s->chr) { 318 qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, 319 imx_event, s); 320 } else { 321 DPRINTF("No char dev for uart at 0x%lx\n", 322 (unsigned long)s->iomem.ram_addr); 323 } 324 } 325 326 static void imx_serial_init(Object *obj) 327 { 328 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 329 IMXSerialState *s = IMX_SERIAL(obj); 330 331 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 332 TYPE_IMX_SERIAL, 0x1000); 333 sysbus_init_mmio(sbd, &s->iomem); 334 sysbus_init_irq(sbd, &s->irq); 335 } 336 337 void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq) 338 { 339 DeviceState *dev; 340 SysBusDevice *bus; 341 CharDriverState *chr; 342 const char chr_name[] = "serial"; 343 char label[ARRAY_SIZE(chr_name) + 1]; 344 345 dev = qdev_create(NULL, TYPE_IMX_SERIAL); 346 347 if (uart >= MAX_SERIAL_PORTS) { 348 hw_error("Cannot assign uart %d: QEMU supports only %d ports\n", 349 uart, MAX_SERIAL_PORTS); 350 } 351 chr = serial_hds[uart]; 352 if (!chr) { 353 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart); 354 chr = qemu_chr_new(label, "null", NULL); 355 if (!(chr)) { 356 hw_error("Can't assign serial port to imx-uart%d.\n", uart); 357 } 358 } 359 360 qdev_prop_set_chr(dev, "chardev", chr); 361 bus = SYS_BUS_DEVICE(dev); 362 qdev_init_nofail(dev); 363 if (addr != (hwaddr)-1) { 364 sysbus_mmio_map(bus, 0, addr); 365 } 366 sysbus_connect_irq(bus, 0, irq); 367 368 } 369 370 371 static Property imx_serial_properties[] = { 372 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 373 DEFINE_PROP_END_OF_LIST(), 374 }; 375 376 static void imx_serial_class_init(ObjectClass *klass, void *data) 377 { 378 DeviceClass *dc = DEVICE_CLASS(klass); 379 380 dc->realize = imx_serial_realize; 381 dc->vmsd = &vmstate_imx_serial; 382 dc->reset = imx_serial_reset_at_boot; 383 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 384 dc->desc = "i.MX series UART"; 385 dc->props = imx_serial_properties; 386 } 387 388 static const TypeInfo imx_serial_info = { 389 .name = TYPE_IMX_SERIAL, 390 .parent = TYPE_SYS_BUS_DEVICE, 391 .instance_size = sizeof(IMXSerialState), 392 .instance_init = imx_serial_init, 393 .class_init = imx_serial_class_init, 394 }; 395 396 static void imx_serial_register_types(void) 397 { 398 type_register_static(&imx_serial_info); 399 } 400 401 type_init(imx_serial_register_types) 402