1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 * This is a `bare-bones' implementation of the IMX series serial ports. 12 * TODO: 13 * -- implement FIFOs. The real hardware has 32 word transmit 14 * and receive FIFOs; we currently use a 1-char buffer 15 * -- implement DMA 16 * -- implement BAUD-rate and modem lines, for when the backend 17 * is a real serial device. 18 */ 19 20 #include "hw/hw.h" 21 #include "hw/sysbus.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/char.h" 24 #include "hw/arm/imx.h" 25 26 //#define DEBUG_SERIAL 1 27 #ifdef DEBUG_SERIAL 28 #define DPRINTF(fmt, args...) \ 29 do { printf("imx_serial: " fmt , ##args); } while (0) 30 #else 31 #define DPRINTF(fmt, args...) do {} while (0) 32 #endif 33 34 /* 35 * Define to 1 for messages about attempts to 36 * access unimplemented registers or similar. 37 */ 38 //#define DEBUG_IMPLEMENTATION 1 39 #ifdef DEBUG_IMPLEMENTATION 40 # define IPRINTF(fmt, args...) \ 41 do { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0) 42 #else 43 # define IPRINTF(fmt, args...) do {} while (0) 44 #endif 45 46 #define TYPE_IMX_SERIAL "imx-serial" 47 #define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL) 48 49 typedef struct IMXSerialState { 50 SysBusDevice parent_obj; 51 52 MemoryRegion iomem; 53 int32_t readbuff; 54 55 uint32_t usr1; 56 uint32_t usr2; 57 uint32_t ucr1; 58 uint32_t ucr2; 59 uint32_t uts1; 60 61 /* 62 * The registers below are implemented just so that the 63 * guest OS sees what it has written 64 */ 65 uint32_t onems; 66 uint32_t ufcr; 67 uint32_t ubmr; 68 uint32_t ubrc; 69 uint32_t ucr3; 70 71 qemu_irq irq; 72 CharDriverState *chr; 73 } IMXSerialState; 74 75 static const VMStateDescription vmstate_imx_serial = { 76 .name = "imx-serial", 77 .version_id = 1, 78 .minimum_version_id = 1, 79 .fields = (VMStateField[]) { 80 VMSTATE_INT32(readbuff, IMXSerialState), 81 VMSTATE_UINT32(usr1, IMXSerialState), 82 VMSTATE_UINT32(usr2, IMXSerialState), 83 VMSTATE_UINT32(ucr1, IMXSerialState), 84 VMSTATE_UINT32(uts1, IMXSerialState), 85 VMSTATE_UINT32(onems, IMXSerialState), 86 VMSTATE_UINT32(ufcr, IMXSerialState), 87 VMSTATE_UINT32(ubmr, IMXSerialState), 88 VMSTATE_UINT32(ubrc, IMXSerialState), 89 VMSTATE_UINT32(ucr3, IMXSerialState), 90 VMSTATE_END_OF_LIST() 91 }, 92 }; 93 94 95 #define URXD_CHARRDY (1<<15) /* character read is valid */ 96 #define URXD_ERR (1<<14) /* Character has error */ 97 #define URXD_BRK (1<<11) /* Break received */ 98 99 #define USR1_PARTYER (1<<15) /* Parity Error */ 100 #define USR1_RTSS (1<<14) /* RTS pin status */ 101 #define USR1_TRDY (1<<13) /* Tx ready */ 102 #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ 103 #define USR1_ESCF (1<<11) /* Escape sequence interrupt */ 104 #define USR1_FRAMERR (1<<10) /* Framing error */ 105 #define USR1_RRDY (1<<9) /* receiver ready */ 106 #define USR1_AGTIM (1<<8) /* Aging timer interrupt */ 107 #define USR1_DTRD (1<<7) /* DTR changed */ 108 #define USR1_RXDS (1<<6) /* Receiver is idle */ 109 #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ 110 #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ 111 112 #define USR2_ADET (1<<15) /* Autobaud complete */ 113 #define USR2_TXFE (1<<14) /* Transmit FIFO empty */ 114 #define USR2_DTRF (1<<13) /* DTR/DSR transition */ 115 #define USR2_IDLE (1<<12) /* UART has been idle for too long */ 116 #define USR2_ACST (1<<11) /* Autobaud counter stopped */ 117 #define USR2_RIDELT (1<<10) /* Ring Indicator delta */ 118 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 119 #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ 120 #define USR2_WAKE (1<<7) /* Start bit detected */ 121 #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ 122 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 123 #define USR2_RTSF (1<<4) /* RTS transition */ 124 #define USR2_TXDC (1<<3) /* Transmission complete */ 125 #define USR2_BRCD (1<<2) /* Break condition detected */ 126 #define USR2_ORE (1<<1) /* Overrun error */ 127 #define USR2_RDR (1<<0) /* Receive data ready */ 128 129 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ 130 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ 131 #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ 132 #define UCR1_UARTEN (1<<0) /* UART Enable */ 133 134 #define UCR2_TXEN (1<<2) /* Transmitter enable */ 135 #define UCR2_RXEN (1<<1) /* Receiver enable */ 136 #define UCR2_SRST (1<<0) /* Reset complete */ 137 138 #define UTS1_TXEMPTY (1<<6) 139 #define UTS1_RXEMPTY (1<<5) 140 #define UTS1_TXFULL (1<<4) 141 #define UTS1_RXFULL (1<<3) 142 143 static void imx_update(IMXSerialState *s) 144 { 145 uint32_t flags; 146 147 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 148 if (!(s->ucr1 & UCR1_TXMPTYEN)) { 149 flags &= ~USR1_TRDY; 150 } 151 152 qemu_set_irq(s->irq, !!flags); 153 } 154 155 static void imx_serial_reset(IMXSerialState *s) 156 { 157 158 s->usr1 = USR1_TRDY | USR1_RXDS; 159 /* 160 * Fake attachment of a terminal: assert RTS. 161 */ 162 s->usr1 |= USR1_RTSS; 163 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 164 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 165 s->ucr1 = 0; 166 s->ucr2 = UCR2_SRST; 167 s->ucr3 = 0x700; 168 s->ubmr = 0; 169 s->ubrc = 4; 170 s->readbuff = URXD_ERR; 171 } 172 173 static void imx_serial_reset_at_boot(DeviceState *dev) 174 { 175 IMXSerialState *s = IMX_SERIAL(dev); 176 177 imx_serial_reset(s); 178 179 /* 180 * enable the uart on boot, so messages from the linux decompresser 181 * are visible. On real hardware this is done by the boot rom 182 * before anything else is loaded. 183 */ 184 s->ucr1 = UCR1_UARTEN; 185 s->ucr2 = UCR2_TXEN; 186 187 } 188 189 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 190 unsigned size) 191 { 192 IMXSerialState *s = (IMXSerialState *)opaque; 193 uint32_t c; 194 195 DPRINTF("read(offset=%x)\n", offset >> 2); 196 switch (offset >> 2) { 197 case 0x0: /* URXD */ 198 c = s->readbuff; 199 if (!(s->uts1 & UTS1_RXEMPTY)) { 200 /* Character is valid */ 201 c |= URXD_CHARRDY; 202 s->usr1 &= ~USR1_RRDY; 203 s->usr2 &= ~USR2_RDR; 204 s->uts1 |= UTS1_RXEMPTY; 205 imx_update(s); 206 qemu_chr_accept_input(s->chr); 207 } 208 return c; 209 210 case 0x20: /* UCR1 */ 211 return s->ucr1; 212 213 case 0x21: /* UCR2 */ 214 return s->ucr2; 215 216 case 0x25: /* USR1 */ 217 return s->usr1; 218 219 case 0x26: /* USR2 */ 220 return s->usr2; 221 222 case 0x2A: /* BRM Modulator */ 223 return s->ubmr; 224 225 case 0x2B: /* Baud Rate Count */ 226 return s->ubrc; 227 228 case 0x2d: /* Test register */ 229 return s->uts1; 230 231 case 0x24: /* UFCR */ 232 return s->ufcr; 233 234 case 0x2c: 235 return s->onems; 236 237 case 0x22: /* UCR3 */ 238 return s->ucr3; 239 240 case 0x23: /* UCR4 */ 241 case 0x29: /* BRM Incremental */ 242 return 0x0; /* TODO */ 243 244 default: 245 IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset); 246 return 0; 247 } 248 } 249 250 static void imx_serial_write(void *opaque, hwaddr offset, 251 uint64_t value, unsigned size) 252 { 253 IMXSerialState *s = (IMXSerialState *)opaque; 254 unsigned char ch; 255 256 DPRINTF("write(offset=%x, value = %x) to %s\n", 257 offset >> 2, 258 (unsigned int)value, s->chr ? s->chr->label : "NODEV"); 259 260 switch (offset >> 2) { 261 case 0x10: /* UTXD */ 262 ch = value; 263 if (s->ucr2 & UCR2_TXEN) { 264 if (s->chr) { 265 qemu_chr_fe_write(s->chr, &ch, 1); 266 } 267 s->usr1 &= ~USR1_TRDY; 268 imx_update(s); 269 s->usr1 |= USR1_TRDY; 270 imx_update(s); 271 } 272 break; 273 274 case 0x20: /* UCR1 */ 275 s->ucr1 = value & 0xffff; 276 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 277 imx_update(s); 278 break; 279 280 case 0x21: /* UCR2 */ 281 /* 282 * Only a few bits in control register 2 are implemented as yet. 283 * If it's intended to use a real serial device as a back-end, this 284 * register will have to be implemented more fully. 285 */ 286 if (!(value & UCR2_SRST)) { 287 imx_serial_reset(s); 288 imx_update(s); 289 value |= UCR2_SRST; 290 } 291 if (value & UCR2_RXEN) { 292 if (!(s->ucr2 & UCR2_RXEN)) { 293 qemu_chr_accept_input(s->chr); 294 } 295 } 296 s->ucr2 = value & 0xffff; 297 break; 298 299 case 0x25: /* USR1 */ 300 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 301 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 302 s->usr1 &= ~value; 303 break; 304 305 case 0x26: /* USR2 */ 306 /* 307 * Writing 1 to some bits clears them; all other 308 * values are ignored 309 */ 310 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 311 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 312 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 313 s->usr2 &= ~value; 314 break; 315 316 /* 317 * Linux expects to see what it writes to these registers 318 * We don't currently alter the baud rate 319 */ 320 case 0x29: /* UBIR */ 321 s->ubrc = value & 0xffff; 322 break; 323 324 case 0x2a: /* UBMR */ 325 s->ubmr = value & 0xffff; 326 break; 327 328 case 0x2c: /* One ms reg */ 329 s->onems = value & 0xffff; 330 break; 331 332 case 0x24: /* FIFO control register */ 333 s->ufcr = value & 0xffff; 334 break; 335 336 case 0x22: /* UCR3 */ 337 s->ucr3 = value & 0xffff; 338 break; 339 340 case 0x2d: /* UTS1 */ 341 case 0x23: /* UCR4 */ 342 IPRINTF("Unimplemented Register %x written to\n", offset >> 2); 343 /* TODO */ 344 break; 345 346 default: 347 IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset); 348 } 349 } 350 351 static int imx_can_receive(void *opaque) 352 { 353 IMXSerialState *s = (IMXSerialState *)opaque; 354 return !(s->usr1 & USR1_RRDY); 355 } 356 357 static void imx_put_data(void *opaque, uint32_t value) 358 { 359 IMXSerialState *s = (IMXSerialState *)opaque; 360 DPRINTF("received char\n"); 361 s->usr1 |= USR1_RRDY; 362 s->usr2 |= USR2_RDR; 363 s->uts1 &= ~UTS1_RXEMPTY; 364 s->readbuff = value; 365 imx_update(s); 366 } 367 368 static void imx_receive(void *opaque, const uint8_t *buf, int size) 369 { 370 imx_put_data(opaque, *buf); 371 } 372 373 static void imx_event(void *opaque, int event) 374 { 375 if (event == CHR_EVENT_BREAK) { 376 imx_put_data(opaque, URXD_BRK); 377 } 378 } 379 380 381 static const struct MemoryRegionOps imx_serial_ops = { 382 .read = imx_serial_read, 383 .write = imx_serial_write, 384 .endianness = DEVICE_NATIVE_ENDIAN, 385 }; 386 387 static int imx_serial_init(SysBusDevice *dev) 388 { 389 IMXSerialState *s = IMX_SERIAL(dev); 390 391 392 memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s, 393 "imx-serial", 0x1000); 394 sysbus_init_mmio(dev, &s->iomem); 395 sysbus_init_irq(dev, &s->irq); 396 397 if (s->chr) { 398 qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, 399 imx_event, s); 400 } else { 401 DPRINTF("No char dev for uart at 0x%lx\n", 402 (unsigned long)s->iomem.ram_addr); 403 } 404 405 return 0; 406 } 407 408 void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq) 409 { 410 DeviceState *dev; 411 SysBusDevice *bus; 412 CharDriverState *chr; 413 const char chr_name[] = "serial"; 414 char label[ARRAY_SIZE(chr_name) + 1]; 415 416 dev = qdev_create(NULL, TYPE_IMX_SERIAL); 417 418 if (uart >= MAX_SERIAL_PORTS) { 419 hw_error("Cannot assign uart %d: QEMU supports only %d ports\n", 420 uart, MAX_SERIAL_PORTS); 421 } 422 chr = serial_hds[uart]; 423 if (!chr) { 424 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart); 425 chr = qemu_chr_new(label, "null", NULL); 426 if (!(chr)) { 427 hw_error("Can't assign serial port to imx-uart%d.\n", uart); 428 } 429 } 430 431 qdev_prop_set_chr(dev, "chardev", chr); 432 bus = SYS_BUS_DEVICE(dev); 433 qdev_init_nofail(dev); 434 if (addr != (hwaddr)-1) { 435 sysbus_mmio_map(bus, 0, addr); 436 } 437 sysbus_connect_irq(bus, 0, irq); 438 439 } 440 441 442 static Property imx32_serial_properties[] = { 443 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 444 DEFINE_PROP_END_OF_LIST(), 445 }; 446 447 static void imx_serial_class_init(ObjectClass *klass, void *data) 448 { 449 DeviceClass *dc = DEVICE_CLASS(klass); 450 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 451 452 k->init = imx_serial_init; 453 dc->vmsd = &vmstate_imx_serial; 454 dc->reset = imx_serial_reset_at_boot; 455 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 456 dc->desc = "i.MX series UART"; 457 dc->props = imx32_serial_properties; 458 } 459 460 static const TypeInfo imx_serial_info = { 461 .name = TYPE_IMX_SERIAL, 462 .parent = TYPE_SYS_BUS_DEVICE, 463 .instance_size = sizeof(IMXSerialState), 464 .class_init = imx_serial_class_init, 465 }; 466 467 static void imx_serial_register_types(void) 468 { 469 type_register_static(&imx_serial_info); 470 } 471 472 type_init(imx_serial_register_types) 473