1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "qemu/log.h" 25 26 #ifndef DEBUG_IMX_UART 27 #define DEBUG_IMX_UART 0 28 #endif 29 30 #define DPRINTF(fmt, args...) \ 31 do { \ 32 if (DEBUG_IMX_UART) { \ 33 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 34 __func__, ##args); \ 35 } \ 36 } while (0) 37 38 static const VMStateDescription vmstate_imx_serial = { 39 .name = TYPE_IMX_SERIAL, 40 .version_id = 1, 41 .minimum_version_id = 1, 42 .fields = (VMStateField[]) { 43 VMSTATE_INT32(readbuff, IMXSerialState), 44 VMSTATE_UINT32(usr1, IMXSerialState), 45 VMSTATE_UINT32(usr2, IMXSerialState), 46 VMSTATE_UINT32(ucr1, IMXSerialState), 47 VMSTATE_UINT32(uts1, IMXSerialState), 48 VMSTATE_UINT32(onems, IMXSerialState), 49 VMSTATE_UINT32(ufcr, IMXSerialState), 50 VMSTATE_UINT32(ubmr, IMXSerialState), 51 VMSTATE_UINT32(ubrc, IMXSerialState), 52 VMSTATE_UINT32(ucr3, IMXSerialState), 53 VMSTATE_END_OF_LIST() 54 }, 55 }; 56 57 static void imx_update(IMXSerialState *s) 58 { 59 uint32_t flags; 60 61 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 62 if (s->ucr1 & UCR1_TXMPTYEN) { 63 flags |= (s->uts1 & UTS1_TXEMPTY); 64 } else { 65 flags &= ~USR1_TRDY; 66 } 67 68 qemu_set_irq(s->irq, !!flags); 69 } 70 71 static void imx_serial_reset(IMXSerialState *s) 72 { 73 74 s->usr1 = USR1_TRDY | USR1_RXDS; 75 /* 76 * Fake attachment of a terminal: assert RTS. 77 */ 78 s->usr1 |= USR1_RTSS; 79 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 80 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 81 s->ucr1 = 0; 82 s->ucr2 = UCR2_SRST; 83 s->ucr3 = 0x700; 84 s->ubmr = 0; 85 s->ubrc = 4; 86 s->readbuff = URXD_ERR; 87 } 88 89 static void imx_serial_reset_at_boot(DeviceState *dev) 90 { 91 IMXSerialState *s = IMX_SERIAL(dev); 92 93 imx_serial_reset(s); 94 95 /* 96 * enable the uart on boot, so messages from the linux decompresser 97 * are visible. On real hardware this is done by the boot rom 98 * before anything else is loaded. 99 */ 100 s->ucr1 = UCR1_UARTEN; 101 s->ucr2 = UCR2_TXEN; 102 103 } 104 105 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 106 unsigned size) 107 { 108 IMXSerialState *s = (IMXSerialState *)opaque; 109 uint32_t c; 110 111 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 112 113 switch (offset >> 2) { 114 case 0x0: /* URXD */ 115 c = s->readbuff; 116 if (!(s->uts1 & UTS1_RXEMPTY)) { 117 /* Character is valid */ 118 c |= URXD_CHARRDY; 119 s->usr1 &= ~USR1_RRDY; 120 s->usr2 &= ~USR2_RDR; 121 s->uts1 |= UTS1_RXEMPTY; 122 imx_update(s); 123 qemu_chr_fe_accept_input(&s->chr); 124 } 125 return c; 126 127 case 0x20: /* UCR1 */ 128 return s->ucr1; 129 130 case 0x21: /* UCR2 */ 131 return s->ucr2; 132 133 case 0x25: /* USR1 */ 134 return s->usr1; 135 136 case 0x26: /* USR2 */ 137 return s->usr2; 138 139 case 0x2A: /* BRM Modulator */ 140 return s->ubmr; 141 142 case 0x2B: /* Baud Rate Count */ 143 return s->ubrc; 144 145 case 0x2d: /* Test register */ 146 return s->uts1; 147 148 case 0x24: /* UFCR */ 149 return s->ufcr; 150 151 case 0x2c: 152 return s->onems; 153 154 case 0x22: /* UCR3 */ 155 return s->ucr3; 156 157 case 0x23: /* UCR4 */ 158 case 0x29: /* BRM Incremental */ 159 return 0x0; /* TODO */ 160 161 default: 162 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 163 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 164 return 0; 165 } 166 } 167 168 static void imx_serial_write(void *opaque, hwaddr offset, 169 uint64_t value, unsigned size) 170 { 171 IMXSerialState *s = (IMXSerialState *)opaque; 172 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 173 unsigned char ch; 174 175 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 176 offset, (unsigned int)value, chr ? chr->label : "NODEV"); 177 178 switch (offset >> 2) { 179 case 0x10: /* UTXD */ 180 ch = value; 181 if (s->ucr2 & UCR2_TXEN) { 182 /* XXX this blocks entire thread. Rewrite to use 183 * qemu_chr_fe_write and background I/O callbacks */ 184 qemu_chr_fe_write_all(&s->chr, &ch, 1); 185 s->usr1 &= ~USR1_TRDY; 186 imx_update(s); 187 s->usr1 |= USR1_TRDY; 188 imx_update(s); 189 } 190 break; 191 192 case 0x20: /* UCR1 */ 193 s->ucr1 = value & 0xffff; 194 195 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 196 197 imx_update(s); 198 break; 199 200 case 0x21: /* UCR2 */ 201 /* 202 * Only a few bits in control register 2 are implemented as yet. 203 * If it's intended to use a real serial device as a back-end, this 204 * register will have to be implemented more fully. 205 */ 206 if (!(value & UCR2_SRST)) { 207 imx_serial_reset(s); 208 imx_update(s); 209 value |= UCR2_SRST; 210 } 211 if (value & UCR2_RXEN) { 212 if (!(s->ucr2 & UCR2_RXEN)) { 213 qemu_chr_fe_accept_input(&s->chr); 214 } 215 } 216 s->ucr2 = value & 0xffff; 217 break; 218 219 case 0x25: /* USR1 */ 220 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 221 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 222 s->usr1 &= ~value; 223 break; 224 225 case 0x26: /* USR2 */ 226 /* 227 * Writing 1 to some bits clears them; all other 228 * values are ignored 229 */ 230 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 231 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 232 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 233 s->usr2 &= ~value; 234 break; 235 236 /* 237 * Linux expects to see what it writes to these registers 238 * We don't currently alter the baud rate 239 */ 240 case 0x29: /* UBIR */ 241 s->ubrc = value & 0xffff; 242 break; 243 244 case 0x2a: /* UBMR */ 245 s->ubmr = value & 0xffff; 246 break; 247 248 case 0x2c: /* One ms reg */ 249 s->onems = value & 0xffff; 250 break; 251 252 case 0x24: /* FIFO control register */ 253 s->ufcr = value & 0xffff; 254 break; 255 256 case 0x22: /* UCR3 */ 257 s->ucr3 = value & 0xffff; 258 break; 259 260 case 0x2d: /* UTS1 */ 261 case 0x23: /* UCR4 */ 262 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 263 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 264 /* TODO */ 265 break; 266 267 default: 268 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 269 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 270 } 271 } 272 273 static int imx_can_receive(void *opaque) 274 { 275 IMXSerialState *s = (IMXSerialState *)opaque; 276 return !(s->usr1 & USR1_RRDY); 277 } 278 279 static void imx_put_data(void *opaque, uint32_t value) 280 { 281 IMXSerialState *s = (IMXSerialState *)opaque; 282 283 DPRINTF("received char\n"); 284 285 s->usr1 |= USR1_RRDY; 286 s->usr2 |= USR2_RDR; 287 s->uts1 &= ~UTS1_RXEMPTY; 288 s->readbuff = value; 289 imx_update(s); 290 } 291 292 static void imx_receive(void *opaque, const uint8_t *buf, int size) 293 { 294 imx_put_data(opaque, *buf); 295 } 296 297 static void imx_event(void *opaque, int event) 298 { 299 if (event == CHR_EVENT_BREAK) { 300 imx_put_data(opaque, URXD_BRK); 301 } 302 } 303 304 305 static const struct MemoryRegionOps imx_serial_ops = { 306 .read = imx_serial_read, 307 .write = imx_serial_write, 308 .endianness = DEVICE_NATIVE_ENDIAN, 309 }; 310 311 static void imx_serial_realize(DeviceState *dev, Error **errp) 312 { 313 IMXSerialState *s = IMX_SERIAL(dev); 314 315 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 316 317 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 318 imx_event, NULL, s, NULL, true); 319 } 320 321 static void imx_serial_init(Object *obj) 322 { 323 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 324 IMXSerialState *s = IMX_SERIAL(obj); 325 326 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 327 TYPE_IMX_SERIAL, 0x1000); 328 sysbus_init_mmio(sbd, &s->iomem); 329 sysbus_init_irq(sbd, &s->irq); 330 } 331 332 static Property imx_serial_properties[] = { 333 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 334 DEFINE_PROP_END_OF_LIST(), 335 }; 336 337 static void imx_serial_class_init(ObjectClass *klass, void *data) 338 { 339 DeviceClass *dc = DEVICE_CLASS(klass); 340 341 dc->realize = imx_serial_realize; 342 dc->vmsd = &vmstate_imx_serial; 343 dc->reset = imx_serial_reset_at_boot; 344 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 345 dc->desc = "i.MX series UART"; 346 dc->props = imx_serial_properties; 347 } 348 349 static const TypeInfo imx_serial_info = { 350 .name = TYPE_IMX_SERIAL, 351 .parent = TYPE_SYS_BUS_DEVICE, 352 .instance_size = sizeof(IMXSerialState), 353 .instance_init = imx_serial_init, 354 .class_init = imx_serial_class_init, 355 }; 356 357 static void imx_serial_register_types(void) 358 { 359 type_register_static(&imx_serial_info); 360 } 361 362 type_init(imx_serial_register_types) 363