1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "qemu/log.h" 25 26 #ifndef DEBUG_IMX_UART 27 #define DEBUG_IMX_UART 0 28 #endif 29 30 #define DPRINTF(fmt, args...) \ 31 do { \ 32 if (DEBUG_IMX_UART) { \ 33 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 34 __func__, ##args); \ 35 } \ 36 } while (0) 37 38 static const VMStateDescription vmstate_imx_serial = { 39 .name = TYPE_IMX_SERIAL, 40 .version_id = 2, 41 .minimum_version_id = 2, 42 .fields = (VMStateField[]) { 43 VMSTATE_INT32(readbuff, IMXSerialState), 44 VMSTATE_UINT32(usr1, IMXSerialState), 45 VMSTATE_UINT32(usr2, IMXSerialState), 46 VMSTATE_UINT32(ucr1, IMXSerialState), 47 VMSTATE_UINT32(uts1, IMXSerialState), 48 VMSTATE_UINT32(onems, IMXSerialState), 49 VMSTATE_UINT32(ufcr, IMXSerialState), 50 VMSTATE_UINT32(ubmr, IMXSerialState), 51 VMSTATE_UINT32(ubrc, IMXSerialState), 52 VMSTATE_UINT32(ucr3, IMXSerialState), 53 VMSTATE_UINT32(ucr4, IMXSerialState), 54 VMSTATE_END_OF_LIST() 55 }, 56 }; 57 58 static void imx_update(IMXSerialState *s) 59 { 60 uint32_t usr1; 61 uint32_t usr2; 62 uint32_t mask; 63 64 /* 65 * Lucky for us TRDY and RRDY has the same offset in both USR1 and 66 * UCR1, so we can get away with something as simple as the 67 * following: 68 */ 69 usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); 70 /* 71 * Bits that we want in USR2 are not as conveniently laid out, 72 * unfortunately. 73 */ 74 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; 75 /* 76 * TCEN and TXDC are both bit 3 77 */ 78 mask |= s->ucr4 & UCR4_TCEN; 79 80 usr2 = s->usr2 & mask; 81 82 qemu_set_irq(s->irq, usr1 || usr2); 83 } 84 85 static void imx_serial_reset(IMXSerialState *s) 86 { 87 88 s->usr1 = USR1_TRDY | USR1_RXDS; 89 /* 90 * Fake attachment of a terminal: assert RTS. 91 */ 92 s->usr1 |= USR1_RTSS; 93 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 94 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 95 s->ucr1 = 0; 96 s->ucr2 = UCR2_SRST; 97 s->ucr3 = 0x700; 98 s->ubmr = 0; 99 s->ubrc = 4; 100 s->readbuff = URXD_ERR; 101 } 102 103 static void imx_serial_reset_at_boot(DeviceState *dev) 104 { 105 IMXSerialState *s = IMX_SERIAL(dev); 106 107 imx_serial_reset(s); 108 109 /* 110 * enable the uart on boot, so messages from the linux decompresser 111 * are visible. On real hardware this is done by the boot rom 112 * before anything else is loaded. 113 */ 114 s->ucr1 = UCR1_UARTEN; 115 s->ucr2 = UCR2_TXEN; 116 117 } 118 119 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 120 unsigned size) 121 { 122 IMXSerialState *s = (IMXSerialState *)opaque; 123 uint32_t c; 124 125 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 126 127 switch (offset >> 2) { 128 case 0x0: /* URXD */ 129 c = s->readbuff; 130 if (!(s->uts1 & UTS1_RXEMPTY)) { 131 /* Character is valid */ 132 c |= URXD_CHARRDY; 133 s->usr1 &= ~USR1_RRDY; 134 s->usr2 &= ~USR2_RDR; 135 s->uts1 |= UTS1_RXEMPTY; 136 imx_update(s); 137 qemu_chr_fe_accept_input(&s->chr); 138 } 139 return c; 140 141 case 0x20: /* UCR1 */ 142 return s->ucr1; 143 144 case 0x21: /* UCR2 */ 145 return s->ucr2; 146 147 case 0x25: /* USR1 */ 148 return s->usr1; 149 150 case 0x26: /* USR2 */ 151 return s->usr2; 152 153 case 0x2A: /* BRM Modulator */ 154 return s->ubmr; 155 156 case 0x2B: /* Baud Rate Count */ 157 return s->ubrc; 158 159 case 0x2d: /* Test register */ 160 return s->uts1; 161 162 case 0x24: /* UFCR */ 163 return s->ufcr; 164 165 case 0x2c: 166 return s->onems; 167 168 case 0x22: /* UCR3 */ 169 return s->ucr3; 170 171 case 0x23: /* UCR4 */ 172 return s->ucr4; 173 174 case 0x29: /* BRM Incremental */ 175 return 0x0; /* TODO */ 176 177 default: 178 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 179 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 180 return 0; 181 } 182 } 183 184 static void imx_serial_write(void *opaque, hwaddr offset, 185 uint64_t value, unsigned size) 186 { 187 IMXSerialState *s = (IMXSerialState *)opaque; 188 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 189 unsigned char ch; 190 191 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 192 offset, (unsigned int)value, chr ? chr->label : "NODEV"); 193 194 switch (offset >> 2) { 195 case 0x10: /* UTXD */ 196 ch = value; 197 if (s->ucr2 & UCR2_TXEN) { 198 /* XXX this blocks entire thread. Rewrite to use 199 * qemu_chr_fe_write and background I/O callbacks */ 200 qemu_chr_fe_write_all(&s->chr, &ch, 1); 201 s->usr1 &= ~USR1_TRDY; 202 s->usr2 &= ~USR2_TXDC; 203 imx_update(s); 204 s->usr1 |= USR1_TRDY; 205 s->usr2 |= USR2_TXDC; 206 imx_update(s); 207 } 208 break; 209 210 case 0x20: /* UCR1 */ 211 s->ucr1 = value & 0xffff; 212 213 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 214 215 imx_update(s); 216 break; 217 218 case 0x21: /* UCR2 */ 219 /* 220 * Only a few bits in control register 2 are implemented as yet. 221 * If it's intended to use a real serial device as a back-end, this 222 * register will have to be implemented more fully. 223 */ 224 if (!(value & UCR2_SRST)) { 225 imx_serial_reset(s); 226 imx_update(s); 227 value |= UCR2_SRST; 228 } 229 if (value & UCR2_RXEN) { 230 if (!(s->ucr2 & UCR2_RXEN)) { 231 qemu_chr_fe_accept_input(&s->chr); 232 } 233 } 234 s->ucr2 = value & 0xffff; 235 break; 236 237 case 0x25: /* USR1 */ 238 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 239 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 240 s->usr1 &= ~value; 241 break; 242 243 case 0x26: /* USR2 */ 244 /* 245 * Writing 1 to some bits clears them; all other 246 * values are ignored 247 */ 248 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 249 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 250 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 251 s->usr2 &= ~value; 252 break; 253 254 /* 255 * Linux expects to see what it writes to these registers 256 * We don't currently alter the baud rate 257 */ 258 case 0x29: /* UBIR */ 259 s->ubrc = value & 0xffff; 260 break; 261 262 case 0x2a: /* UBMR */ 263 s->ubmr = value & 0xffff; 264 break; 265 266 case 0x2c: /* One ms reg */ 267 s->onems = value & 0xffff; 268 break; 269 270 case 0x24: /* FIFO control register */ 271 s->ufcr = value & 0xffff; 272 break; 273 274 case 0x22: /* UCR3 */ 275 s->ucr3 = value & 0xffff; 276 break; 277 278 case 0x23: /* UCR4 */ 279 s->ucr4 = value & 0xffff; 280 imx_update(s); 281 break; 282 283 case 0x2d: /* UTS1 */ 284 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 285 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 286 /* TODO */ 287 break; 288 289 default: 290 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 291 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 292 } 293 } 294 295 static int imx_can_receive(void *opaque) 296 { 297 IMXSerialState *s = (IMXSerialState *)opaque; 298 return !(s->usr1 & USR1_RRDY); 299 } 300 301 static void imx_put_data(void *opaque, uint32_t value) 302 { 303 IMXSerialState *s = (IMXSerialState *)opaque; 304 305 DPRINTF("received char\n"); 306 307 s->usr1 |= USR1_RRDY; 308 s->usr2 |= USR2_RDR; 309 s->uts1 &= ~UTS1_RXEMPTY; 310 s->readbuff = value; 311 if (value & URXD_BRK) { 312 s->usr2 |= USR2_BRCD; 313 } 314 imx_update(s); 315 } 316 317 static void imx_receive(void *opaque, const uint8_t *buf, int size) 318 { 319 imx_put_data(opaque, *buf); 320 } 321 322 static void imx_event(void *opaque, int event) 323 { 324 if (event == CHR_EVENT_BREAK) { 325 imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); 326 } 327 } 328 329 330 static const struct MemoryRegionOps imx_serial_ops = { 331 .read = imx_serial_read, 332 .write = imx_serial_write, 333 .endianness = DEVICE_NATIVE_ENDIAN, 334 }; 335 336 static void imx_serial_realize(DeviceState *dev, Error **errp) 337 { 338 IMXSerialState *s = IMX_SERIAL(dev); 339 340 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 341 342 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 343 imx_event, NULL, s, NULL, true); 344 } 345 346 static void imx_serial_init(Object *obj) 347 { 348 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 349 IMXSerialState *s = IMX_SERIAL(obj); 350 351 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 352 TYPE_IMX_SERIAL, 0x1000); 353 sysbus_init_mmio(sbd, &s->iomem); 354 sysbus_init_irq(sbd, &s->irq); 355 } 356 357 static Property imx_serial_properties[] = { 358 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 359 DEFINE_PROP_END_OF_LIST(), 360 }; 361 362 static void imx_serial_class_init(ObjectClass *klass, void *data) 363 { 364 DeviceClass *dc = DEVICE_CLASS(klass); 365 366 dc->realize = imx_serial_realize; 367 dc->vmsd = &vmstate_imx_serial; 368 dc->reset = imx_serial_reset_at_boot; 369 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 370 dc->desc = "i.MX series UART"; 371 dc->props = imx_serial_properties; 372 } 373 374 static const TypeInfo imx_serial_info = { 375 .name = TYPE_IMX_SERIAL, 376 .parent = TYPE_SYS_BUS_DEVICE, 377 .instance_size = sizeof(IMXSerialState), 378 .instance_init = imx_serial_init, 379 .class_init = imx_serial_class_init, 380 }; 381 382 static void imx_serial_register_types(void) 383 { 384 type_register_static(&imx_serial_info); 385 } 386 387 type_init(imx_serial_register_types) 388