1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 27 #ifndef DEBUG_IMX_UART 28 #define DEBUG_IMX_UART 0 29 #endif 30 31 #define DPRINTF(fmt, args...) \ 32 do { \ 33 if (DEBUG_IMX_UART) { \ 34 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 35 __func__, ##args); \ 36 } \ 37 } while (0) 38 39 static const VMStateDescription vmstate_imx_serial = { 40 .name = TYPE_IMX_SERIAL, 41 .version_id = 2, 42 .minimum_version_id = 2, 43 .fields = (VMStateField[]) { 44 VMSTATE_INT32(readbuff, IMXSerialState), 45 VMSTATE_UINT32(usr1, IMXSerialState), 46 VMSTATE_UINT32(usr2, IMXSerialState), 47 VMSTATE_UINT32(ucr1, IMXSerialState), 48 VMSTATE_UINT32(uts1, IMXSerialState), 49 VMSTATE_UINT32(onems, IMXSerialState), 50 VMSTATE_UINT32(ufcr, IMXSerialState), 51 VMSTATE_UINT32(ubmr, IMXSerialState), 52 VMSTATE_UINT32(ubrc, IMXSerialState), 53 VMSTATE_UINT32(ucr3, IMXSerialState), 54 VMSTATE_UINT32(ucr4, IMXSerialState), 55 VMSTATE_END_OF_LIST() 56 }, 57 }; 58 59 static void imx_update(IMXSerialState *s) 60 { 61 uint32_t usr1; 62 uint32_t usr2; 63 uint32_t mask; 64 65 /* 66 * Lucky for us TRDY and RRDY has the same offset in both USR1 and 67 * UCR1, so we can get away with something as simple as the 68 * following: 69 */ 70 usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); 71 /* 72 * Bits that we want in USR2 are not as conveniently laid out, 73 * unfortunately. 74 */ 75 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; 76 /* 77 * TCEN and TXDC are both bit 3 78 * RDR and DREN are both bit 0 79 */ 80 mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); 81 82 usr2 = s->usr2 & mask; 83 84 qemu_set_irq(s->irq, usr1 || usr2); 85 } 86 87 static void imx_serial_reset(IMXSerialState *s) 88 { 89 90 s->usr1 = USR1_TRDY | USR1_RXDS; 91 /* 92 * Fake attachment of a terminal: assert RTS. 93 */ 94 s->usr1 |= USR1_RTSS; 95 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 96 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 97 s->ucr1 = 0; 98 s->ucr2 = UCR2_SRST; 99 s->ucr3 = 0x700; 100 s->ubmr = 0; 101 s->ubrc = 4; 102 s->readbuff = URXD_ERR; 103 } 104 105 static void imx_serial_reset_at_boot(DeviceState *dev) 106 { 107 IMXSerialState *s = IMX_SERIAL(dev); 108 109 imx_serial_reset(s); 110 111 /* 112 * enable the uart on boot, so messages from the linux decompresser 113 * are visible. On real hardware this is done by the boot rom 114 * before anything else is loaded. 115 */ 116 s->ucr1 = UCR1_UARTEN; 117 s->ucr2 = UCR2_TXEN; 118 119 } 120 121 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 122 unsigned size) 123 { 124 IMXSerialState *s = (IMXSerialState *)opaque; 125 uint32_t c; 126 127 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 128 129 switch (offset >> 2) { 130 case 0x0: /* URXD */ 131 c = s->readbuff; 132 if (!(s->uts1 & UTS1_RXEMPTY)) { 133 /* Character is valid */ 134 c |= URXD_CHARRDY; 135 s->usr1 &= ~USR1_RRDY; 136 s->usr2 &= ~USR2_RDR; 137 s->uts1 |= UTS1_RXEMPTY; 138 imx_update(s); 139 qemu_chr_fe_accept_input(&s->chr); 140 } 141 return c; 142 143 case 0x20: /* UCR1 */ 144 return s->ucr1; 145 146 case 0x21: /* UCR2 */ 147 return s->ucr2; 148 149 case 0x25: /* USR1 */ 150 return s->usr1; 151 152 case 0x26: /* USR2 */ 153 return s->usr2; 154 155 case 0x2A: /* BRM Modulator */ 156 return s->ubmr; 157 158 case 0x2B: /* Baud Rate Count */ 159 return s->ubrc; 160 161 case 0x2d: /* Test register */ 162 return s->uts1; 163 164 case 0x24: /* UFCR */ 165 return s->ufcr; 166 167 case 0x2c: 168 return s->onems; 169 170 case 0x22: /* UCR3 */ 171 return s->ucr3; 172 173 case 0x23: /* UCR4 */ 174 return s->ucr4; 175 176 case 0x29: /* BRM Incremental */ 177 return 0x0; /* TODO */ 178 179 default: 180 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 181 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 182 return 0; 183 } 184 } 185 186 static void imx_serial_write(void *opaque, hwaddr offset, 187 uint64_t value, unsigned size) 188 { 189 IMXSerialState *s = (IMXSerialState *)opaque; 190 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 191 unsigned char ch; 192 193 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 194 offset, (unsigned int)value, chr ? chr->label : "NODEV"); 195 196 switch (offset >> 2) { 197 case 0x10: /* UTXD */ 198 ch = value; 199 if (s->ucr2 & UCR2_TXEN) { 200 /* XXX this blocks entire thread. Rewrite to use 201 * qemu_chr_fe_write and background I/O callbacks */ 202 qemu_chr_fe_write_all(&s->chr, &ch, 1); 203 s->usr1 &= ~USR1_TRDY; 204 s->usr2 &= ~USR2_TXDC; 205 imx_update(s); 206 s->usr1 |= USR1_TRDY; 207 s->usr2 |= USR2_TXDC; 208 imx_update(s); 209 } 210 break; 211 212 case 0x20: /* UCR1 */ 213 s->ucr1 = value & 0xffff; 214 215 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 216 217 imx_update(s); 218 break; 219 220 case 0x21: /* UCR2 */ 221 /* 222 * Only a few bits in control register 2 are implemented as yet. 223 * If it's intended to use a real serial device as a back-end, this 224 * register will have to be implemented more fully. 225 */ 226 if (!(value & UCR2_SRST)) { 227 imx_serial_reset(s); 228 imx_update(s); 229 value |= UCR2_SRST; 230 } 231 if (value & UCR2_RXEN) { 232 if (!(s->ucr2 & UCR2_RXEN)) { 233 qemu_chr_fe_accept_input(&s->chr); 234 } 235 } 236 s->ucr2 = value & 0xffff; 237 break; 238 239 case 0x25: /* USR1 */ 240 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 241 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 242 s->usr1 &= ~value; 243 break; 244 245 case 0x26: /* USR2 */ 246 /* 247 * Writing 1 to some bits clears them; all other 248 * values are ignored 249 */ 250 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 251 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 252 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 253 s->usr2 &= ~value; 254 break; 255 256 /* 257 * Linux expects to see what it writes to these registers 258 * We don't currently alter the baud rate 259 */ 260 case 0x29: /* UBIR */ 261 s->ubrc = value & 0xffff; 262 break; 263 264 case 0x2a: /* UBMR */ 265 s->ubmr = value & 0xffff; 266 break; 267 268 case 0x2c: /* One ms reg */ 269 s->onems = value & 0xffff; 270 break; 271 272 case 0x24: /* FIFO control register */ 273 s->ufcr = value & 0xffff; 274 break; 275 276 case 0x22: /* UCR3 */ 277 s->ucr3 = value & 0xffff; 278 break; 279 280 case 0x23: /* UCR4 */ 281 s->ucr4 = value & 0xffff; 282 imx_update(s); 283 break; 284 285 case 0x2d: /* UTS1 */ 286 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 287 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 288 /* TODO */ 289 break; 290 291 default: 292 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 293 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 294 } 295 } 296 297 static int imx_can_receive(void *opaque) 298 { 299 IMXSerialState *s = (IMXSerialState *)opaque; 300 return !(s->usr1 & USR1_RRDY); 301 } 302 303 static void imx_put_data(void *opaque, uint32_t value) 304 { 305 IMXSerialState *s = (IMXSerialState *)opaque; 306 307 DPRINTF("received char\n"); 308 309 s->usr1 |= USR1_RRDY; 310 s->usr2 |= USR2_RDR; 311 s->uts1 &= ~UTS1_RXEMPTY; 312 s->readbuff = value; 313 if (value & URXD_BRK) { 314 s->usr2 |= USR2_BRCD; 315 } 316 imx_update(s); 317 } 318 319 static void imx_receive(void *opaque, const uint8_t *buf, int size) 320 { 321 imx_put_data(opaque, *buf); 322 } 323 324 static void imx_event(void *opaque, int event) 325 { 326 if (event == CHR_EVENT_BREAK) { 327 imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); 328 } 329 } 330 331 332 static const struct MemoryRegionOps imx_serial_ops = { 333 .read = imx_serial_read, 334 .write = imx_serial_write, 335 .endianness = DEVICE_NATIVE_ENDIAN, 336 }; 337 338 static void imx_serial_realize(DeviceState *dev, Error **errp) 339 { 340 IMXSerialState *s = IMX_SERIAL(dev); 341 342 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 343 344 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 345 imx_event, NULL, s, NULL, true); 346 } 347 348 static void imx_serial_init(Object *obj) 349 { 350 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 351 IMXSerialState *s = IMX_SERIAL(obj); 352 353 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 354 TYPE_IMX_SERIAL, 0x1000); 355 sysbus_init_mmio(sbd, &s->iomem); 356 sysbus_init_irq(sbd, &s->irq); 357 } 358 359 static Property imx_serial_properties[] = { 360 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 361 DEFINE_PROP_END_OF_LIST(), 362 }; 363 364 static void imx_serial_class_init(ObjectClass *klass, void *data) 365 { 366 DeviceClass *dc = DEVICE_CLASS(klass); 367 368 dc->realize = imx_serial_realize; 369 dc->vmsd = &vmstate_imx_serial; 370 dc->reset = imx_serial_reset_at_boot; 371 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 372 dc->desc = "i.MX series UART"; 373 dc->props = imx_serial_properties; 374 } 375 376 static const TypeInfo imx_serial_info = { 377 .name = TYPE_IMX_SERIAL, 378 .parent = TYPE_SYS_BUS_DEVICE, 379 .instance_size = sizeof(IMXSerialState), 380 .instance_init = imx_serial_init, 381 .class_init = imx_serial_class_init, 382 }; 383 384 static void imx_serial_register_types(void) 385 { 386 type_register_static(&imx_serial_info); 387 } 388 389 type_init(imx_serial_register_types) 390