1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/char.h" 25 #include "qemu/log.h" 26 27 #ifndef DEBUG_IMX_UART 28 #define DEBUG_IMX_UART 0 29 #endif 30 31 #define DPRINTF(fmt, args...) \ 32 do { \ 33 if (DEBUG_IMX_UART) { \ 34 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 35 __func__, ##args); \ 36 } \ 37 } while (0) 38 39 static const VMStateDescription vmstate_imx_serial = { 40 .name = TYPE_IMX_SERIAL, 41 .version_id = 1, 42 .minimum_version_id = 1, 43 .fields = (VMStateField[]) { 44 VMSTATE_INT32(readbuff, IMXSerialState), 45 VMSTATE_UINT32(usr1, IMXSerialState), 46 VMSTATE_UINT32(usr2, IMXSerialState), 47 VMSTATE_UINT32(ucr1, IMXSerialState), 48 VMSTATE_UINT32(uts1, IMXSerialState), 49 VMSTATE_UINT32(onems, IMXSerialState), 50 VMSTATE_UINT32(ufcr, IMXSerialState), 51 VMSTATE_UINT32(ubmr, IMXSerialState), 52 VMSTATE_UINT32(ubrc, IMXSerialState), 53 VMSTATE_UINT32(ucr3, IMXSerialState), 54 VMSTATE_END_OF_LIST() 55 }, 56 }; 57 58 static void imx_update(IMXSerialState *s) 59 { 60 uint32_t flags; 61 62 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 63 if (s->ucr1 & UCR1_TXMPTYEN) { 64 flags |= (s->uts1 & UTS1_TXEMPTY); 65 } else { 66 flags &= ~USR1_TRDY; 67 } 68 69 qemu_set_irq(s->irq, !!flags); 70 } 71 72 static void imx_serial_reset(IMXSerialState *s) 73 { 74 75 s->usr1 = USR1_TRDY | USR1_RXDS; 76 /* 77 * Fake attachment of a terminal: assert RTS. 78 */ 79 s->usr1 |= USR1_RTSS; 80 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 81 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 82 s->ucr1 = 0; 83 s->ucr2 = UCR2_SRST; 84 s->ucr3 = 0x700; 85 s->ubmr = 0; 86 s->ubrc = 4; 87 s->readbuff = URXD_ERR; 88 } 89 90 static void imx_serial_reset_at_boot(DeviceState *dev) 91 { 92 IMXSerialState *s = IMX_SERIAL(dev); 93 94 imx_serial_reset(s); 95 96 /* 97 * enable the uart on boot, so messages from the linux decompresser 98 * are visible. On real hardware this is done by the boot rom 99 * before anything else is loaded. 100 */ 101 s->ucr1 = UCR1_UARTEN; 102 s->ucr2 = UCR2_TXEN; 103 104 } 105 106 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 107 unsigned size) 108 { 109 IMXSerialState *s = (IMXSerialState *)opaque; 110 uint32_t c; 111 112 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 113 114 switch (offset >> 2) { 115 case 0x0: /* URXD */ 116 c = s->readbuff; 117 if (!(s->uts1 & UTS1_RXEMPTY)) { 118 /* Character is valid */ 119 c |= URXD_CHARRDY; 120 s->usr1 &= ~USR1_RRDY; 121 s->usr2 &= ~USR2_RDR; 122 s->uts1 |= UTS1_RXEMPTY; 123 imx_update(s); 124 qemu_chr_fe_accept_input(&s->chr); 125 } 126 return c; 127 128 case 0x20: /* UCR1 */ 129 return s->ucr1; 130 131 case 0x21: /* UCR2 */ 132 return s->ucr2; 133 134 case 0x25: /* USR1 */ 135 return s->usr1; 136 137 case 0x26: /* USR2 */ 138 return s->usr2; 139 140 case 0x2A: /* BRM Modulator */ 141 return s->ubmr; 142 143 case 0x2B: /* Baud Rate Count */ 144 return s->ubrc; 145 146 case 0x2d: /* Test register */ 147 return s->uts1; 148 149 case 0x24: /* UFCR */ 150 return s->ufcr; 151 152 case 0x2c: 153 return s->onems; 154 155 case 0x22: /* UCR3 */ 156 return s->ucr3; 157 158 case 0x23: /* UCR4 */ 159 case 0x29: /* BRM Incremental */ 160 return 0x0; /* TODO */ 161 162 default: 163 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 164 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 165 return 0; 166 } 167 } 168 169 static void imx_serial_write(void *opaque, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 IMXSerialState *s = (IMXSerialState *)opaque; 173 CharDriverState *chr = qemu_chr_fe_get_driver(&s->chr); 174 unsigned char ch; 175 176 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 177 offset, (unsigned int)value, chr ? chr->label : "NODEV"); 178 179 switch (offset >> 2) { 180 case 0x10: /* UTXD */ 181 ch = value; 182 if (s->ucr2 & UCR2_TXEN) { 183 /* XXX this blocks entire thread. Rewrite to use 184 * qemu_chr_fe_write and background I/O callbacks */ 185 qemu_chr_fe_write_all(&s->chr, &ch, 1); 186 s->usr1 &= ~USR1_TRDY; 187 imx_update(s); 188 s->usr1 |= USR1_TRDY; 189 imx_update(s); 190 } 191 break; 192 193 case 0x20: /* UCR1 */ 194 s->ucr1 = value & 0xffff; 195 196 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 197 198 imx_update(s); 199 break; 200 201 case 0x21: /* UCR2 */ 202 /* 203 * Only a few bits in control register 2 are implemented as yet. 204 * If it's intended to use a real serial device as a back-end, this 205 * register will have to be implemented more fully. 206 */ 207 if (!(value & UCR2_SRST)) { 208 imx_serial_reset(s); 209 imx_update(s); 210 value |= UCR2_SRST; 211 } 212 if (value & UCR2_RXEN) { 213 if (!(s->ucr2 & UCR2_RXEN)) { 214 qemu_chr_fe_accept_input(&s->chr); 215 } 216 } 217 s->ucr2 = value & 0xffff; 218 break; 219 220 case 0x25: /* USR1 */ 221 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 222 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 223 s->usr1 &= ~value; 224 break; 225 226 case 0x26: /* USR2 */ 227 /* 228 * Writing 1 to some bits clears them; all other 229 * values are ignored 230 */ 231 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 232 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 233 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 234 s->usr2 &= ~value; 235 break; 236 237 /* 238 * Linux expects to see what it writes to these registers 239 * We don't currently alter the baud rate 240 */ 241 case 0x29: /* UBIR */ 242 s->ubrc = value & 0xffff; 243 break; 244 245 case 0x2a: /* UBMR */ 246 s->ubmr = value & 0xffff; 247 break; 248 249 case 0x2c: /* One ms reg */ 250 s->onems = value & 0xffff; 251 break; 252 253 case 0x24: /* FIFO control register */ 254 s->ufcr = value & 0xffff; 255 break; 256 257 case 0x22: /* UCR3 */ 258 s->ucr3 = value & 0xffff; 259 break; 260 261 case 0x2d: /* UTS1 */ 262 case 0x23: /* UCR4 */ 263 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 264 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 265 /* TODO */ 266 break; 267 268 default: 269 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 270 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 271 } 272 } 273 274 static int imx_can_receive(void *opaque) 275 { 276 IMXSerialState *s = (IMXSerialState *)opaque; 277 return !(s->usr1 & USR1_RRDY); 278 } 279 280 static void imx_put_data(void *opaque, uint32_t value) 281 { 282 IMXSerialState *s = (IMXSerialState *)opaque; 283 284 DPRINTF("received char\n"); 285 286 s->usr1 |= USR1_RRDY; 287 s->usr2 |= USR2_RDR; 288 s->uts1 &= ~UTS1_RXEMPTY; 289 s->readbuff = value; 290 imx_update(s); 291 } 292 293 static void imx_receive(void *opaque, const uint8_t *buf, int size) 294 { 295 imx_put_data(opaque, *buf); 296 } 297 298 static void imx_event(void *opaque, int event) 299 { 300 if (event == CHR_EVENT_BREAK) { 301 imx_put_data(opaque, URXD_BRK); 302 } 303 } 304 305 306 static const struct MemoryRegionOps imx_serial_ops = { 307 .read = imx_serial_read, 308 .write = imx_serial_write, 309 .endianness = DEVICE_NATIVE_ENDIAN, 310 }; 311 312 static void imx_serial_realize(DeviceState *dev, Error **errp) 313 { 314 IMXSerialState *s = IMX_SERIAL(dev); 315 316 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 317 318 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 319 imx_event, s, NULL, true); 320 } 321 322 static void imx_serial_init(Object *obj) 323 { 324 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 325 IMXSerialState *s = IMX_SERIAL(obj); 326 327 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 328 TYPE_IMX_SERIAL, 0x1000); 329 sysbus_init_mmio(sbd, &s->iomem); 330 sysbus_init_irq(sbd, &s->irq); 331 } 332 333 static Property imx_serial_properties[] = { 334 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 335 DEFINE_PROP_END_OF_LIST(), 336 }; 337 338 static void imx_serial_class_init(ObjectClass *klass, void *data) 339 { 340 DeviceClass *dc = DEVICE_CLASS(klass); 341 342 dc->realize = imx_serial_realize; 343 dc->vmsd = &vmstate_imx_serial; 344 dc->reset = imx_serial_reset_at_boot; 345 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 346 dc->desc = "i.MX series UART"; 347 dc->props = imx_serial_properties; 348 } 349 350 static const TypeInfo imx_serial_info = { 351 .name = TYPE_IMX_SERIAL, 352 .parent = TYPE_SYS_BUS_DEVICE, 353 .instance_size = sizeof(IMXSerialState), 354 .instance_init = imx_serial_init, 355 .class_init = imx_serial_class_init, 356 }; 357 358 static void imx_serial_register_types(void) 359 { 360 type_register_static(&imx_serial_info); 361 } 362 363 type_init(imx_serial_register_types) 364