1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/char.h" 25 26 #ifndef DEBUG_IMX_UART 27 #define DEBUG_IMX_UART 0 28 #endif 29 30 #define DPRINTF(fmt, args...) \ 31 do { \ 32 if (DEBUG_IMX_UART) { \ 33 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 34 __func__, ##args); \ 35 } \ 36 } while (0) 37 38 static const VMStateDescription vmstate_imx_serial = { 39 .name = TYPE_IMX_SERIAL, 40 .version_id = 1, 41 .minimum_version_id = 1, 42 .fields = (VMStateField[]) { 43 VMSTATE_INT32(readbuff, IMXSerialState), 44 VMSTATE_UINT32(usr1, IMXSerialState), 45 VMSTATE_UINT32(usr2, IMXSerialState), 46 VMSTATE_UINT32(ucr1, IMXSerialState), 47 VMSTATE_UINT32(uts1, IMXSerialState), 48 VMSTATE_UINT32(onems, IMXSerialState), 49 VMSTATE_UINT32(ufcr, IMXSerialState), 50 VMSTATE_UINT32(ubmr, IMXSerialState), 51 VMSTATE_UINT32(ubrc, IMXSerialState), 52 VMSTATE_UINT32(ucr3, IMXSerialState), 53 VMSTATE_END_OF_LIST() 54 }, 55 }; 56 57 static void imx_update(IMXSerialState *s) 58 { 59 uint32_t flags; 60 61 flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); 62 if (s->ucr1 & UCR1_TXMPTYEN) { 63 flags |= (s->uts1 & UTS1_TXEMPTY); 64 } else { 65 flags &= ~USR1_TRDY; 66 } 67 68 qemu_set_irq(s->irq, !!flags); 69 } 70 71 static void imx_serial_reset(IMXSerialState *s) 72 { 73 74 s->usr1 = USR1_TRDY | USR1_RXDS; 75 /* 76 * Fake attachment of a terminal: assert RTS. 77 */ 78 s->usr1 |= USR1_RTSS; 79 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 80 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 81 s->ucr1 = 0; 82 s->ucr2 = UCR2_SRST; 83 s->ucr3 = 0x700; 84 s->ubmr = 0; 85 s->ubrc = 4; 86 s->readbuff = URXD_ERR; 87 } 88 89 static void imx_serial_reset_at_boot(DeviceState *dev) 90 { 91 IMXSerialState *s = IMX_SERIAL(dev); 92 93 imx_serial_reset(s); 94 95 /* 96 * enable the uart on boot, so messages from the linux decompresser 97 * are visible. On real hardware this is done by the boot rom 98 * before anything else is loaded. 99 */ 100 s->ucr1 = UCR1_UARTEN; 101 s->ucr2 = UCR2_TXEN; 102 103 } 104 105 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 106 unsigned size) 107 { 108 IMXSerialState *s = (IMXSerialState *)opaque; 109 uint32_t c; 110 111 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 112 113 switch (offset >> 2) { 114 case 0x0: /* URXD */ 115 c = s->readbuff; 116 if (!(s->uts1 & UTS1_RXEMPTY)) { 117 /* Character is valid */ 118 c |= URXD_CHARRDY; 119 s->usr1 &= ~USR1_RRDY; 120 s->usr2 &= ~USR2_RDR; 121 s->uts1 |= UTS1_RXEMPTY; 122 imx_update(s); 123 if (s->chr) { 124 qemu_chr_accept_input(s->chr); 125 } 126 } 127 return c; 128 129 case 0x20: /* UCR1 */ 130 return s->ucr1; 131 132 case 0x21: /* UCR2 */ 133 return s->ucr2; 134 135 case 0x25: /* USR1 */ 136 return s->usr1; 137 138 case 0x26: /* USR2 */ 139 return s->usr2; 140 141 case 0x2A: /* BRM Modulator */ 142 return s->ubmr; 143 144 case 0x2B: /* Baud Rate Count */ 145 return s->ubrc; 146 147 case 0x2d: /* Test register */ 148 return s->uts1; 149 150 case 0x24: /* UFCR */ 151 return s->ufcr; 152 153 case 0x2c: 154 return s->onems; 155 156 case 0x22: /* UCR3 */ 157 return s->ucr3; 158 159 case 0x23: /* UCR4 */ 160 case 0x29: /* BRM Incremental */ 161 return 0x0; /* TODO */ 162 163 default: 164 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 165 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 166 return 0; 167 } 168 } 169 170 static void imx_serial_write(void *opaque, hwaddr offset, 171 uint64_t value, unsigned size) 172 { 173 IMXSerialState *s = (IMXSerialState *)opaque; 174 unsigned char ch; 175 176 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 177 offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV"); 178 179 switch (offset >> 2) { 180 case 0x10: /* UTXD */ 181 ch = value; 182 if (s->ucr2 & UCR2_TXEN) { 183 if (s->chr) { 184 qemu_chr_fe_write(s->chr, &ch, 1); 185 } 186 s->usr1 &= ~USR1_TRDY; 187 imx_update(s); 188 s->usr1 |= USR1_TRDY; 189 imx_update(s); 190 } 191 break; 192 193 case 0x20: /* UCR1 */ 194 s->ucr1 = value & 0xffff; 195 196 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 197 198 imx_update(s); 199 break; 200 201 case 0x21: /* UCR2 */ 202 /* 203 * Only a few bits in control register 2 are implemented as yet. 204 * If it's intended to use a real serial device as a back-end, this 205 * register will have to be implemented more fully. 206 */ 207 if (!(value & UCR2_SRST)) { 208 imx_serial_reset(s); 209 imx_update(s); 210 value |= UCR2_SRST; 211 } 212 if (value & UCR2_RXEN) { 213 if (!(s->ucr2 & UCR2_RXEN)) { 214 if (s->chr) { 215 qemu_chr_accept_input(s->chr); 216 } 217 } 218 } 219 s->ucr2 = value & 0xffff; 220 break; 221 222 case 0x25: /* USR1 */ 223 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 224 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 225 s->usr1 &= ~value; 226 break; 227 228 case 0x26: /* USR2 */ 229 /* 230 * Writing 1 to some bits clears them; all other 231 * values are ignored 232 */ 233 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 234 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 235 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 236 s->usr2 &= ~value; 237 break; 238 239 /* 240 * Linux expects to see what it writes to these registers 241 * We don't currently alter the baud rate 242 */ 243 case 0x29: /* UBIR */ 244 s->ubrc = value & 0xffff; 245 break; 246 247 case 0x2a: /* UBMR */ 248 s->ubmr = value & 0xffff; 249 break; 250 251 case 0x2c: /* One ms reg */ 252 s->onems = value & 0xffff; 253 break; 254 255 case 0x24: /* FIFO control register */ 256 s->ufcr = value & 0xffff; 257 break; 258 259 case 0x22: /* UCR3 */ 260 s->ucr3 = value & 0xffff; 261 break; 262 263 case 0x2d: /* UTS1 */ 264 case 0x23: /* UCR4 */ 265 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 266 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 267 /* TODO */ 268 break; 269 270 default: 271 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 272 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 273 } 274 } 275 276 static int imx_can_receive(void *opaque) 277 { 278 IMXSerialState *s = (IMXSerialState *)opaque; 279 return !(s->usr1 & USR1_RRDY); 280 } 281 282 static void imx_put_data(void *opaque, uint32_t value) 283 { 284 IMXSerialState *s = (IMXSerialState *)opaque; 285 286 DPRINTF("received char\n"); 287 288 s->usr1 |= USR1_RRDY; 289 s->usr2 |= USR2_RDR; 290 s->uts1 &= ~UTS1_RXEMPTY; 291 s->readbuff = value; 292 imx_update(s); 293 } 294 295 static void imx_receive(void *opaque, const uint8_t *buf, int size) 296 { 297 imx_put_data(opaque, *buf); 298 } 299 300 static void imx_event(void *opaque, int event) 301 { 302 if (event == CHR_EVENT_BREAK) { 303 imx_put_data(opaque, URXD_BRK); 304 } 305 } 306 307 308 static const struct MemoryRegionOps imx_serial_ops = { 309 .read = imx_serial_read, 310 .write = imx_serial_write, 311 .endianness = DEVICE_NATIVE_ENDIAN, 312 }; 313 314 static void imx_serial_realize(DeviceState *dev, Error **errp) 315 { 316 IMXSerialState *s = IMX_SERIAL(dev); 317 318 if (s->chr) { 319 qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, 320 imx_event, s); 321 } else { 322 DPRINTF("No char dev for uart\n"); 323 } 324 } 325 326 static void imx_serial_init(Object *obj) 327 { 328 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 329 IMXSerialState *s = IMX_SERIAL(obj); 330 331 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 332 TYPE_IMX_SERIAL, 0x1000); 333 sysbus_init_mmio(sbd, &s->iomem); 334 sysbus_init_irq(sbd, &s->irq); 335 } 336 337 static Property imx_serial_properties[] = { 338 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 339 DEFINE_PROP_END_OF_LIST(), 340 }; 341 342 static void imx_serial_class_init(ObjectClass *klass, void *data) 343 { 344 DeviceClass *dc = DEVICE_CLASS(klass); 345 346 dc->realize = imx_serial_realize; 347 dc->vmsd = &vmstate_imx_serial; 348 dc->reset = imx_serial_reset_at_boot; 349 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 350 dc->desc = "i.MX series UART"; 351 dc->props = imx_serial_properties; 352 } 353 354 static const TypeInfo imx_serial_info = { 355 .name = TYPE_IMX_SERIAL, 356 .parent = TYPE_SYS_BUS_DEVICE, 357 .instance_size = sizeof(IMXSerialState), 358 .instance_init = imx_serial_init, 359 .class_init = imx_serial_class_init, 360 }; 361 362 static void imx_serial_register_types(void) 363 { 364 type_register_static(&imx_serial_info); 365 } 366 367 type_init(imx_serial_register_types) 368