1 /* 2 * QEMU lowRISC Ibex UART device 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * For details check the documentation here: 7 * https://docs.opentitan.org/hw/ip/uart/doc/ 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/char/ibex_uart.h" 30 #include "hw/irq.h" 31 #include "hw/qdev-clock.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-properties-system.h" 34 #include "migration/vmstate.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 38 REG32(INTR_STATE, 0x00) 39 FIELD(INTR_STATE, TX_WATERMARK, 0, 1) 40 FIELD(INTR_STATE, RX_WATERMARK, 1, 1) 41 FIELD(INTR_STATE, TX_EMPTY, 2, 1) 42 FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) 43 REG32(INTR_ENABLE, 0x04) 44 REG32(INTR_TEST, 0x08) 45 REG32(ALERT_TEST, 0x0C) 46 REG32(CTRL, 0x10) 47 FIELD(CTRL, TX_ENABLE, 0, 1) 48 FIELD(CTRL, RX_ENABLE, 1, 1) 49 FIELD(CTRL, NF, 2, 1) 50 FIELD(CTRL, SLPBK, 4, 1) 51 FIELD(CTRL, LLPBK, 5, 1) 52 FIELD(CTRL, PARITY_EN, 6, 1) 53 FIELD(CTRL, PARITY_ODD, 7, 1) 54 FIELD(CTRL, RXBLVL, 8, 2) 55 FIELD(CTRL, NCO, 16, 16) 56 REG32(STATUS, 0x14) 57 FIELD(STATUS, TXFULL, 0, 1) 58 FIELD(STATUS, RXFULL, 1, 1) 59 FIELD(STATUS, TXEMPTY, 2, 1) 60 FIELD(STATUS, RXIDLE, 4, 1) 61 FIELD(STATUS, RXEMPTY, 5, 1) 62 REG32(RDATA, 0x18) 63 REG32(WDATA, 0x1C) 64 REG32(FIFO_CTRL, 0x20) 65 FIELD(FIFO_CTRL, RXRST, 0, 1) 66 FIELD(FIFO_CTRL, TXRST, 1, 1) 67 FIELD(FIFO_CTRL, RXILVL, 2, 3) 68 FIELD(FIFO_CTRL, TXILVL, 5, 2) 69 REG32(FIFO_STATUS, 0x24) 70 FIELD(FIFO_STATUS, TXLVL, 0, 5) 71 FIELD(FIFO_STATUS, RXLVL, 16, 5) 72 REG32(OVRD, 0x28) 73 REG32(VAL, 0x2C) 74 REG32(TIMEOUT_CTRL, 0x30) 75 76 static void ibex_uart_update_irqs(IbexUartState *s) 77 { 78 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { 79 qemu_set_irq(s->tx_watermark, 1); 80 } else { 81 qemu_set_irq(s->tx_watermark, 0); 82 } 83 84 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { 85 qemu_set_irq(s->rx_watermark, 1); 86 } else { 87 qemu_set_irq(s->rx_watermark, 0); 88 } 89 90 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) { 91 qemu_set_irq(s->tx_empty, 1); 92 } else { 93 qemu_set_irq(s->tx_empty, 0); 94 } 95 96 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) { 97 qemu_set_irq(s->rx_overflow, 1); 98 } else { 99 qemu_set_irq(s->rx_overflow, 0); 100 } 101 } 102 103 static int ibex_uart_can_receive(void *opaque) 104 { 105 IbexUartState *s = opaque; 106 107 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) 108 && !(s->uart_status & R_STATUS_RXFULL_MASK)) { 109 return 1; 110 } 111 112 return 0; 113 } 114 115 static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) 116 { 117 IbexUartState *s = opaque; 118 uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK) 119 >> R_FIFO_CTRL_RXILVL_SHIFT; 120 121 s->uart_rdata = *buf; 122 123 s->uart_status &= ~R_STATUS_RXIDLE_MASK; 124 s->uart_status &= ~R_STATUS_RXEMPTY_MASK; 125 /* The RXFULL is set after receiving a single byte 126 * as the FIFO buffers are not yet implemented. 127 */ 128 s->uart_status |= R_STATUS_RXFULL_MASK; 129 s->rx_level += 1; 130 131 if (size > rx_fifo_level) { 132 s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; 133 } 134 135 ibex_uart_update_irqs(s); 136 } 137 138 static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond, 139 void *opaque) 140 { 141 IbexUartState *s = opaque; 142 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 143 >> R_FIFO_CTRL_TXILVL_SHIFT; 144 int ret; 145 146 /* instant drain the fifo when there's no back-end */ 147 if (!qemu_chr_fe_backend_connected(&s->chr)) { 148 s->tx_level = 0; 149 return FALSE; 150 } 151 152 if (!s->tx_level) { 153 s->uart_status &= ~R_STATUS_TXFULL_MASK; 154 s->uart_status |= R_STATUS_TXEMPTY_MASK; 155 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 156 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 157 ibex_uart_update_irqs(s); 158 return FALSE; 159 } 160 161 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); 162 163 if (ret >= 0) { 164 s->tx_level -= ret; 165 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); 166 } 167 168 if (s->tx_level) { 169 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 170 ibex_uart_xmit, s); 171 if (!r) { 172 s->tx_level = 0; 173 return FALSE; 174 } 175 } 176 177 /* Clear the TX Full bit */ 178 if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) { 179 s->uart_status &= ~R_STATUS_TXFULL_MASK; 180 } 181 182 /* Disable the TX_WATERMARK IRQ */ 183 if (s->tx_level < tx_fifo_level) { 184 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 185 } 186 187 /* Set TX empty */ 188 if (s->tx_level == 0) { 189 s->uart_status |= R_STATUS_TXEMPTY_MASK; 190 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 191 } 192 193 ibex_uart_update_irqs(s); 194 return FALSE; 195 } 196 197 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, 198 int size) 199 { 200 uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 201 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 202 >> R_FIFO_CTRL_TXILVL_SHIFT; 203 204 if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) { 205 size = IBEX_UART_TX_FIFO_SIZE - s->tx_level; 206 qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow"); 207 } 208 209 memcpy(s->tx_fifo + s->tx_level, buf, size); 210 s->tx_level += size; 211 212 if (s->tx_level > 0) { 213 s->uart_status &= ~R_STATUS_TXEMPTY_MASK; 214 } 215 216 if (s->tx_level >= tx_fifo_level) { 217 s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK; 218 ibex_uart_update_irqs(s); 219 } 220 221 if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) { 222 s->uart_status |= R_STATUS_TXFULL_MASK; 223 } 224 225 timer_mod(s->fifo_trigger_handle, current_time + 226 (s->char_tx_time * 4)); 227 } 228 229 static void ibex_uart_reset(DeviceState *dev) 230 { 231 IbexUartState *s = IBEX_UART(dev); 232 233 s->uart_intr_state = 0x00000000; 234 s->uart_intr_state = 0x00000000; 235 s->uart_intr_enable = 0x00000000; 236 s->uart_ctrl = 0x00000000; 237 s->uart_status = 0x0000003c; 238 s->uart_rdata = 0x00000000; 239 s->uart_fifo_ctrl = 0x00000000; 240 s->uart_fifo_status = 0x00000000; 241 s->uart_ovrd = 0x00000000; 242 s->uart_val = 0x00000000; 243 s->uart_timeout_ctrl = 0x00000000; 244 245 s->tx_level = 0; 246 s->rx_level = 0; 247 248 s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; 249 250 ibex_uart_update_irqs(s); 251 } 252 253 static uint64_t ibex_uart_get_baud(IbexUartState *s) 254 { 255 uint64_t baud; 256 257 baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16); 258 baud *= clock_get_hz(s->f_clk); 259 baud >>= 20; 260 261 return baud; 262 } 263 264 static uint64_t ibex_uart_read(void *opaque, hwaddr addr, 265 unsigned int size) 266 { 267 IbexUartState *s = opaque; 268 uint64_t retvalue = 0; 269 270 switch (addr >> 2) { 271 case R_INTR_STATE: 272 retvalue = s->uart_intr_state; 273 break; 274 case R_INTR_ENABLE: 275 retvalue = s->uart_intr_enable; 276 break; 277 case R_INTR_TEST: 278 qemu_log_mask(LOG_GUEST_ERROR, 279 "%s: wdata is write only\n", __func__); 280 break; 281 282 case R_CTRL: 283 retvalue = s->uart_ctrl; 284 break; 285 case R_STATUS: 286 retvalue = s->uart_status; 287 break; 288 289 case R_RDATA: 290 retvalue = s->uart_rdata; 291 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { 292 qemu_chr_fe_accept_input(&s->chr); 293 294 s->rx_level -= 1; 295 s->uart_status &= ~R_STATUS_RXFULL_MASK; 296 if (s->rx_level == 0) { 297 s->uart_status |= R_STATUS_RXIDLE_MASK; 298 s->uart_status |= R_STATUS_RXEMPTY_MASK; 299 } 300 } 301 break; 302 case R_WDATA: 303 qemu_log_mask(LOG_GUEST_ERROR, 304 "%s: wdata is write only\n", __func__); 305 break; 306 307 case R_FIFO_CTRL: 308 retvalue = s->uart_fifo_ctrl; 309 break; 310 case R_FIFO_STATUS: 311 retvalue = s->uart_fifo_status; 312 313 retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; 314 retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; 315 316 qemu_log_mask(LOG_UNIMP, 317 "%s: RX fifos are not supported\n", __func__); 318 break; 319 320 case R_OVRD: 321 retvalue = s->uart_ovrd; 322 qemu_log_mask(LOG_UNIMP, 323 "%s: ovrd is not supported\n", __func__); 324 break; 325 case R_VAL: 326 retvalue = s->uart_val; 327 qemu_log_mask(LOG_UNIMP, 328 "%s: val is not supported\n", __func__); 329 break; 330 case R_TIMEOUT_CTRL: 331 retvalue = s->uart_timeout_ctrl; 332 qemu_log_mask(LOG_UNIMP, 333 "%s: timeout_ctrl is not supported\n", __func__); 334 break; 335 default: 336 qemu_log_mask(LOG_GUEST_ERROR, 337 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 338 return 0; 339 } 340 341 return retvalue; 342 } 343 344 static void ibex_uart_write(void *opaque, hwaddr addr, 345 uint64_t val64, unsigned int size) 346 { 347 IbexUartState *s = opaque; 348 uint32_t value = val64; 349 350 switch (addr >> 2) { 351 case R_INTR_STATE: 352 /* Write 1 clear */ 353 s->uart_intr_state &= ~value; 354 ibex_uart_update_irqs(s); 355 break; 356 case R_INTR_ENABLE: 357 s->uart_intr_enable = value; 358 ibex_uart_update_irqs(s); 359 break; 360 case R_INTR_TEST: 361 s->uart_intr_state |= value; 362 ibex_uart_update_irqs(s); 363 break; 364 365 case R_CTRL: 366 s->uart_ctrl = value; 367 368 if (value & R_CTRL_NF_MASK) { 369 qemu_log_mask(LOG_UNIMP, 370 "%s: UART_CTRL_NF is not supported\n", __func__); 371 } 372 if (value & R_CTRL_SLPBK_MASK) { 373 qemu_log_mask(LOG_UNIMP, 374 "%s: UART_CTRL_SLPBK is not supported\n", __func__); 375 } 376 if (value & R_CTRL_LLPBK_MASK) { 377 qemu_log_mask(LOG_UNIMP, 378 "%s: UART_CTRL_LLPBK is not supported\n", __func__); 379 } 380 if (value & R_CTRL_PARITY_EN_MASK) { 381 qemu_log_mask(LOG_UNIMP, 382 "%s: UART_CTRL_PARITY_EN is not supported\n", 383 __func__); 384 } 385 if (value & R_CTRL_PARITY_ODD_MASK) { 386 qemu_log_mask(LOG_UNIMP, 387 "%s: UART_CTRL_PARITY_ODD is not supported\n", 388 __func__); 389 } 390 if (value & R_CTRL_RXBLVL_MASK) { 391 qemu_log_mask(LOG_UNIMP, 392 "%s: UART_CTRL_RXBLVL is not supported\n", __func__); 393 } 394 if (value & R_CTRL_NCO_MASK) { 395 uint64_t baud = ibex_uart_get_baud(s); 396 397 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 398 } 399 break; 400 case R_STATUS: 401 qemu_log_mask(LOG_GUEST_ERROR, 402 "%s: status is read only\n", __func__); 403 break; 404 405 case R_RDATA: 406 qemu_log_mask(LOG_GUEST_ERROR, 407 "%s: rdata is read only\n", __func__); 408 break; 409 case R_WDATA: 410 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 411 break; 412 413 case R_FIFO_CTRL: 414 s->uart_fifo_ctrl = value; 415 416 if (value & R_FIFO_CTRL_RXRST_MASK) { 417 s->rx_level = 0; 418 qemu_log_mask(LOG_UNIMP, 419 "%s: RX fifos are not supported\n", __func__); 420 } 421 if (value & R_FIFO_CTRL_TXRST_MASK) { 422 s->tx_level = 0; 423 } 424 break; 425 case R_FIFO_STATUS: 426 qemu_log_mask(LOG_GUEST_ERROR, 427 "%s: fifo_status is read only\n", __func__); 428 break; 429 430 case R_OVRD: 431 s->uart_ovrd = value; 432 qemu_log_mask(LOG_UNIMP, 433 "%s: ovrd is not supported\n", __func__); 434 break; 435 case R_VAL: 436 qemu_log_mask(LOG_GUEST_ERROR, 437 "%s: val is read only\n", __func__); 438 break; 439 case R_TIMEOUT_CTRL: 440 s->uart_timeout_ctrl = value; 441 qemu_log_mask(LOG_UNIMP, 442 "%s: timeout_ctrl is not supported\n", __func__); 443 break; 444 default: 445 qemu_log_mask(LOG_GUEST_ERROR, 446 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 447 } 448 } 449 450 static void ibex_uart_clk_update(void *opaque, ClockEvent event) 451 { 452 IbexUartState *s = opaque; 453 454 /* recompute uart's speed on clock change */ 455 uint64_t baud = ibex_uart_get_baud(s); 456 457 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 458 } 459 460 static void fifo_trigger_update(void *opaque) 461 { 462 IbexUartState *s = opaque; 463 464 if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) { 465 ibex_uart_xmit(NULL, G_IO_OUT, s); 466 } 467 } 468 469 static const MemoryRegionOps ibex_uart_ops = { 470 .read = ibex_uart_read, 471 .write = ibex_uart_write, 472 .endianness = DEVICE_NATIVE_ENDIAN, 473 .impl.min_access_size = 4, 474 .impl.max_access_size = 4, 475 }; 476 477 static int ibex_uart_post_load(void *opaque, int version_id) 478 { 479 IbexUartState *s = opaque; 480 481 ibex_uart_update_irqs(s); 482 return 0; 483 } 484 485 static const VMStateDescription vmstate_ibex_uart = { 486 .name = TYPE_IBEX_UART, 487 .version_id = 1, 488 .minimum_version_id = 1, 489 .post_load = ibex_uart_post_load, 490 .fields = (VMStateField[]) { 491 VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState, 492 IBEX_UART_TX_FIFO_SIZE), 493 VMSTATE_UINT32(tx_level, IbexUartState), 494 VMSTATE_UINT64(char_tx_time, IbexUartState), 495 VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState), 496 VMSTATE_UINT32(uart_intr_state, IbexUartState), 497 VMSTATE_UINT32(uart_intr_enable, IbexUartState), 498 VMSTATE_UINT32(uart_ctrl, IbexUartState), 499 VMSTATE_UINT32(uart_status, IbexUartState), 500 VMSTATE_UINT32(uart_rdata, IbexUartState), 501 VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState), 502 VMSTATE_UINT32(uart_fifo_status, IbexUartState), 503 VMSTATE_UINT32(uart_ovrd, IbexUartState), 504 VMSTATE_UINT32(uart_val, IbexUartState), 505 VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState), 506 VMSTATE_END_OF_LIST() 507 } 508 }; 509 510 static Property ibex_uart_properties[] = { 511 DEFINE_PROP_CHR("chardev", IbexUartState, chr), 512 DEFINE_PROP_END_OF_LIST(), 513 }; 514 515 static void ibex_uart_init(Object *obj) 516 { 517 IbexUartState *s = IBEX_UART(obj); 518 519 s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock", 520 ibex_uart_clk_update, s, ClockUpdate); 521 clock_set_hz(s->f_clk, IBEX_UART_CLOCK); 522 523 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); 524 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); 525 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); 526 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); 527 528 memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s, 529 TYPE_IBEX_UART, 0x400); 530 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 531 } 532 533 static void ibex_uart_realize(DeviceState *dev, Error **errp) 534 { 535 IbexUartState *s = IBEX_UART(dev); 536 537 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 538 fifo_trigger_update, s); 539 540 qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive, 541 ibex_uart_receive, NULL, NULL, 542 s, NULL, true); 543 } 544 545 static void ibex_uart_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 549 dc->reset = ibex_uart_reset; 550 dc->realize = ibex_uart_realize; 551 dc->vmsd = &vmstate_ibex_uart; 552 device_class_set_props(dc, ibex_uart_properties); 553 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 554 } 555 556 static const TypeInfo ibex_uart_info = { 557 .name = TYPE_IBEX_UART, 558 .parent = TYPE_SYS_BUS_DEVICE, 559 .instance_size = sizeof(IbexUartState), 560 .instance_init = ibex_uart_init, 561 .class_init = ibex_uart_class_init, 562 }; 563 564 static void ibex_uart_register_types(void) 565 { 566 type_register_static(&ibex_uart_info); 567 } 568 569 type_init(ibex_uart_register_types) 570