1 /* 2 * QEMU lowRISC Ibex UART device 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * For details check the documentation here: 7 * https://docs.opentitan.org/hw/ip/uart/doc/ 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/char/ibex_uart.h" 30 #include "hw/irq.h" 31 #include "hw/qdev-clock.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-properties-system.h" 34 #include "migration/vmstate.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 38 REG32(INTR_STATE, 0x00) 39 FIELD(INTR_STATE, TX_WATERMARK, 0, 1) 40 FIELD(INTR_STATE, RX_WATERMARK, 1, 1) 41 FIELD(INTR_STATE, TX_EMPTY, 2, 1) 42 FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) 43 REG32(INTR_ENABLE, 0x04) 44 REG32(INTR_TEST, 0x08) 45 REG32(CTRL, 0x0C) 46 FIELD(CTRL, TX_ENABLE, 0, 1) 47 FIELD(CTRL, RX_ENABLE, 1, 1) 48 FIELD(CTRL, NF, 2, 1) 49 FIELD(CTRL, SLPBK, 4, 1) 50 FIELD(CTRL, LLPBK, 5, 1) 51 FIELD(CTRL, PARITY_EN, 6, 1) 52 FIELD(CTRL, PARITY_ODD, 7, 1) 53 FIELD(CTRL, RXBLVL, 8, 2) 54 FIELD(CTRL, NCO, 16, 16) 55 REG32(STATUS, 0x10) 56 FIELD(STATUS, TXFULL, 0, 1) 57 FIELD(STATUS, RXFULL, 1, 1) 58 FIELD(STATUS, TXEMPTY, 2, 1) 59 FIELD(STATUS, RXIDLE, 4, 1) 60 FIELD(STATUS, RXEMPTY, 5, 1) 61 REG32(RDATA, 0x14) 62 REG32(WDATA, 0x18) 63 REG32(FIFO_CTRL, 0x1c) 64 FIELD(FIFO_CTRL, RXRST, 0, 1) 65 FIELD(FIFO_CTRL, TXRST, 1, 1) 66 FIELD(FIFO_CTRL, RXILVL, 2, 3) 67 FIELD(FIFO_CTRL, TXILVL, 5, 2) 68 REG32(FIFO_STATUS, 0x20) 69 FIELD(FIFO_STATUS, TXLVL, 0, 5) 70 FIELD(FIFO_STATUS, RXLVL, 16, 5) 71 REG32(OVRD, 0x24) 72 REG32(VAL, 0x28) 73 REG32(TIMEOUT_CTRL, 0x2c) 74 75 static void ibex_uart_update_irqs(IbexUartState *s) 76 { 77 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { 78 qemu_set_irq(s->tx_watermark, 1); 79 } else { 80 qemu_set_irq(s->tx_watermark, 0); 81 } 82 83 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { 84 qemu_set_irq(s->rx_watermark, 1); 85 } else { 86 qemu_set_irq(s->rx_watermark, 0); 87 } 88 89 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) { 90 qemu_set_irq(s->tx_empty, 1); 91 } else { 92 qemu_set_irq(s->tx_empty, 0); 93 } 94 95 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) { 96 qemu_set_irq(s->rx_overflow, 1); 97 } else { 98 qemu_set_irq(s->rx_overflow, 0); 99 } 100 } 101 102 static int ibex_uart_can_receive(void *opaque) 103 { 104 IbexUartState *s = opaque; 105 106 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) 107 && !(s->uart_status & R_STATUS_RXFULL_MASK)) { 108 return 1; 109 } 110 111 return 0; 112 } 113 114 static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) 115 { 116 IbexUartState *s = opaque; 117 uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK) 118 >> R_FIFO_CTRL_RXILVL_SHIFT; 119 120 s->uart_rdata = *buf; 121 122 s->uart_status &= ~R_STATUS_RXIDLE_MASK; 123 s->uart_status &= ~R_STATUS_RXEMPTY_MASK; 124 /* The RXFULL is set after receiving a single byte 125 * as the FIFO buffers are not yet implemented. 126 */ 127 s->uart_status |= R_STATUS_RXFULL_MASK; 128 s->rx_level += 1; 129 130 if (size > rx_fifo_level) { 131 s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; 132 } 133 134 ibex_uart_update_irqs(s); 135 } 136 137 static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, 138 void *opaque) 139 { 140 IbexUartState *s = opaque; 141 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 142 >> R_FIFO_CTRL_TXILVL_SHIFT; 143 int ret; 144 145 /* instant drain the fifo when there's no back-end */ 146 if (!qemu_chr_fe_backend_connected(&s->chr)) { 147 s->tx_level = 0; 148 return FALSE; 149 } 150 151 if (!s->tx_level) { 152 s->uart_status &= ~R_STATUS_TXFULL_MASK; 153 s->uart_status |= R_STATUS_TXEMPTY_MASK; 154 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 155 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 156 ibex_uart_update_irqs(s); 157 return FALSE; 158 } 159 160 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); 161 162 if (ret >= 0) { 163 s->tx_level -= ret; 164 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); 165 } 166 167 if (s->tx_level) { 168 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 169 ibex_uart_xmit, s); 170 if (!r) { 171 s->tx_level = 0; 172 return FALSE; 173 } 174 } 175 176 /* Clear the TX Full bit */ 177 if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) { 178 s->uart_status &= ~R_STATUS_TXFULL_MASK; 179 } 180 181 /* Disable the TX_WATERMARK IRQ */ 182 if (s->tx_level < tx_fifo_level) { 183 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 184 } 185 186 /* Set TX empty */ 187 if (s->tx_level == 0) { 188 s->uart_status |= R_STATUS_TXEMPTY_MASK; 189 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 190 } 191 192 ibex_uart_update_irqs(s); 193 return FALSE; 194 } 195 196 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, 197 int size) 198 { 199 uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 200 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 201 >> R_FIFO_CTRL_TXILVL_SHIFT; 202 203 if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) { 204 size = IBEX_UART_TX_FIFO_SIZE - s->tx_level; 205 qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow"); 206 } 207 208 memcpy(s->tx_fifo + s->tx_level, buf, size); 209 s->tx_level += size; 210 211 if (s->tx_level > 0) { 212 s->uart_status &= ~R_STATUS_TXEMPTY_MASK; 213 } 214 215 if (s->tx_level >= tx_fifo_level) { 216 s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK; 217 ibex_uart_update_irqs(s); 218 } 219 220 if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) { 221 s->uart_status |= R_STATUS_TXFULL_MASK; 222 } 223 224 timer_mod(s->fifo_trigger_handle, current_time + 225 (s->char_tx_time * 4)); 226 } 227 228 static void ibex_uart_reset(DeviceState *dev) 229 { 230 IbexUartState *s = IBEX_UART(dev); 231 232 s->uart_intr_state = 0x00000000; 233 s->uart_intr_state = 0x00000000; 234 s->uart_intr_enable = 0x00000000; 235 s->uart_ctrl = 0x00000000; 236 s->uart_status = 0x0000003c; 237 s->uart_rdata = 0x00000000; 238 s->uart_fifo_ctrl = 0x00000000; 239 s->uart_fifo_status = 0x00000000; 240 s->uart_ovrd = 0x00000000; 241 s->uart_val = 0x00000000; 242 s->uart_timeout_ctrl = 0x00000000; 243 244 s->tx_level = 0; 245 s->rx_level = 0; 246 247 s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; 248 249 ibex_uart_update_irqs(s); 250 } 251 252 static uint64_t ibex_uart_get_baud(IbexUartState *s) 253 { 254 uint64_t baud; 255 256 baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16); 257 baud *= clock_get_hz(s->f_clk); 258 baud >>= 20; 259 260 return baud; 261 } 262 263 static uint64_t ibex_uart_read(void *opaque, hwaddr addr, 264 unsigned int size) 265 { 266 IbexUartState *s = opaque; 267 uint64_t retvalue = 0; 268 269 switch (addr >> 2) { 270 case R_INTR_STATE: 271 retvalue = s->uart_intr_state; 272 break; 273 case R_INTR_ENABLE: 274 retvalue = s->uart_intr_enable; 275 break; 276 case R_INTR_TEST: 277 qemu_log_mask(LOG_GUEST_ERROR, 278 "%s: wdata is write only\n", __func__); 279 break; 280 281 case R_CTRL: 282 retvalue = s->uart_ctrl; 283 break; 284 case R_STATUS: 285 retvalue = s->uart_status; 286 break; 287 288 case R_RDATA: 289 retvalue = s->uart_rdata; 290 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { 291 qemu_chr_fe_accept_input(&s->chr); 292 293 s->rx_level -= 1; 294 s->uart_status &= ~R_STATUS_RXFULL_MASK; 295 if (s->rx_level == 0) { 296 s->uart_status |= R_STATUS_RXIDLE_MASK; 297 s->uart_status |= R_STATUS_RXEMPTY_MASK; 298 } 299 } 300 break; 301 case R_WDATA: 302 qemu_log_mask(LOG_GUEST_ERROR, 303 "%s: wdata is write only\n", __func__); 304 break; 305 306 case R_FIFO_CTRL: 307 retvalue = s->uart_fifo_ctrl; 308 break; 309 case R_FIFO_STATUS: 310 retvalue = s->uart_fifo_status; 311 312 retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; 313 retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; 314 315 qemu_log_mask(LOG_UNIMP, 316 "%s: RX fifos are not supported\n", __func__); 317 break; 318 319 case R_OVRD: 320 retvalue = s->uart_ovrd; 321 qemu_log_mask(LOG_UNIMP, 322 "%s: ovrd is not supported\n", __func__); 323 break; 324 case R_VAL: 325 retvalue = s->uart_val; 326 qemu_log_mask(LOG_UNIMP, 327 "%s: val is not supported\n", __func__); 328 break; 329 case R_TIMEOUT_CTRL: 330 retvalue = s->uart_timeout_ctrl; 331 qemu_log_mask(LOG_UNIMP, 332 "%s: timeout_ctrl is not supported\n", __func__); 333 break; 334 default: 335 qemu_log_mask(LOG_GUEST_ERROR, 336 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 337 return 0; 338 } 339 340 return retvalue; 341 } 342 343 static void ibex_uart_write(void *opaque, hwaddr addr, 344 uint64_t val64, unsigned int size) 345 { 346 IbexUartState *s = opaque; 347 uint32_t value = val64; 348 349 switch (addr >> 2) { 350 case R_INTR_STATE: 351 /* Write 1 clear */ 352 s->uart_intr_state &= ~value; 353 ibex_uart_update_irqs(s); 354 break; 355 case R_INTR_ENABLE: 356 s->uart_intr_enable = value; 357 ibex_uart_update_irqs(s); 358 break; 359 case R_INTR_TEST: 360 s->uart_intr_state |= value; 361 ibex_uart_update_irqs(s); 362 break; 363 364 case R_CTRL: 365 s->uart_ctrl = value; 366 367 if (value & R_CTRL_NF_MASK) { 368 qemu_log_mask(LOG_UNIMP, 369 "%s: UART_CTRL_NF is not supported\n", __func__); 370 } 371 if (value & R_CTRL_SLPBK_MASK) { 372 qemu_log_mask(LOG_UNIMP, 373 "%s: UART_CTRL_SLPBK is not supported\n", __func__); 374 } 375 if (value & R_CTRL_LLPBK_MASK) { 376 qemu_log_mask(LOG_UNIMP, 377 "%s: UART_CTRL_LLPBK is not supported\n", __func__); 378 } 379 if (value & R_CTRL_PARITY_EN_MASK) { 380 qemu_log_mask(LOG_UNIMP, 381 "%s: UART_CTRL_PARITY_EN is not supported\n", 382 __func__); 383 } 384 if (value & R_CTRL_PARITY_ODD_MASK) { 385 qemu_log_mask(LOG_UNIMP, 386 "%s: UART_CTRL_PARITY_ODD is not supported\n", 387 __func__); 388 } 389 if (value & R_CTRL_RXBLVL_MASK) { 390 qemu_log_mask(LOG_UNIMP, 391 "%s: UART_CTRL_RXBLVL is not supported\n", __func__); 392 } 393 if (value & R_CTRL_NCO_MASK) { 394 uint64_t baud = ibex_uart_get_baud(s); 395 396 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 397 } 398 break; 399 case R_STATUS: 400 qemu_log_mask(LOG_GUEST_ERROR, 401 "%s: status is read only\n", __func__); 402 break; 403 404 case R_RDATA: 405 qemu_log_mask(LOG_GUEST_ERROR, 406 "%s: rdata is read only\n", __func__); 407 break; 408 case R_WDATA: 409 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 410 break; 411 412 case R_FIFO_CTRL: 413 s->uart_fifo_ctrl = value; 414 415 if (value & R_FIFO_CTRL_RXRST_MASK) { 416 s->rx_level = 0; 417 qemu_log_mask(LOG_UNIMP, 418 "%s: RX fifos are not supported\n", __func__); 419 } 420 if (value & R_FIFO_CTRL_TXRST_MASK) { 421 s->tx_level = 0; 422 } 423 break; 424 case R_FIFO_STATUS: 425 qemu_log_mask(LOG_GUEST_ERROR, 426 "%s: fifo_status is read only\n", __func__); 427 break; 428 429 case R_OVRD: 430 s->uart_ovrd = value; 431 qemu_log_mask(LOG_UNIMP, 432 "%s: ovrd is not supported\n", __func__); 433 break; 434 case R_VAL: 435 qemu_log_mask(LOG_GUEST_ERROR, 436 "%s: val is read only\n", __func__); 437 break; 438 case R_TIMEOUT_CTRL: 439 s->uart_timeout_ctrl = value; 440 qemu_log_mask(LOG_UNIMP, 441 "%s: timeout_ctrl is not supported\n", __func__); 442 break; 443 default: 444 qemu_log_mask(LOG_GUEST_ERROR, 445 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 446 } 447 } 448 449 static void ibex_uart_clk_update(void *opaque, ClockEvent event) 450 { 451 IbexUartState *s = opaque; 452 453 /* recompute uart's speed on clock change */ 454 uint64_t baud = ibex_uart_get_baud(s); 455 456 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 457 } 458 459 static void fifo_trigger_update(void *opaque) 460 { 461 IbexUartState *s = opaque; 462 463 if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) { 464 ibex_uart_xmit(NULL, G_IO_OUT, s); 465 } 466 } 467 468 static const MemoryRegionOps ibex_uart_ops = { 469 .read = ibex_uart_read, 470 .write = ibex_uart_write, 471 .endianness = DEVICE_NATIVE_ENDIAN, 472 .impl.min_access_size = 4, 473 .impl.max_access_size = 4, 474 }; 475 476 static int ibex_uart_post_load(void *opaque, int version_id) 477 { 478 IbexUartState *s = opaque; 479 480 ibex_uart_update_irqs(s); 481 return 0; 482 } 483 484 static const VMStateDescription vmstate_ibex_uart = { 485 .name = TYPE_IBEX_UART, 486 .version_id = 1, 487 .minimum_version_id = 1, 488 .post_load = ibex_uart_post_load, 489 .fields = (VMStateField[]) { 490 VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState, 491 IBEX_UART_TX_FIFO_SIZE), 492 VMSTATE_UINT32(tx_level, IbexUartState), 493 VMSTATE_UINT64(char_tx_time, IbexUartState), 494 VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState), 495 VMSTATE_UINT32(uart_intr_state, IbexUartState), 496 VMSTATE_UINT32(uart_intr_enable, IbexUartState), 497 VMSTATE_UINT32(uart_ctrl, IbexUartState), 498 VMSTATE_UINT32(uart_status, IbexUartState), 499 VMSTATE_UINT32(uart_rdata, IbexUartState), 500 VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState), 501 VMSTATE_UINT32(uart_fifo_status, IbexUartState), 502 VMSTATE_UINT32(uart_ovrd, IbexUartState), 503 VMSTATE_UINT32(uart_val, IbexUartState), 504 VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState), 505 VMSTATE_END_OF_LIST() 506 } 507 }; 508 509 static Property ibex_uart_properties[] = { 510 DEFINE_PROP_CHR("chardev", IbexUartState, chr), 511 DEFINE_PROP_END_OF_LIST(), 512 }; 513 514 static void ibex_uart_init(Object *obj) 515 { 516 IbexUartState *s = IBEX_UART(obj); 517 518 s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock", 519 ibex_uart_clk_update, s, ClockUpdate); 520 clock_set_hz(s->f_clk, IBEX_UART_CLOCK); 521 522 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); 523 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); 524 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); 525 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); 526 527 memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s, 528 TYPE_IBEX_UART, 0x400); 529 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 530 } 531 532 static void ibex_uart_realize(DeviceState *dev, Error **errp) 533 { 534 IbexUartState *s = IBEX_UART(dev); 535 536 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 537 fifo_trigger_update, s); 538 539 qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive, 540 ibex_uart_receive, NULL, NULL, 541 s, NULL, true); 542 } 543 544 static void ibex_uart_class_init(ObjectClass *klass, void *data) 545 { 546 DeviceClass *dc = DEVICE_CLASS(klass); 547 548 dc->reset = ibex_uart_reset; 549 dc->realize = ibex_uart_realize; 550 dc->vmsd = &vmstate_ibex_uart; 551 device_class_set_props(dc, ibex_uart_properties); 552 } 553 554 static const TypeInfo ibex_uart_info = { 555 .name = TYPE_IBEX_UART, 556 .parent = TYPE_SYS_BUS_DEVICE, 557 .instance_size = sizeof(IbexUartState), 558 .instance_init = ibex_uart_init, 559 .class_init = ibex_uart_class_init, 560 }; 561 562 static void ibex_uart_register_types(void) 563 { 564 type_register_static(&ibex_uart_info); 565 } 566 567 type_init(ibex_uart_register_types) 568