1 /* 2 * QEMU GRLIB APB UART Emulator 3 * 4 * Copyright (c) 2010-2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "sysemu/char.h" 27 28 #include "trace.h" 29 30 #define UART_REG_SIZE 20 /* Size of memory mapped registers */ 31 32 /* UART status register fields */ 33 #define UART_DATA_READY (1 << 0) 34 #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1) 35 #define UART_TRANSMIT_FIFO_EMPTY (1 << 2) 36 #define UART_BREAK_RECEIVED (1 << 3) 37 #define UART_OVERRUN (1 << 4) 38 #define UART_PARITY_ERROR (1 << 5) 39 #define UART_FRAMING_ERROR (1 << 6) 40 #define UART_TRANSMIT_FIFO_HALF (1 << 7) 41 #define UART_RECEIVE_FIFO_HALF (1 << 8) 42 #define UART_TRANSMIT_FIFO_FULL (1 << 9) 43 #define UART_RECEIVE_FIFO_FULL (1 << 10) 44 45 /* UART control register fields */ 46 #define UART_RECEIVE_ENABLE (1 << 0) 47 #define UART_TRANSMIT_ENABLE (1 << 1) 48 #define UART_RECEIVE_INTERRUPT (1 << 2) 49 #define UART_TRANSMIT_INTERRUPT (1 << 3) 50 #define UART_PARITY_SELECT (1 << 4) 51 #define UART_PARITY_ENABLE (1 << 5) 52 #define UART_FLOW_CONTROL (1 << 6) 53 #define UART_LOOPBACK (1 << 7) 54 #define UART_EXTERNAL_CLOCK (1 << 8) 55 #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9) 56 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10) 57 #define UART_FIFO_DEBUG_MODE (1 << 11) 58 #define UART_OUTPUT_ENABLE (1 << 12) 59 #define UART_FIFO_AVAILABLE (1 << 31) 60 61 /* Memory mapped register offsets */ 62 #define DATA_OFFSET 0x00 63 #define STATUS_OFFSET 0x04 64 #define CONTROL_OFFSET 0x08 65 #define SCALER_OFFSET 0x0C /* not supported */ 66 #define FIFO_DEBUG_OFFSET 0x10 /* not supported */ 67 68 #define FIFO_LENGTH 1024 69 70 typedef struct UART { 71 SysBusDevice busdev; 72 MemoryRegion iomem; 73 qemu_irq irq; 74 75 CharDriverState *chr; 76 77 /* registers */ 78 uint32_t status; 79 uint32_t control; 80 81 /* FIFO */ 82 char buffer[FIFO_LENGTH]; 83 int len; 84 int current; 85 } UART; 86 87 static int uart_data_to_read(UART *uart) 88 { 89 return uart->current < uart->len; 90 } 91 92 static char uart_pop(UART *uart) 93 { 94 char ret; 95 96 if (uart->len == 0) { 97 uart->status &= ~UART_DATA_READY; 98 return 0; 99 } 100 101 ret = uart->buffer[uart->current++]; 102 103 if (uart->current >= uart->len) { 104 /* Flush */ 105 uart->len = 0; 106 uart->current = 0; 107 } 108 109 if (!uart_data_to_read(uart)) { 110 uart->status &= ~UART_DATA_READY; 111 } 112 113 return ret; 114 } 115 116 static void uart_add_to_fifo(UART *uart, 117 const uint8_t *buffer, 118 int length) 119 { 120 if (uart->len + length > FIFO_LENGTH) { 121 abort(); 122 } 123 memcpy(uart->buffer + uart->len, buffer, length); 124 uart->len += length; 125 } 126 127 static int grlib_apbuart_can_receive(void *opaque) 128 { 129 UART *uart = opaque; 130 131 return FIFO_LENGTH - uart->len; 132 } 133 134 static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) 135 { 136 UART *uart = opaque; 137 138 if (uart->control & UART_RECEIVE_ENABLE) { 139 uart_add_to_fifo(uart, buf, size); 140 141 uart->status |= UART_DATA_READY; 142 143 if (uart->control & UART_RECEIVE_INTERRUPT) { 144 qemu_irq_pulse(uart->irq); 145 } 146 } 147 } 148 149 static void grlib_apbuart_event(void *opaque, int event) 150 { 151 trace_grlib_apbuart_event(event); 152 } 153 154 155 static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr, 156 unsigned size) 157 { 158 UART *uart = opaque; 159 160 addr &= 0xff; 161 162 /* Unit registers */ 163 switch (addr) { 164 case DATA_OFFSET: 165 case DATA_OFFSET + 3: /* when only one byte read */ 166 return uart_pop(uart); 167 168 case STATUS_OFFSET: 169 /* Read Only */ 170 return uart->status; 171 172 case CONTROL_OFFSET: 173 return uart->control; 174 175 case SCALER_OFFSET: 176 /* Not supported */ 177 return 0; 178 179 default: 180 trace_grlib_apbuart_readl_unknown(addr); 181 return 0; 182 } 183 } 184 185 static void grlib_apbuart_write(void *opaque, hwaddr addr, 186 uint64_t value, unsigned size) 187 { 188 UART *uart = opaque; 189 unsigned char c = 0; 190 191 addr &= 0xff; 192 193 /* Unit registers */ 194 switch (addr) { 195 case DATA_OFFSET: 196 case DATA_OFFSET + 3: /* When only one byte write */ 197 /* Transmit when character device available and transmitter enabled */ 198 if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) { 199 c = value & 0xFF; 200 qemu_chr_fe_write(uart->chr, &c, 1); 201 /* Generate interrupt */ 202 if (uart->control & UART_TRANSMIT_INTERRUPT) { 203 qemu_irq_pulse(uart->irq); 204 } 205 } 206 return; 207 208 case STATUS_OFFSET: 209 /* Read Only */ 210 return; 211 212 case CONTROL_OFFSET: 213 uart->control = value; 214 return; 215 216 case SCALER_OFFSET: 217 /* Not supported */ 218 return; 219 220 default: 221 break; 222 } 223 224 trace_grlib_apbuart_writel_unknown(addr, value); 225 } 226 227 static const MemoryRegionOps grlib_apbuart_ops = { 228 .write = grlib_apbuart_write, 229 .read = grlib_apbuart_read, 230 .endianness = DEVICE_NATIVE_ENDIAN, 231 }; 232 233 static int grlib_apbuart_init(SysBusDevice *dev) 234 { 235 UART *uart = FROM_SYSBUS(typeof(*uart), dev); 236 237 qemu_chr_add_handlers(uart->chr, 238 grlib_apbuart_can_receive, 239 grlib_apbuart_receive, 240 grlib_apbuart_event, 241 uart); 242 243 sysbus_init_irq(dev, &uart->irq); 244 245 memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart, 246 "uart", UART_REG_SIZE); 247 248 sysbus_init_mmio(dev, &uart->iomem); 249 250 return 0; 251 } 252 253 static void grlib_apbuart_reset(DeviceState *d) 254 { 255 UART *uart = container_of(d, UART, busdev.qdev); 256 257 /* Transmitter FIFO and shift registers are always empty in QEMU */ 258 uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY; 259 /* Everything is off */ 260 uart->control = 0; 261 /* Flush receive FIFO */ 262 uart->len = 0; 263 uart->current = 0; 264 } 265 266 static Property grlib_apbuart_properties[] = { 267 DEFINE_PROP_CHR("chrdev", UART, chr), 268 DEFINE_PROP_END_OF_LIST(), 269 }; 270 271 static void grlib_apbuart_class_init(ObjectClass *klass, void *data) 272 { 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 275 276 k->init = grlib_apbuart_init; 277 dc->reset = grlib_apbuart_reset; 278 dc->props = grlib_apbuart_properties; 279 } 280 281 static const TypeInfo grlib_apbuart_info = { 282 .name = "grlib,apbuart", 283 .parent = TYPE_SYS_BUS_DEVICE, 284 .instance_size = sizeof(UART), 285 .class_init = grlib_apbuart_class_init, 286 }; 287 288 static void grlib_apbuart_register_types(void) 289 { 290 type_register_static(&grlib_apbuart_info); 291 } 292 293 type_init(grlib_apbuart_register_types) 294