1 /* 2 * Exynos4210 UART Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/sysbus.h" 24 #include "qemu/error-report.h" 25 #include "qemu/module.h" 26 #include "sysemu/sysemu.h" 27 #include "chardev/char-fe.h" 28 #include "chardev/char-serial.h" 29 30 #include "hw/arm/exynos4210.h" 31 32 #undef DEBUG_UART 33 #undef DEBUG_UART_EXTEND 34 #undef DEBUG_IRQ 35 #undef DEBUG_Rx_DATA 36 #undef DEBUG_Tx_DATA 37 38 #define DEBUG_UART 0 39 #define DEBUG_UART_EXTEND 0 40 #define DEBUG_IRQ 0 41 #define DEBUG_Rx_DATA 0 42 #define DEBUG_Tx_DATA 0 43 44 #if DEBUG_UART 45 #define PRINT_DEBUG(fmt, args...) \ 46 do { \ 47 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 48 } while (0) 49 50 #if DEBUG_UART_EXTEND 51 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 52 do { \ 53 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 54 } while (0) 55 #else 56 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 57 do {} while (0) 58 #endif /* EXTEND */ 59 60 #else 61 #define PRINT_DEBUG(fmt, args...) \ 62 do {} while (0) 63 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 64 do {} while (0) 65 #endif 66 67 #define PRINT_ERROR(fmt, args...) \ 68 do { \ 69 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 70 } while (0) 71 72 /* 73 * Offsets for UART registers relative to SFR base address 74 * for UARTn 75 * 76 */ 77 #define ULCON 0x0000 /* Line Control */ 78 #define UCON 0x0004 /* Control */ 79 #define UFCON 0x0008 /* FIFO Control */ 80 #define UMCON 0x000C /* Modem Control */ 81 #define UTRSTAT 0x0010 /* Tx/Rx Status */ 82 #define UERSTAT 0x0014 /* UART Error Status */ 83 #define UFSTAT 0x0018 /* FIFO Status */ 84 #define UMSTAT 0x001C /* Modem Status */ 85 #define UTXH 0x0020 /* Transmit Buffer */ 86 #define URXH 0x0024 /* Receive Buffer */ 87 #define UBRDIV 0x0028 /* Baud Rate Divisor */ 88 #define UFRACVAL 0x002C /* Divisor Fractional Value */ 89 #define UINTP 0x0030 /* Interrupt Pending */ 90 #define UINTSP 0x0034 /* Interrupt Source Pending */ 91 #define UINTM 0x0038 /* Interrupt Mask */ 92 93 /* 94 * for indexing register in the uint32_t array 95 * 96 * 'reg' - register offset (see offsets definitions above) 97 * 98 */ 99 #define I_(reg) (reg / sizeof(uint32_t)) 100 101 typedef struct Exynos4210UartReg { 102 const char *name; /* the only reason is the debug output */ 103 hwaddr offset; 104 uint32_t reset_value; 105 } Exynos4210UartReg; 106 107 static const Exynos4210UartReg exynos4210_uart_regs[] = { 108 {"ULCON", ULCON, 0x00000000}, 109 {"UCON", UCON, 0x00003000}, 110 {"UFCON", UFCON, 0x00000000}, 111 {"UMCON", UMCON, 0x00000000}, 112 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 113 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 114 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 115 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 116 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 117 {"URXH", URXH, 0x00000000}, /* RO */ 118 {"UBRDIV", UBRDIV, 0x00000000}, 119 {"UFRACVAL", UFRACVAL, 0x00000000}, 120 {"UINTP", UINTP, 0x00000000}, 121 {"UINTSP", UINTSP, 0x00000000}, 122 {"UINTM", UINTM, 0x00000000}, 123 }; 124 125 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 126 127 /* UART FIFO Control */ 128 #define UFCON_FIFO_ENABLE 0x1 129 #define UFCON_Rx_FIFO_RESET 0x2 130 #define UFCON_Tx_FIFO_RESET 0x4 131 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 132 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 133 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 134 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 135 136 /* Uart FIFO Status */ 137 #define UFSTAT_Rx_FIFO_COUNT 0xff 138 #define UFSTAT_Rx_FIFO_FULL 0x100 139 #define UFSTAT_Rx_FIFO_ERROR 0x200 140 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 141 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 142 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 143 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 144 145 /* UART Interrupt Source Pending */ 146 #define UINTSP_RXD 0x1 /* Receive interrupt */ 147 #define UINTSP_ERROR 0x2 /* Error interrupt */ 148 #define UINTSP_TXD 0x4 /* Transmit interrupt */ 149 #define UINTSP_MODEM 0x8 /* Modem interrupt */ 150 151 /* UART Line Control */ 152 #define ULCON_IR_MODE_SHIFT 6 153 #define ULCON_PARITY_SHIFT 3 154 #define ULCON_STOP_BIT_SHIFT 1 155 156 /* UART Tx/Rx Status */ 157 #define UTRSTAT_TRANSMITTER_EMPTY 0x4 158 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 159 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 160 161 /* UART Error Status */ 162 #define UERSTAT_OVERRUN 0x1 163 #define UERSTAT_PARITY 0x2 164 #define UERSTAT_FRAME 0x4 165 #define UERSTAT_BREAK 0x8 166 167 typedef struct { 168 uint8_t *data; 169 uint32_t sp, rp; /* store and retrieve pointers */ 170 uint32_t size; 171 } Exynos4210UartFIFO; 172 173 #define TYPE_EXYNOS4210_UART "exynos4210.uart" 174 #define EXYNOS4210_UART(obj) \ 175 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 176 177 typedef struct Exynos4210UartState { 178 SysBusDevice parent_obj; 179 180 MemoryRegion iomem; 181 182 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 183 Exynos4210UartFIFO rx; 184 Exynos4210UartFIFO tx; 185 186 CharBackend chr; 187 qemu_irq irq; 188 189 uint32_t channel; 190 191 } Exynos4210UartState; 192 193 194 #if DEBUG_UART 195 /* Used only for debugging inside PRINT_DEBUG_... macros */ 196 static const char *exynos4210_uart_regname(hwaddr offset) 197 { 198 199 int i; 200 201 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 202 if (offset == exynos4210_uart_regs[i].offset) { 203 return exynos4210_uart_regs[i].name; 204 } 205 } 206 207 return NULL; 208 } 209 #endif 210 211 212 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 213 { 214 q->data[q->sp] = ch; 215 q->sp = (q->sp + 1) % q->size; 216 } 217 218 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 219 { 220 uint8_t ret = q->data[q->rp]; 221 q->rp = (q->rp + 1) % q->size; 222 return ret; 223 } 224 225 static int fifo_elements_number(const Exynos4210UartFIFO *q) 226 { 227 if (q->sp < q->rp) { 228 return q->size - q->rp + q->sp; 229 } 230 231 return q->sp - q->rp; 232 } 233 234 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 235 { 236 return q->size - fifo_elements_number(q); 237 } 238 239 static void fifo_reset(Exynos4210UartFIFO *q) 240 { 241 g_free(q->data); 242 q->data = NULL; 243 244 q->data = (uint8_t *)g_malloc0(q->size); 245 246 q->sp = 0; 247 q->rp = 0; 248 } 249 250 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 251 { 252 uint32_t level = 0; 253 uint32_t reg; 254 255 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 256 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 257 258 switch (s->channel) { 259 case 0: 260 level = reg * 32; 261 break; 262 case 1: 263 case 4: 264 level = reg * 8; 265 break; 266 case 2: 267 case 3: 268 level = reg * 2; 269 break; 270 default: 271 level = 0; 272 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); 273 } 274 275 return level; 276 } 277 278 static void exynos4210_uart_update_irq(Exynos4210UartState *s) 279 { 280 /* 281 * The Tx interrupt is always requested if the number of data in the 282 * transmit FIFO is smaller than the trigger level. 283 */ 284 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 285 286 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 287 UFSTAT_Tx_FIFO_COUNT_SHIFT; 288 289 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 290 s->reg[I_(UINTSP)] |= UINTSP_TXD; 291 } 292 } 293 294 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 295 296 if (s->reg[I_(UINTP)]) { 297 qemu_irq_raise(s->irq); 298 299 #if DEBUG_IRQ 300 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", 301 s->channel, s->reg[I_(UINTP)]); 302 #endif 303 304 } else { 305 qemu_irq_lower(s->irq); 306 } 307 } 308 309 static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 310 { 311 int speed, parity, data_bits, stop_bits; 312 QEMUSerialSetParams ssp; 313 uint64_t uclk_rate; 314 315 if (s->reg[I_(UBRDIV)] == 0) { 316 return; 317 } 318 319 if (s->reg[I_(ULCON)] & 0x20) { 320 if (s->reg[I_(ULCON)] & 0x28) { 321 parity = 'E'; 322 } else { 323 parity = 'O'; 324 } 325 } else { 326 parity = 'N'; 327 } 328 329 if (s->reg[I_(ULCON)] & 0x4) { 330 stop_bits = 2; 331 } else { 332 stop_bits = 1; 333 } 334 335 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 336 337 uclk_rate = 24000000; 338 339 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 340 (s->reg[I_(UFRACVAL)] & 0x7) + 16); 341 342 ssp.speed = speed; 343 ssp.parity = parity; 344 ssp.data_bits = data_bits; 345 ssp.stop_bits = stop_bits; 346 347 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 348 349 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", 350 s->channel, speed, parity, data_bits, stop_bits); 351 } 352 353 static void exynos4210_uart_write(void *opaque, hwaddr offset, 354 uint64_t val, unsigned size) 355 { 356 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 357 uint8_t ch; 358 359 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, 360 offset, exynos4210_uart_regname(offset), (long long unsigned int)val); 361 362 switch (offset) { 363 case ULCON: 364 case UBRDIV: 365 case UFRACVAL: 366 s->reg[I_(offset)] = val; 367 exynos4210_uart_update_parameters(s); 368 break; 369 case UFCON: 370 s->reg[I_(UFCON)] = val; 371 if (val & UFCON_Rx_FIFO_RESET) { 372 fifo_reset(&s->rx); 373 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 374 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); 375 } 376 if (val & UFCON_Tx_FIFO_RESET) { 377 fifo_reset(&s->tx); 378 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 379 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); 380 } 381 break; 382 383 case UTXH: 384 if (qemu_chr_fe_backend_connected(&s->chr)) { 385 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 386 UTRSTAT_Tx_BUFFER_EMPTY); 387 ch = (uint8_t)val; 388 /* XXX this blocks entire thread. Rewrite to use 389 * qemu_chr_fe_write and background I/O callbacks */ 390 qemu_chr_fe_write_all(&s->chr, &ch, 1); 391 #if DEBUG_Tx_DATA 392 fprintf(stderr, "%c", ch); 393 #endif 394 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 395 UTRSTAT_Tx_BUFFER_EMPTY; 396 s->reg[I_(UINTSP)] |= UINTSP_TXD; 397 exynos4210_uart_update_irq(s); 398 } 399 break; 400 401 case UINTP: 402 s->reg[I_(UINTP)] &= ~val; 403 s->reg[I_(UINTSP)] &= ~val; 404 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", 405 s->channel, offset, s->reg[I_(UINTP)]); 406 exynos4210_uart_update_irq(s); 407 break; 408 case UTRSTAT: 409 case UERSTAT: 410 case UFSTAT: 411 case UMSTAT: 412 case URXH: 413 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", 414 s->channel, exynos4210_uart_regname(offset), offset); 415 break; 416 case UINTSP: 417 s->reg[I_(UINTSP)] &= ~val; 418 break; 419 case UINTM: 420 s->reg[I_(UINTM)] = val; 421 exynos4210_uart_update_irq(s); 422 break; 423 case UCON: 424 case UMCON: 425 default: 426 s->reg[I_(offset)] = val; 427 break; 428 } 429 } 430 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 431 unsigned size) 432 { 433 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 434 uint32_t res; 435 436 switch (offset) { 437 case UERSTAT: /* Read Only */ 438 res = s->reg[I_(UERSTAT)]; 439 s->reg[I_(UERSTAT)] = 0; 440 return res; 441 case UFSTAT: /* Read Only */ 442 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 443 if (fifo_empty_elements_number(&s->rx) == 0) { 444 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 445 s->reg[I_(UFSTAT)] &= ~0xff; 446 } 447 return s->reg[I_(UFSTAT)]; 448 case URXH: 449 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 450 if (fifo_elements_number(&s->rx)) { 451 res = fifo_retrieve(&s->rx); 452 #if DEBUG_Rx_DATA 453 fprintf(stderr, "%c", res); 454 #endif 455 if (!fifo_elements_number(&s->rx)) { 456 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 457 } else { 458 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 459 } 460 } else { 461 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 462 exynos4210_uart_update_irq(s); 463 res = 0; 464 } 465 } else { 466 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 467 res = s->reg[I_(URXH)]; 468 } 469 return res; 470 case UTXH: 471 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", 472 s->channel, exynos4210_uart_regname(offset), offset); 473 break; 474 default: 475 return s->reg[I_(offset)]; 476 } 477 478 return 0; 479 } 480 481 static const MemoryRegionOps exynos4210_uart_ops = { 482 .read = exynos4210_uart_read, 483 .write = exynos4210_uart_write, 484 .endianness = DEVICE_NATIVE_ENDIAN, 485 .valid = { 486 .max_access_size = 4, 487 .unaligned = false 488 }, 489 }; 490 491 static int exynos4210_uart_can_receive(void *opaque) 492 { 493 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 494 495 return fifo_empty_elements_number(&s->rx); 496 } 497 498 499 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 500 { 501 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 502 int i; 503 504 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 505 if (fifo_empty_elements_number(&s->rx) < size) { 506 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { 507 fifo_store(&s->rx, buf[i]); 508 } 509 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 510 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 511 } else { 512 for (i = 0; i < size; i++) { 513 fifo_store(&s->rx, buf[i]); 514 } 515 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 516 } 517 /* XXX: Around here we maybe should check Rx trigger level */ 518 s->reg[I_(UINTSP)] |= UINTSP_RXD; 519 } else { 520 s->reg[I_(URXH)] = buf[0]; 521 s->reg[I_(UINTSP)] |= UINTSP_RXD; 522 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 523 } 524 525 exynos4210_uart_update_irq(s); 526 } 527 528 529 static void exynos4210_uart_event(void *opaque, int event) 530 { 531 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 532 533 if (event == CHR_EVENT_BREAK) { 534 /* When the RxDn is held in logic 0, then a null byte is pushed into the 535 * fifo */ 536 fifo_store(&s->rx, '\0'); 537 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 538 exynos4210_uart_update_irq(s); 539 } 540 } 541 542 543 static void exynos4210_uart_reset(DeviceState *dev) 544 { 545 Exynos4210UartState *s = EXYNOS4210_UART(dev); 546 int i; 547 548 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 549 s->reg[I_(exynos4210_uart_regs[i].offset)] = 550 exynos4210_uart_regs[i].reset_value; 551 } 552 553 fifo_reset(&s->rx); 554 fifo_reset(&s->tx); 555 556 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); 557 } 558 559 static const VMStateDescription vmstate_exynos4210_uart_fifo = { 560 .name = "exynos4210.uart.fifo", 561 .version_id = 1, 562 .minimum_version_id = 1, 563 .fields = (VMStateField[]) { 564 VMSTATE_UINT32(sp, Exynos4210UartFIFO), 565 VMSTATE_UINT32(rp, Exynos4210UartFIFO), 566 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 567 VMSTATE_END_OF_LIST() 568 } 569 }; 570 571 static const VMStateDescription vmstate_exynos4210_uart = { 572 .name = "exynos4210.uart", 573 .version_id = 1, 574 .minimum_version_id = 1, 575 .fields = (VMStateField[]) { 576 VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 577 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 578 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 579 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 580 VMSTATE_END_OF_LIST() 581 } 582 }; 583 584 DeviceState *exynos4210_uart_create(hwaddr addr, 585 int fifo_size, 586 int channel, 587 Chardev *chr, 588 qemu_irq irq) 589 { 590 DeviceState *dev; 591 SysBusDevice *bus; 592 593 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 594 595 qdev_prop_set_chr(dev, "chardev", chr); 596 qdev_prop_set_uint32(dev, "channel", channel); 597 qdev_prop_set_uint32(dev, "rx-size", fifo_size); 598 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 599 600 bus = SYS_BUS_DEVICE(dev); 601 qdev_init_nofail(dev); 602 if (addr != (hwaddr)-1) { 603 sysbus_mmio_map(bus, 0, addr); 604 } 605 sysbus_connect_irq(bus, 0, irq); 606 607 return dev; 608 } 609 610 static void exynos4210_uart_init(Object *obj) 611 { 612 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 613 Exynos4210UartState *s = EXYNOS4210_UART(dev); 614 615 /* memory mapping */ 616 memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 617 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 618 sysbus_init_mmio(dev, &s->iomem); 619 620 sysbus_init_irq(dev, &s->irq); 621 } 622 623 static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 624 { 625 Exynos4210UartState *s = EXYNOS4210_UART(dev); 626 627 qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 628 exynos4210_uart_receive, exynos4210_uart_event, 629 NULL, s, NULL, true); 630 } 631 632 static Property exynos4210_uart_properties[] = { 633 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 634 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 635 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 636 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 637 DEFINE_PROP_END_OF_LIST(), 638 }; 639 640 static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 641 { 642 DeviceClass *dc = DEVICE_CLASS(klass); 643 644 dc->realize = exynos4210_uart_realize; 645 dc->reset = exynos4210_uart_reset; 646 dc->props = exynos4210_uart_properties; 647 dc->vmsd = &vmstate_exynos4210_uart; 648 } 649 650 static const TypeInfo exynos4210_uart_info = { 651 .name = TYPE_EXYNOS4210_UART, 652 .parent = TYPE_SYS_BUS_DEVICE, 653 .instance_size = sizeof(Exynos4210UartState), 654 .instance_init = exynos4210_uart_init, 655 .class_init = exynos4210_uart_class_init, 656 }; 657 658 static void exynos4210_uart_register(void) 659 { 660 type_register_static(&exynos4210_uart_info); 661 } 662 663 type_init(exynos4210_uart_register) 664