1 /* 2 * Exynos4210 UART Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 */ 21 22 #include "hw/sysbus.h" 23 #include "qemu/error-report.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/char.h" 26 27 #include "hw/arm/exynos4210.h" 28 29 #undef DEBUG_UART 30 #undef DEBUG_UART_EXTEND 31 #undef DEBUG_IRQ 32 #undef DEBUG_Rx_DATA 33 #undef DEBUG_Tx_DATA 34 35 #define DEBUG_UART 0 36 #define DEBUG_UART_EXTEND 0 37 #define DEBUG_IRQ 0 38 #define DEBUG_Rx_DATA 0 39 #define DEBUG_Tx_DATA 0 40 41 #if DEBUG_UART 42 #define PRINT_DEBUG(fmt, args...) \ 43 do { \ 44 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 45 } while (0) 46 47 #if DEBUG_UART_EXTEND 48 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 49 do { \ 50 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 51 } while (0) 52 #else 53 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 54 do {} while (0) 55 #endif /* EXTEND */ 56 57 #else 58 #define PRINT_DEBUG(fmt, args...) \ 59 do {} while (0) 60 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 61 do {} while (0) 62 #endif 63 64 #define PRINT_ERROR(fmt, args...) \ 65 do { \ 66 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 67 } while (0) 68 69 /* 70 * Offsets for UART registers relative to SFR base address 71 * for UARTn 72 * 73 */ 74 #define ULCON 0x0000 /* Line Control */ 75 #define UCON 0x0004 /* Control */ 76 #define UFCON 0x0008 /* FIFO Control */ 77 #define UMCON 0x000C /* Modem Control */ 78 #define UTRSTAT 0x0010 /* Tx/Rx Status */ 79 #define UERSTAT 0x0014 /* UART Error Status */ 80 #define UFSTAT 0x0018 /* FIFO Status */ 81 #define UMSTAT 0x001C /* Modem Status */ 82 #define UTXH 0x0020 /* Transmit Buffer */ 83 #define URXH 0x0024 /* Receive Buffer */ 84 #define UBRDIV 0x0028 /* Baud Rate Divisor */ 85 #define UFRACVAL 0x002C /* Divisor Fractional Value */ 86 #define UINTP 0x0030 /* Interrupt Pending */ 87 #define UINTSP 0x0034 /* Interrupt Source Pending */ 88 #define UINTM 0x0038 /* Interrupt Mask */ 89 90 /* 91 * for indexing register in the uint32_t array 92 * 93 * 'reg' - register offset (see offsets definitions above) 94 * 95 */ 96 #define I_(reg) (reg / sizeof(uint32_t)) 97 98 typedef struct Exynos4210UartReg { 99 const char *name; /* the only reason is the debug output */ 100 hwaddr offset; 101 uint32_t reset_value; 102 } Exynos4210UartReg; 103 104 static Exynos4210UartReg exynos4210_uart_regs[] = { 105 {"ULCON", ULCON, 0x00000000}, 106 {"UCON", UCON, 0x00003000}, 107 {"UFCON", UFCON, 0x00000000}, 108 {"UMCON", UMCON, 0x00000000}, 109 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 110 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 111 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 112 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 113 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 114 {"URXH", URXH, 0x00000000}, /* RO */ 115 {"UBRDIV", UBRDIV, 0x00000000}, 116 {"UFRACVAL", UFRACVAL, 0x00000000}, 117 {"UINTP", UINTP, 0x00000000}, 118 {"UINTSP", UINTSP, 0x00000000}, 119 {"UINTM", UINTM, 0x00000000}, 120 }; 121 122 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 123 124 /* UART FIFO Control */ 125 #define UFCON_FIFO_ENABLE 0x1 126 #define UFCON_Rx_FIFO_RESET 0x2 127 #define UFCON_Tx_FIFO_RESET 0x4 128 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 129 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 130 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 131 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 132 133 /* Uart FIFO Status */ 134 #define UFSTAT_Rx_FIFO_COUNT 0xff 135 #define UFSTAT_Rx_FIFO_FULL 0x100 136 #define UFSTAT_Rx_FIFO_ERROR 0x200 137 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 138 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 139 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 140 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 141 142 /* UART Interrupt Source Pending */ 143 #define UINTSP_RXD 0x1 /* Receive interrupt */ 144 #define UINTSP_ERROR 0x2 /* Error interrupt */ 145 #define UINTSP_TXD 0x4 /* Transmit interrupt */ 146 #define UINTSP_MODEM 0x8 /* Modem interrupt */ 147 148 /* UART Line Control */ 149 #define ULCON_IR_MODE_SHIFT 6 150 #define ULCON_PARITY_SHIFT 3 151 #define ULCON_STOP_BIT_SHIFT 1 152 153 /* UART Tx/Rx Status */ 154 #define UTRSTAT_TRANSMITTER_EMPTY 0x4 155 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 156 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 157 158 /* UART Error Status */ 159 #define UERSTAT_OVERRUN 0x1 160 #define UERSTAT_PARITY 0x2 161 #define UERSTAT_FRAME 0x4 162 #define UERSTAT_BREAK 0x8 163 164 typedef struct { 165 uint8_t *data; 166 uint32_t sp, rp; /* store and retrieve pointers */ 167 uint32_t size; 168 } Exynos4210UartFIFO; 169 170 #define TYPE_EXYNOS4210_UART "exynos4210.uart" 171 #define EXYNOS4210_UART(obj) \ 172 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 173 174 typedef struct Exynos4210UartState { 175 SysBusDevice parent_obj; 176 177 MemoryRegion iomem; 178 179 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 180 Exynos4210UartFIFO rx; 181 Exynos4210UartFIFO tx; 182 183 CharDriverState *chr; 184 qemu_irq irq; 185 186 uint32_t channel; 187 188 } Exynos4210UartState; 189 190 191 #if DEBUG_UART 192 /* Used only for debugging inside PRINT_DEBUG_... macros */ 193 static const char *exynos4210_uart_regname(hwaddr offset) 194 { 195 196 int i; 197 198 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 199 if (offset == exynos4210_uart_regs[i].offset) { 200 return exynos4210_uart_regs[i].name; 201 } 202 } 203 204 return NULL; 205 } 206 #endif 207 208 209 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 210 { 211 q->data[q->sp] = ch; 212 q->sp = (q->sp + 1) % q->size; 213 } 214 215 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 216 { 217 uint8_t ret = q->data[q->rp]; 218 q->rp = (q->rp + 1) % q->size; 219 return ret; 220 } 221 222 static int fifo_elements_number(Exynos4210UartFIFO *q) 223 { 224 if (q->sp < q->rp) { 225 return q->size - q->rp + q->sp; 226 } 227 228 return q->sp - q->rp; 229 } 230 231 static int fifo_empty_elements_number(Exynos4210UartFIFO *q) 232 { 233 return q->size - fifo_elements_number(q); 234 } 235 236 static void fifo_reset(Exynos4210UartFIFO *q) 237 { 238 g_free(q->data); 239 q->data = NULL; 240 241 q->data = (uint8_t *)g_malloc0(q->size); 242 243 q->sp = 0; 244 q->rp = 0; 245 } 246 247 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s) 248 { 249 uint32_t level = 0; 250 uint32_t reg; 251 252 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 253 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 254 255 switch (s->channel) { 256 case 0: 257 level = reg * 32; 258 break; 259 case 1: 260 case 4: 261 level = reg * 8; 262 break; 263 case 2: 264 case 3: 265 level = reg * 2; 266 break; 267 default: 268 level = 0; 269 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); 270 } 271 272 return level; 273 } 274 275 static void exynos4210_uart_update_irq(Exynos4210UartState *s) 276 { 277 /* 278 * The Tx interrupt is always requested if the number of data in the 279 * transmit FIFO is smaller than the trigger level. 280 */ 281 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 282 283 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 284 UFSTAT_Tx_FIFO_COUNT_SHIFT; 285 286 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 287 s->reg[I_(UINTSP)] |= UINTSP_TXD; 288 } 289 } 290 291 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 292 293 if (s->reg[I_(UINTP)]) { 294 qemu_irq_raise(s->irq); 295 296 #if DEBUG_IRQ 297 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", 298 s->channel, s->reg[I_(UINTP)]); 299 #endif 300 301 } else { 302 qemu_irq_lower(s->irq); 303 } 304 } 305 306 static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 307 { 308 int speed, parity, data_bits, stop_bits, frame_size; 309 QEMUSerialSetParams ssp; 310 uint64_t uclk_rate; 311 312 if (s->reg[I_(UBRDIV)] == 0) { 313 return; 314 } 315 316 frame_size = 1; /* start bit */ 317 if (s->reg[I_(ULCON)] & 0x20) { 318 frame_size++; /* parity bit */ 319 if (s->reg[I_(ULCON)] & 0x28) { 320 parity = 'E'; 321 } else { 322 parity = 'O'; 323 } 324 } else { 325 parity = 'N'; 326 } 327 328 if (s->reg[I_(ULCON)] & 0x4) { 329 stop_bits = 2; 330 } else { 331 stop_bits = 1; 332 } 333 334 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 335 336 frame_size += data_bits + stop_bits; 337 338 uclk_rate = 24000000; 339 340 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 341 (s->reg[I_(UFRACVAL)] & 0x7) + 16); 342 343 ssp.speed = speed; 344 ssp.parity = parity; 345 ssp.data_bits = data_bits; 346 ssp.stop_bits = stop_bits; 347 348 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 349 350 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", 351 s->channel, speed, parity, data_bits, stop_bits); 352 } 353 354 static void exynos4210_uart_write(void *opaque, hwaddr offset, 355 uint64_t val, unsigned size) 356 { 357 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 358 uint8_t ch; 359 360 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, 361 offset, exynos4210_uart_regname(offset), (long long unsigned int)val); 362 363 switch (offset) { 364 case ULCON: 365 case UBRDIV: 366 case UFRACVAL: 367 s->reg[I_(offset)] = val; 368 exynos4210_uart_update_parameters(s); 369 break; 370 case UFCON: 371 s->reg[I_(UFCON)] = val; 372 if (val & UFCON_Rx_FIFO_RESET) { 373 fifo_reset(&s->rx); 374 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 375 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); 376 } 377 if (val & UFCON_Tx_FIFO_RESET) { 378 fifo_reset(&s->tx); 379 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 380 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); 381 } 382 break; 383 384 case UTXH: 385 if (s->chr) { 386 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 387 UTRSTAT_Tx_BUFFER_EMPTY); 388 ch = (uint8_t)val; 389 qemu_chr_fe_write(s->chr, &ch, 1); 390 #if DEBUG_Tx_DATA 391 fprintf(stderr, "%c", ch); 392 #endif 393 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 394 UTRSTAT_Tx_BUFFER_EMPTY; 395 s->reg[I_(UINTSP)] |= UINTSP_TXD; 396 exynos4210_uart_update_irq(s); 397 } 398 break; 399 400 case UINTP: 401 s->reg[I_(UINTP)] &= ~val; 402 s->reg[I_(UINTSP)] &= ~val; 403 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", 404 s->channel, offset, s->reg[I_(UINTP)]); 405 exynos4210_uart_update_irq(s); 406 break; 407 case UTRSTAT: 408 case UERSTAT: 409 case UFSTAT: 410 case UMSTAT: 411 case URXH: 412 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", 413 s->channel, exynos4210_uart_regname(offset), offset); 414 break; 415 case UINTSP: 416 s->reg[I_(UINTSP)] &= ~val; 417 break; 418 case UINTM: 419 s->reg[I_(UINTM)] = val; 420 exynos4210_uart_update_irq(s); 421 break; 422 case UCON: 423 case UMCON: 424 default: 425 s->reg[I_(offset)] = val; 426 break; 427 } 428 } 429 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 430 unsigned size) 431 { 432 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 433 uint32_t res; 434 435 switch (offset) { 436 case UERSTAT: /* Read Only */ 437 res = s->reg[I_(UERSTAT)]; 438 s->reg[I_(UERSTAT)] = 0; 439 return res; 440 case UFSTAT: /* Read Only */ 441 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 442 if (fifo_empty_elements_number(&s->rx) == 0) { 443 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 444 s->reg[I_(UFSTAT)] &= ~0xff; 445 } 446 return s->reg[I_(UFSTAT)]; 447 case URXH: 448 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 449 if (fifo_elements_number(&s->rx)) { 450 res = fifo_retrieve(&s->rx); 451 #if DEBUG_Rx_DATA 452 fprintf(stderr, "%c", res); 453 #endif 454 if (!fifo_elements_number(&s->rx)) { 455 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 456 } else { 457 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 458 } 459 } else { 460 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 461 exynos4210_uart_update_irq(s); 462 res = 0; 463 } 464 } else { 465 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 466 res = s->reg[I_(URXH)]; 467 } 468 return res; 469 case UTXH: 470 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", 471 s->channel, exynos4210_uart_regname(offset), offset); 472 break; 473 default: 474 return s->reg[I_(offset)]; 475 } 476 477 return 0; 478 } 479 480 static const MemoryRegionOps exynos4210_uart_ops = { 481 .read = exynos4210_uart_read, 482 .write = exynos4210_uart_write, 483 .endianness = DEVICE_NATIVE_ENDIAN, 484 .valid = { 485 .max_access_size = 4, 486 .unaligned = false 487 }, 488 }; 489 490 static int exynos4210_uart_can_receive(void *opaque) 491 { 492 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 493 494 return fifo_empty_elements_number(&s->rx); 495 } 496 497 498 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 499 { 500 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 501 int i; 502 503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 504 if (fifo_empty_elements_number(&s->rx) < size) { 505 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { 506 fifo_store(&s->rx, buf[i]); 507 } 508 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 509 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 510 } else { 511 for (i = 0; i < size; i++) { 512 fifo_store(&s->rx, buf[i]); 513 } 514 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 515 } 516 /* XXX: Around here we maybe should check Rx trigger level */ 517 s->reg[I_(UINTSP)] |= UINTSP_RXD; 518 } else { 519 s->reg[I_(URXH)] = buf[0]; 520 s->reg[I_(UINTSP)] |= UINTSP_RXD; 521 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 522 } 523 524 exynos4210_uart_update_irq(s); 525 } 526 527 528 static void exynos4210_uart_event(void *opaque, int event) 529 { 530 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 531 532 if (event == CHR_EVENT_BREAK) { 533 /* When the RxDn is held in logic 0, then a null byte is pushed into the 534 * fifo */ 535 fifo_store(&s->rx, '\0'); 536 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 537 exynos4210_uart_update_irq(s); 538 } 539 } 540 541 542 static void exynos4210_uart_reset(DeviceState *dev) 543 { 544 Exynos4210UartState *s = EXYNOS4210_UART(dev); 545 int i; 546 547 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 548 s->reg[I_(exynos4210_uart_regs[i].offset)] = 549 exynos4210_uart_regs[i].reset_value; 550 } 551 552 fifo_reset(&s->rx); 553 fifo_reset(&s->tx); 554 555 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); 556 } 557 558 static const VMStateDescription vmstate_exynos4210_uart_fifo = { 559 .name = "exynos4210.uart.fifo", 560 .version_id = 1, 561 .minimum_version_id = 1, 562 .fields = (VMStateField[]) { 563 VMSTATE_UINT32(sp, Exynos4210UartFIFO), 564 VMSTATE_UINT32(rp, Exynos4210UartFIFO), 565 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size), 566 VMSTATE_END_OF_LIST() 567 } 568 }; 569 570 static const VMStateDescription vmstate_exynos4210_uart = { 571 .name = "exynos4210.uart", 572 .version_id = 1, 573 .minimum_version_id = 1, 574 .fields = (VMStateField[]) { 575 VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 576 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 577 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 578 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 579 VMSTATE_END_OF_LIST() 580 } 581 }; 582 583 DeviceState *exynos4210_uart_create(hwaddr addr, 584 int fifo_size, 585 int channel, 586 CharDriverState *chr, 587 qemu_irq irq) 588 { 589 DeviceState *dev; 590 SysBusDevice *bus; 591 592 const char chr_name[] = "serial"; 593 char label[ARRAY_SIZE(chr_name) + 1]; 594 595 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 596 597 if (!chr) { 598 if (channel >= MAX_SERIAL_PORTS) { 599 error_report("Only %d serial ports are supported by QEMU", 600 MAX_SERIAL_PORTS); 601 exit(1); 602 } 603 chr = serial_hds[channel]; 604 if (!chr) { 605 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); 606 chr = qemu_chr_new(label, "null", NULL); 607 if (!(chr)) { 608 error_report("Can't assign serial port to UART%d", channel); 609 exit(1); 610 } 611 } 612 } 613 614 qdev_prop_set_chr(dev, "chardev", chr); 615 qdev_prop_set_uint32(dev, "channel", channel); 616 qdev_prop_set_uint32(dev, "rx-size", fifo_size); 617 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 618 619 bus = SYS_BUS_DEVICE(dev); 620 qdev_init_nofail(dev); 621 if (addr != (hwaddr)-1) { 622 sysbus_mmio_map(bus, 0, addr); 623 } 624 sysbus_connect_irq(bus, 0, irq); 625 626 return dev; 627 } 628 629 static int exynos4210_uart_init(SysBusDevice *dev) 630 { 631 Exynos4210UartState *s = EXYNOS4210_UART(dev); 632 633 /* memory mapping */ 634 memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s, 635 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 636 sysbus_init_mmio(dev, &s->iomem); 637 638 sysbus_init_irq(dev, &s->irq); 639 640 qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive, 641 exynos4210_uart_receive, exynos4210_uart_event, s); 642 643 return 0; 644 } 645 646 static Property exynos4210_uart_properties[] = { 647 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 648 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 649 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 650 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 651 DEFINE_PROP_END_OF_LIST(), 652 }; 653 654 static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 655 { 656 DeviceClass *dc = DEVICE_CLASS(klass); 657 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 658 659 k->init = exynos4210_uart_init; 660 dc->reset = exynos4210_uart_reset; 661 dc->props = exynos4210_uart_properties; 662 dc->vmsd = &vmstate_exynos4210_uart; 663 } 664 665 static const TypeInfo exynos4210_uart_info = { 666 .name = TYPE_EXYNOS4210_UART, 667 .parent = TYPE_SYS_BUS_DEVICE, 668 .instance_size = sizeof(Exynos4210UartState), 669 .class_init = exynos4210_uart_class_init, 670 }; 671 672 static void exynos4210_uart_register(void) 673 { 674 type_register_static(&exynos4210_uart_info); 675 } 676 677 type_init(exynos4210_uart_register) 678