xref: /openbmc/qemu/hw/char/exynos4210_uart.c (revision 709395f8)
1 /*
2  *  Exynos4210 UART Emulation
3  *
4  *  Copyright (C) 2011 Samsung Electronics Co Ltd.
5  *    Maksim Kozlov, <m.kozlov@samsung.com>
6  *
7  *  This program is free software; you can redistribute it and/or modify it
8  *  under the terms of the GNU General Public License as published by the
9  *  Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful, but WITHOUT
13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  *  for more details.
16  *
17  *  You should have received a copy of the GNU General Public License along
18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
19  *
20  */
21 
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/sysemu.h"
26 #include "chardev/char-fe.h"
27 #include "chardev/char-serial.h"
28 
29 #include "hw/arm/exynos4210.h"
30 
31 #undef DEBUG_UART
32 #undef DEBUG_UART_EXTEND
33 #undef DEBUG_IRQ
34 #undef DEBUG_Rx_DATA
35 #undef DEBUG_Tx_DATA
36 
37 #define DEBUG_UART            0
38 #define DEBUG_UART_EXTEND     0
39 #define DEBUG_IRQ             0
40 #define DEBUG_Rx_DATA         0
41 #define DEBUG_Tx_DATA         0
42 
43 #if DEBUG_UART
44 #define  PRINT_DEBUG(fmt, args...)  \
45         do { \
46             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
47         } while (0)
48 
49 #if DEBUG_UART_EXTEND
50 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
51         do { \
52             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
53         } while (0)
54 #else
55 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
56         do {} while (0)
57 #endif /* EXTEND */
58 
59 #else
60 #define  PRINT_DEBUG(fmt, args...)  \
61         do {} while (0)
62 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
63         do {} while (0)
64 #endif
65 
66 #define  PRINT_ERROR(fmt, args...) \
67         do { \
68             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
69         } while (0)
70 
71 /*
72  *  Offsets for UART registers relative to SFR base address
73  *  for UARTn
74  *
75  */
76 #define ULCON      0x0000 /* Line Control             */
77 #define UCON       0x0004 /* Control                  */
78 #define UFCON      0x0008 /* FIFO Control             */
79 #define UMCON      0x000C /* Modem Control            */
80 #define UTRSTAT    0x0010 /* Tx/Rx Status             */
81 #define UERSTAT    0x0014 /* UART Error Status        */
82 #define UFSTAT     0x0018 /* FIFO Status              */
83 #define UMSTAT     0x001C /* Modem Status             */
84 #define UTXH       0x0020 /* Transmit Buffer          */
85 #define URXH       0x0024 /* Receive Buffer           */
86 #define UBRDIV     0x0028 /* Baud Rate Divisor        */
87 #define UFRACVAL   0x002C /* Divisor Fractional Value */
88 #define UINTP      0x0030 /* Interrupt Pending        */
89 #define UINTSP     0x0034 /* Interrupt Source Pending */
90 #define UINTM      0x0038 /* Interrupt Mask           */
91 
92 /*
93  * for indexing register in the uint32_t array
94  *
95  * 'reg' - register offset (see offsets definitions above)
96  *
97  */
98 #define I_(reg) (reg / sizeof(uint32_t))
99 
100 typedef struct Exynos4210UartReg {
101     const char         *name; /* the only reason is the debug output */
102     hwaddr  offset;
103     uint32_t            reset_value;
104 } Exynos4210UartReg;
105 
106 static const Exynos4210UartReg exynos4210_uart_regs[] = {
107     {"ULCON",    ULCON,    0x00000000},
108     {"UCON",     UCON,     0x00003000},
109     {"UFCON",    UFCON,    0x00000000},
110     {"UMCON",    UMCON,    0x00000000},
111     {"UTRSTAT",  UTRSTAT,  0x00000006}, /* RO */
112     {"UERSTAT",  UERSTAT,  0x00000000}, /* RO */
113     {"UFSTAT",   UFSTAT,   0x00000000}, /* RO */
114     {"UMSTAT",   UMSTAT,   0x00000000}, /* RO */
115     {"UTXH",     UTXH,     0x5c5c5c5c}, /* WO, undefined reset value*/
116     {"URXH",     URXH,     0x00000000}, /* RO */
117     {"UBRDIV",   UBRDIV,   0x00000000},
118     {"UFRACVAL", UFRACVAL, 0x00000000},
119     {"UINTP",    UINTP,    0x00000000},
120     {"UINTSP",   UINTSP,   0x00000000},
121     {"UINTM",    UINTM,    0x00000000},
122 };
123 
124 #define EXYNOS4210_UART_REGS_MEM_SIZE    0x3C
125 
126 /* UART FIFO Control */
127 #define UFCON_FIFO_ENABLE                    0x1
128 #define UFCON_Rx_FIFO_RESET                  0x2
129 #define UFCON_Tx_FIFO_RESET                  0x4
130 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT    8
131 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
132 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT    4
133 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
134 
135 /* Uart FIFO Status */
136 #define UFSTAT_Rx_FIFO_COUNT        0xff
137 #define UFSTAT_Rx_FIFO_FULL         0x100
138 #define UFSTAT_Rx_FIFO_ERROR        0x200
139 #define UFSTAT_Tx_FIFO_COUNT_SHIFT  16
140 #define UFSTAT_Tx_FIFO_COUNT        (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
141 #define UFSTAT_Tx_FIFO_FULL_SHIFT   24
142 #define UFSTAT_Tx_FIFO_FULL         (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
143 
144 /* UART Interrupt Source Pending */
145 #define UINTSP_RXD      0x1 /* Receive interrupt  */
146 #define UINTSP_ERROR    0x2 /* Error interrupt    */
147 #define UINTSP_TXD      0x4 /* Transmit interrupt */
148 #define UINTSP_MODEM    0x8 /* Modem interrupt    */
149 
150 /* UART Line Control */
151 #define ULCON_IR_MODE_SHIFT   6
152 #define ULCON_PARITY_SHIFT    3
153 #define ULCON_STOP_BIT_SHIFT  1
154 
155 /* UART Tx/Rx Status */
156 #define UTRSTAT_TRANSMITTER_EMPTY       0x4
157 #define UTRSTAT_Tx_BUFFER_EMPTY         0x2
158 #define UTRSTAT_Rx_BUFFER_DATA_READY    0x1
159 
160 /* UART Error Status */
161 #define UERSTAT_OVERRUN  0x1
162 #define UERSTAT_PARITY   0x2
163 #define UERSTAT_FRAME    0x4
164 #define UERSTAT_BREAK    0x8
165 
166 typedef struct {
167     uint8_t    *data;
168     uint32_t    sp, rp; /* store and retrieve pointers */
169     uint32_t    size;
170 } Exynos4210UartFIFO;
171 
172 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
173 #define EXYNOS4210_UART(obj) \
174     OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
175 
176 typedef struct Exynos4210UartState {
177     SysBusDevice parent_obj;
178 
179     MemoryRegion iomem;
180 
181     uint32_t             reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
182     Exynos4210UartFIFO   rx;
183     Exynos4210UartFIFO   tx;
184 
185     CharBackend       chr;
186     qemu_irq          irq;
187 
188     uint32_t channel;
189 
190 } Exynos4210UartState;
191 
192 
193 #if DEBUG_UART
194 /* Used only for debugging inside PRINT_DEBUG_... macros */
195 static const char *exynos4210_uart_regname(hwaddr  offset)
196 {
197 
198     int i;
199 
200     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
201         if (offset == exynos4210_uart_regs[i].offset) {
202             return exynos4210_uart_regs[i].name;
203         }
204     }
205 
206     return NULL;
207 }
208 #endif
209 
210 
211 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
212 {
213     q->data[q->sp] = ch;
214     q->sp = (q->sp + 1) % q->size;
215 }
216 
217 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
218 {
219     uint8_t ret = q->data[q->rp];
220     q->rp = (q->rp + 1) % q->size;
221     return  ret;
222 }
223 
224 static int fifo_elements_number(const Exynos4210UartFIFO *q)
225 {
226     if (q->sp < q->rp) {
227         return q->size - q->rp + q->sp;
228     }
229 
230     return q->sp - q->rp;
231 }
232 
233 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
234 {
235     return q->size - fifo_elements_number(q);
236 }
237 
238 static void fifo_reset(Exynos4210UartFIFO *q)
239 {
240     g_free(q->data);
241     q->data = NULL;
242 
243     q->data = (uint8_t *)g_malloc0(q->size);
244 
245     q->sp = 0;
246     q->rp = 0;
247 }
248 
249 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
250 {
251     uint32_t level = 0;
252     uint32_t reg;
253 
254     reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
255             UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
256 
257     switch (s->channel) {
258     case 0:
259         level = reg * 32;
260         break;
261     case 1:
262     case 4:
263         level = reg * 8;
264         break;
265     case 2:
266     case 3:
267         level = reg * 2;
268         break;
269     default:
270         level = 0;
271         PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
272     }
273 
274     return level;
275 }
276 
277 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
278 {
279     /*
280      * The Tx interrupt is always requested if the number of data in the
281      * transmit FIFO is smaller than the trigger level.
282      */
283     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
284 
285         uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
286                 UFSTAT_Tx_FIFO_COUNT_SHIFT;
287 
288         if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
289             s->reg[I_(UINTSP)] |= UINTSP_TXD;
290         }
291     }
292 
293     s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
294 
295     if (s->reg[I_(UINTP)]) {
296         qemu_irq_raise(s->irq);
297 
298 #if DEBUG_IRQ
299         fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
300                 s->channel, s->reg[I_(UINTP)]);
301 #endif
302 
303     } else {
304         qemu_irq_lower(s->irq);
305     }
306 }
307 
308 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
309 {
310     int speed, parity, data_bits, stop_bits;
311     QEMUSerialSetParams ssp;
312     uint64_t uclk_rate;
313 
314     if (s->reg[I_(UBRDIV)] == 0) {
315         return;
316     }
317 
318     if (s->reg[I_(ULCON)] & 0x20) {
319         if (s->reg[I_(ULCON)] & 0x28) {
320             parity = 'E';
321         } else {
322             parity = 'O';
323         }
324     } else {
325         parity = 'N';
326     }
327 
328     if (s->reg[I_(ULCON)] & 0x4) {
329         stop_bits = 2;
330     } else {
331         stop_bits = 1;
332     }
333 
334     data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
335 
336     uclk_rate = 24000000;
337 
338     speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
339             (s->reg[I_(UFRACVAL)] & 0x7) + 16);
340 
341     ssp.speed     = speed;
342     ssp.parity    = parity;
343     ssp.data_bits = data_bits;
344     ssp.stop_bits = stop_bits;
345 
346     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
347 
348     PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
349                 s->channel, speed, parity, data_bits, stop_bits);
350 }
351 
352 static void exynos4210_uart_write(void *opaque, hwaddr offset,
353                                uint64_t val, unsigned size)
354 {
355     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
356     uint8_t ch;
357 
358     PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
359         offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
360 
361     switch (offset) {
362     case ULCON:
363     case UBRDIV:
364     case UFRACVAL:
365         s->reg[I_(offset)] = val;
366         exynos4210_uart_update_parameters(s);
367         break;
368     case UFCON:
369         s->reg[I_(UFCON)] = val;
370         if (val & UFCON_Rx_FIFO_RESET) {
371             fifo_reset(&s->rx);
372             s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
373             PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
374         }
375         if (val & UFCON_Tx_FIFO_RESET) {
376             fifo_reset(&s->tx);
377             s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
378             PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
379         }
380         break;
381 
382     case UTXH:
383         if (qemu_chr_fe_backend_connected(&s->chr)) {
384             s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
385                     UTRSTAT_Tx_BUFFER_EMPTY);
386             ch = (uint8_t)val;
387             /* XXX this blocks entire thread. Rewrite to use
388              * qemu_chr_fe_write and background I/O callbacks */
389             qemu_chr_fe_write_all(&s->chr, &ch, 1);
390 #if DEBUG_Tx_DATA
391             fprintf(stderr, "%c", ch);
392 #endif
393             s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
394                     UTRSTAT_Tx_BUFFER_EMPTY;
395             s->reg[I_(UINTSP)]  |= UINTSP_TXD;
396             exynos4210_uart_update_irq(s);
397         }
398         break;
399 
400     case UINTP:
401         s->reg[I_(UINTP)] &= ~val;
402         s->reg[I_(UINTSP)] &= ~val;
403         PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
404                     s->channel, offset, s->reg[I_(UINTP)]);
405         exynos4210_uart_update_irq(s);
406         break;
407     case UTRSTAT:
408     case UERSTAT:
409     case UFSTAT:
410     case UMSTAT:
411     case URXH:
412         PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
413                     s->channel, exynos4210_uart_regname(offset), offset);
414         break;
415     case UINTSP:
416         s->reg[I_(UINTSP)]  &= ~val;
417         break;
418     case UINTM:
419         s->reg[I_(UINTM)] = val;
420         exynos4210_uart_update_irq(s);
421         break;
422     case UCON:
423     case UMCON:
424     default:
425         s->reg[I_(offset)] = val;
426         break;
427     }
428 }
429 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
430                                   unsigned size)
431 {
432     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
433     uint32_t res;
434 
435     switch (offset) {
436     case UERSTAT: /* Read Only */
437         res = s->reg[I_(UERSTAT)];
438         s->reg[I_(UERSTAT)] = 0;
439         return res;
440     case UFSTAT: /* Read Only */
441         s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
442         if (fifo_empty_elements_number(&s->rx) == 0) {
443             s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
444             s->reg[I_(UFSTAT)] &= ~0xff;
445         }
446         return s->reg[I_(UFSTAT)];
447     case URXH:
448         if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
449             if (fifo_elements_number(&s->rx)) {
450                 res = fifo_retrieve(&s->rx);
451 #if DEBUG_Rx_DATA
452                 fprintf(stderr, "%c", res);
453 #endif
454                 if (!fifo_elements_number(&s->rx)) {
455                     s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
456                 } else {
457                     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
458                 }
459             } else {
460                 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
461                 exynos4210_uart_update_irq(s);
462                 res = 0;
463             }
464         } else {
465             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
466             res = s->reg[I_(URXH)];
467         }
468         return res;
469     case UTXH:
470         PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
471                     s->channel, exynos4210_uart_regname(offset), offset);
472         break;
473     default:
474         return s->reg[I_(offset)];
475     }
476 
477     return 0;
478 }
479 
480 static const MemoryRegionOps exynos4210_uart_ops = {
481     .read = exynos4210_uart_read,
482     .write = exynos4210_uart_write,
483     .endianness = DEVICE_NATIVE_ENDIAN,
484     .valid = {
485         .max_access_size = 4,
486         .unaligned = false
487     },
488 };
489 
490 static int exynos4210_uart_can_receive(void *opaque)
491 {
492     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
493 
494     return fifo_empty_elements_number(&s->rx);
495 }
496 
497 
498 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
499 {
500     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
501     int i;
502 
503     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
504         if (fifo_empty_elements_number(&s->rx) < size) {
505             for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
506                 fifo_store(&s->rx, buf[i]);
507             }
508             s->reg[I_(UINTSP)] |= UINTSP_ERROR;
509             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
510         } else {
511             for (i = 0; i < size; i++) {
512                 fifo_store(&s->rx, buf[i]);
513             }
514             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
515         }
516         /* XXX: Around here we maybe should check Rx trigger level */
517         s->reg[I_(UINTSP)] |= UINTSP_RXD;
518     } else {
519         s->reg[I_(URXH)] = buf[0];
520         s->reg[I_(UINTSP)] |= UINTSP_RXD;
521         s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
522     }
523 
524     exynos4210_uart_update_irq(s);
525 }
526 
527 
528 static void exynos4210_uart_event(void *opaque, int event)
529 {
530     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
531 
532     if (event == CHR_EVENT_BREAK) {
533         /* When the RxDn is held in logic 0, then a null byte is pushed into the
534          * fifo */
535         fifo_store(&s->rx, '\0');
536         s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
537         exynos4210_uart_update_irq(s);
538     }
539 }
540 
541 
542 static void exynos4210_uart_reset(DeviceState *dev)
543 {
544     Exynos4210UartState *s = EXYNOS4210_UART(dev);
545     int i;
546 
547     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
548         s->reg[I_(exynos4210_uart_regs[i].offset)] =
549                 exynos4210_uart_regs[i].reset_value;
550     }
551 
552     fifo_reset(&s->rx);
553     fifo_reset(&s->tx);
554 
555     PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
556 }
557 
558 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
559     .name = "exynos4210.uart.fifo",
560     .version_id = 1,
561     .minimum_version_id = 1,
562     .fields = (VMStateField[]) {
563         VMSTATE_UINT32(sp, Exynos4210UartFIFO),
564         VMSTATE_UINT32(rp, Exynos4210UartFIFO),
565         VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size),
566         VMSTATE_END_OF_LIST()
567     }
568 };
569 
570 static const VMStateDescription vmstate_exynos4210_uart = {
571     .name = "exynos4210.uart",
572     .version_id = 1,
573     .minimum_version_id = 1,
574     .fields = (VMStateField[]) {
575         VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
576                        vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
577         VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
578                              EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
579         VMSTATE_END_OF_LIST()
580     }
581 };
582 
583 DeviceState *exynos4210_uart_create(hwaddr addr,
584                                     int fifo_size,
585                                     int channel,
586                                     Chardev *chr,
587                                     qemu_irq irq)
588 {
589     DeviceState  *dev;
590     SysBusDevice *bus;
591 
592     dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
593 
594     qdev_prop_set_chr(dev, "chardev", chr);
595     qdev_prop_set_uint32(dev, "channel", channel);
596     qdev_prop_set_uint32(dev, "rx-size", fifo_size);
597     qdev_prop_set_uint32(dev, "tx-size", fifo_size);
598 
599     bus = SYS_BUS_DEVICE(dev);
600     qdev_init_nofail(dev);
601     if (addr != (hwaddr)-1) {
602         sysbus_mmio_map(bus, 0, addr);
603     }
604     sysbus_connect_irq(bus, 0, irq);
605 
606     return dev;
607 }
608 
609 static void exynos4210_uart_init(Object *obj)
610 {
611     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
612     Exynos4210UartState *s = EXYNOS4210_UART(dev);
613 
614     /* memory mapping */
615     memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
616                           "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
617     sysbus_init_mmio(dev, &s->iomem);
618 
619     sysbus_init_irq(dev, &s->irq);
620 }
621 
622 static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
623 {
624     Exynos4210UartState *s = EXYNOS4210_UART(dev);
625 
626     qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
627                              exynos4210_uart_receive, exynos4210_uart_event,
628                              NULL, s, NULL, true);
629 }
630 
631 static Property exynos4210_uart_properties[] = {
632     DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
633     DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
634     DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
635     DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
636     DEFINE_PROP_END_OF_LIST(),
637 };
638 
639 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
640 {
641     DeviceClass *dc = DEVICE_CLASS(klass);
642 
643     dc->realize = exynos4210_uart_realize;
644     dc->reset = exynos4210_uart_reset;
645     dc->props = exynos4210_uart_properties;
646     dc->vmsd = &vmstate_exynos4210_uart;
647 }
648 
649 static const TypeInfo exynos4210_uart_info = {
650     .name          = TYPE_EXYNOS4210_UART,
651     .parent        = TYPE_SYS_BUS_DEVICE,
652     .instance_size = sizeof(Exynos4210UartState),
653     .instance_init = exynos4210_uart_init,
654     .class_init    = exynos4210_uart_class_init,
655 };
656 
657 static void exynos4210_uart_register(void)
658 {
659     type_register_static(&exynos4210_uart_info);
660 }
661 
662 type_init(exynos4210_uart_register)
663