1 /* 2 * Exynos4210 UART Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/sysbus.h" 24 #include "qemu/error-report.h" 25 #include "qemu/module.h" 26 #include "sysemu/sysemu.h" 27 #include "chardev/char-fe.h" 28 #include "chardev/char-serial.h" 29 30 #include "hw/arm/exynos4210.h" 31 #include "hw/irq.h" 32 33 #undef DEBUG_UART 34 #undef DEBUG_UART_EXTEND 35 #undef DEBUG_IRQ 36 #undef DEBUG_Rx_DATA 37 #undef DEBUG_Tx_DATA 38 39 #define DEBUG_UART 0 40 #define DEBUG_UART_EXTEND 0 41 #define DEBUG_IRQ 0 42 #define DEBUG_Rx_DATA 0 43 #define DEBUG_Tx_DATA 0 44 45 #if DEBUG_UART 46 #define PRINT_DEBUG(fmt, args...) \ 47 do { \ 48 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 49 } while (0) 50 51 #if DEBUG_UART_EXTEND 52 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 53 do { \ 54 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 55 } while (0) 56 #else 57 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 58 do {} while (0) 59 #endif /* EXTEND */ 60 61 #else 62 #define PRINT_DEBUG(fmt, args...) \ 63 do {} while (0) 64 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 65 do {} while (0) 66 #endif 67 68 #define PRINT_ERROR(fmt, args...) \ 69 do { \ 70 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 71 } while (0) 72 73 /* 74 * Offsets for UART registers relative to SFR base address 75 * for UARTn 76 * 77 */ 78 #define ULCON 0x0000 /* Line Control */ 79 #define UCON 0x0004 /* Control */ 80 #define UFCON 0x0008 /* FIFO Control */ 81 #define UMCON 0x000C /* Modem Control */ 82 #define UTRSTAT 0x0010 /* Tx/Rx Status */ 83 #define UERSTAT 0x0014 /* UART Error Status */ 84 #define UFSTAT 0x0018 /* FIFO Status */ 85 #define UMSTAT 0x001C /* Modem Status */ 86 #define UTXH 0x0020 /* Transmit Buffer */ 87 #define URXH 0x0024 /* Receive Buffer */ 88 #define UBRDIV 0x0028 /* Baud Rate Divisor */ 89 #define UFRACVAL 0x002C /* Divisor Fractional Value */ 90 #define UINTP 0x0030 /* Interrupt Pending */ 91 #define UINTSP 0x0034 /* Interrupt Source Pending */ 92 #define UINTM 0x0038 /* Interrupt Mask */ 93 94 /* 95 * for indexing register in the uint32_t array 96 * 97 * 'reg' - register offset (see offsets definitions above) 98 * 99 */ 100 #define I_(reg) (reg / sizeof(uint32_t)) 101 102 typedef struct Exynos4210UartReg { 103 const char *name; /* the only reason is the debug output */ 104 hwaddr offset; 105 uint32_t reset_value; 106 } Exynos4210UartReg; 107 108 static const Exynos4210UartReg exynos4210_uart_regs[] = { 109 {"ULCON", ULCON, 0x00000000}, 110 {"UCON", UCON, 0x00003000}, 111 {"UFCON", UFCON, 0x00000000}, 112 {"UMCON", UMCON, 0x00000000}, 113 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 114 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 115 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 116 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 117 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 118 {"URXH", URXH, 0x00000000}, /* RO */ 119 {"UBRDIV", UBRDIV, 0x00000000}, 120 {"UFRACVAL", UFRACVAL, 0x00000000}, 121 {"UINTP", UINTP, 0x00000000}, 122 {"UINTSP", UINTSP, 0x00000000}, 123 {"UINTM", UINTM, 0x00000000}, 124 }; 125 126 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 127 128 /* UART FIFO Control */ 129 #define UFCON_FIFO_ENABLE 0x1 130 #define UFCON_Rx_FIFO_RESET 0x2 131 #define UFCON_Tx_FIFO_RESET 0x4 132 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 133 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 134 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 135 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 136 137 /* Uart FIFO Status */ 138 #define UFSTAT_Rx_FIFO_COUNT 0xff 139 #define UFSTAT_Rx_FIFO_FULL 0x100 140 #define UFSTAT_Rx_FIFO_ERROR 0x200 141 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 142 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 143 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 144 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 145 146 /* UART Interrupt Source Pending */ 147 #define UINTSP_RXD 0x1 /* Receive interrupt */ 148 #define UINTSP_ERROR 0x2 /* Error interrupt */ 149 #define UINTSP_TXD 0x4 /* Transmit interrupt */ 150 #define UINTSP_MODEM 0x8 /* Modem interrupt */ 151 152 /* UART Line Control */ 153 #define ULCON_IR_MODE_SHIFT 6 154 #define ULCON_PARITY_SHIFT 3 155 #define ULCON_STOP_BIT_SHIFT 1 156 157 /* UART Tx/Rx Status */ 158 #define UTRSTAT_TRANSMITTER_EMPTY 0x4 159 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 160 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 161 162 /* UART Error Status */ 163 #define UERSTAT_OVERRUN 0x1 164 #define UERSTAT_PARITY 0x2 165 #define UERSTAT_FRAME 0x4 166 #define UERSTAT_BREAK 0x8 167 168 typedef struct { 169 uint8_t *data; 170 uint32_t sp, rp; /* store and retrieve pointers */ 171 uint32_t size; 172 } Exynos4210UartFIFO; 173 174 #define TYPE_EXYNOS4210_UART "exynos4210.uart" 175 #define EXYNOS4210_UART(obj) \ 176 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 177 178 typedef struct Exynos4210UartState { 179 SysBusDevice parent_obj; 180 181 MemoryRegion iomem; 182 183 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 184 Exynos4210UartFIFO rx; 185 Exynos4210UartFIFO tx; 186 187 CharBackend chr; 188 qemu_irq irq; 189 190 uint32_t channel; 191 192 } Exynos4210UartState; 193 194 195 #if DEBUG_UART 196 /* Used only for debugging inside PRINT_DEBUG_... macros */ 197 static const char *exynos4210_uart_regname(hwaddr offset) 198 { 199 200 int i; 201 202 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 203 if (offset == exynos4210_uart_regs[i].offset) { 204 return exynos4210_uart_regs[i].name; 205 } 206 } 207 208 return NULL; 209 } 210 #endif 211 212 213 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 214 { 215 q->data[q->sp] = ch; 216 q->sp = (q->sp + 1) % q->size; 217 } 218 219 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 220 { 221 uint8_t ret = q->data[q->rp]; 222 q->rp = (q->rp + 1) % q->size; 223 return ret; 224 } 225 226 static int fifo_elements_number(const Exynos4210UartFIFO *q) 227 { 228 if (q->sp < q->rp) { 229 return q->size - q->rp + q->sp; 230 } 231 232 return q->sp - q->rp; 233 } 234 235 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 236 { 237 return q->size - fifo_elements_number(q); 238 } 239 240 static void fifo_reset(Exynos4210UartFIFO *q) 241 { 242 g_free(q->data); 243 q->data = NULL; 244 245 q->data = (uint8_t *)g_malloc0(q->size); 246 247 q->sp = 0; 248 q->rp = 0; 249 } 250 251 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 252 { 253 uint32_t level = 0; 254 uint32_t reg; 255 256 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 257 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 258 259 switch (s->channel) { 260 case 0: 261 level = reg * 32; 262 break; 263 case 1: 264 case 4: 265 level = reg * 8; 266 break; 267 case 2: 268 case 3: 269 level = reg * 2; 270 break; 271 default: 272 level = 0; 273 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); 274 } 275 276 return level; 277 } 278 279 static void exynos4210_uart_update_irq(Exynos4210UartState *s) 280 { 281 /* 282 * The Tx interrupt is always requested if the number of data in the 283 * transmit FIFO is smaller than the trigger level. 284 */ 285 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 286 287 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 288 UFSTAT_Tx_FIFO_COUNT_SHIFT; 289 290 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 291 s->reg[I_(UINTSP)] |= UINTSP_TXD; 292 } 293 } 294 295 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 296 297 if (s->reg[I_(UINTP)]) { 298 qemu_irq_raise(s->irq); 299 300 #if DEBUG_IRQ 301 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", 302 s->channel, s->reg[I_(UINTP)]); 303 #endif 304 305 } else { 306 qemu_irq_lower(s->irq); 307 } 308 } 309 310 static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 311 { 312 int speed, parity, data_bits, stop_bits; 313 QEMUSerialSetParams ssp; 314 uint64_t uclk_rate; 315 316 if (s->reg[I_(UBRDIV)] == 0) { 317 return; 318 } 319 320 if (s->reg[I_(ULCON)] & 0x20) { 321 if (s->reg[I_(ULCON)] & 0x28) { 322 parity = 'E'; 323 } else { 324 parity = 'O'; 325 } 326 } else { 327 parity = 'N'; 328 } 329 330 if (s->reg[I_(ULCON)] & 0x4) { 331 stop_bits = 2; 332 } else { 333 stop_bits = 1; 334 } 335 336 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 337 338 uclk_rate = 24000000; 339 340 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 341 (s->reg[I_(UFRACVAL)] & 0x7) + 16); 342 343 ssp.speed = speed; 344 ssp.parity = parity; 345 ssp.data_bits = data_bits; 346 ssp.stop_bits = stop_bits; 347 348 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 349 350 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", 351 s->channel, speed, parity, data_bits, stop_bits); 352 } 353 354 static void exynos4210_uart_write(void *opaque, hwaddr offset, 355 uint64_t val, unsigned size) 356 { 357 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 358 uint8_t ch; 359 360 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, 361 offset, exynos4210_uart_regname(offset), (long long unsigned int)val); 362 363 switch (offset) { 364 case ULCON: 365 case UBRDIV: 366 case UFRACVAL: 367 s->reg[I_(offset)] = val; 368 exynos4210_uart_update_parameters(s); 369 break; 370 case UFCON: 371 s->reg[I_(UFCON)] = val; 372 if (val & UFCON_Rx_FIFO_RESET) { 373 fifo_reset(&s->rx); 374 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 375 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); 376 } 377 if (val & UFCON_Tx_FIFO_RESET) { 378 fifo_reset(&s->tx); 379 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 380 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); 381 } 382 break; 383 384 case UTXH: 385 if (qemu_chr_fe_backend_connected(&s->chr)) { 386 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 387 UTRSTAT_Tx_BUFFER_EMPTY); 388 ch = (uint8_t)val; 389 /* XXX this blocks entire thread. Rewrite to use 390 * qemu_chr_fe_write and background I/O callbacks */ 391 qemu_chr_fe_write_all(&s->chr, &ch, 1); 392 #if DEBUG_Tx_DATA 393 fprintf(stderr, "%c", ch); 394 #endif 395 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 396 UTRSTAT_Tx_BUFFER_EMPTY; 397 s->reg[I_(UINTSP)] |= UINTSP_TXD; 398 exynos4210_uart_update_irq(s); 399 } 400 break; 401 402 case UINTP: 403 s->reg[I_(UINTP)] &= ~val; 404 s->reg[I_(UINTSP)] &= ~val; 405 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", 406 s->channel, offset, s->reg[I_(UINTP)]); 407 exynos4210_uart_update_irq(s); 408 break; 409 case UTRSTAT: 410 case UERSTAT: 411 case UFSTAT: 412 case UMSTAT: 413 case URXH: 414 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", 415 s->channel, exynos4210_uart_regname(offset), offset); 416 break; 417 case UINTSP: 418 s->reg[I_(UINTSP)] &= ~val; 419 break; 420 case UINTM: 421 s->reg[I_(UINTM)] = val; 422 exynos4210_uart_update_irq(s); 423 break; 424 case UCON: 425 case UMCON: 426 default: 427 s->reg[I_(offset)] = val; 428 break; 429 } 430 } 431 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 432 unsigned size) 433 { 434 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 435 uint32_t res; 436 437 switch (offset) { 438 case UERSTAT: /* Read Only */ 439 res = s->reg[I_(UERSTAT)]; 440 s->reg[I_(UERSTAT)] = 0; 441 return res; 442 case UFSTAT: /* Read Only */ 443 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 444 if (fifo_empty_elements_number(&s->rx) == 0) { 445 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 446 s->reg[I_(UFSTAT)] &= ~0xff; 447 } 448 return s->reg[I_(UFSTAT)]; 449 case URXH: 450 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 451 if (fifo_elements_number(&s->rx)) { 452 res = fifo_retrieve(&s->rx); 453 #if DEBUG_Rx_DATA 454 fprintf(stderr, "%c", res); 455 #endif 456 if (!fifo_elements_number(&s->rx)) { 457 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 458 } else { 459 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 460 } 461 } else { 462 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 463 exynos4210_uart_update_irq(s); 464 res = 0; 465 } 466 } else { 467 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 468 res = s->reg[I_(URXH)]; 469 } 470 return res; 471 case UTXH: 472 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", 473 s->channel, exynos4210_uart_regname(offset), offset); 474 break; 475 default: 476 return s->reg[I_(offset)]; 477 } 478 479 return 0; 480 } 481 482 static const MemoryRegionOps exynos4210_uart_ops = { 483 .read = exynos4210_uart_read, 484 .write = exynos4210_uart_write, 485 .endianness = DEVICE_NATIVE_ENDIAN, 486 .valid = { 487 .max_access_size = 4, 488 .unaligned = false 489 }, 490 }; 491 492 static int exynos4210_uart_can_receive(void *opaque) 493 { 494 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 495 496 return fifo_empty_elements_number(&s->rx); 497 } 498 499 500 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 501 { 502 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 503 int i; 504 505 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 506 if (fifo_empty_elements_number(&s->rx) < size) { 507 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { 508 fifo_store(&s->rx, buf[i]); 509 } 510 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 511 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 512 } else { 513 for (i = 0; i < size; i++) { 514 fifo_store(&s->rx, buf[i]); 515 } 516 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 517 } 518 /* XXX: Around here we maybe should check Rx trigger level */ 519 s->reg[I_(UINTSP)] |= UINTSP_RXD; 520 } else { 521 s->reg[I_(URXH)] = buf[0]; 522 s->reg[I_(UINTSP)] |= UINTSP_RXD; 523 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 524 } 525 526 exynos4210_uart_update_irq(s); 527 } 528 529 530 static void exynos4210_uart_event(void *opaque, int event) 531 { 532 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 533 534 if (event == CHR_EVENT_BREAK) { 535 /* When the RxDn is held in logic 0, then a null byte is pushed into the 536 * fifo */ 537 fifo_store(&s->rx, '\0'); 538 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 539 exynos4210_uart_update_irq(s); 540 } 541 } 542 543 544 static void exynos4210_uart_reset(DeviceState *dev) 545 { 546 Exynos4210UartState *s = EXYNOS4210_UART(dev); 547 int i; 548 549 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 550 s->reg[I_(exynos4210_uart_regs[i].offset)] = 551 exynos4210_uart_regs[i].reset_value; 552 } 553 554 fifo_reset(&s->rx); 555 fifo_reset(&s->tx); 556 557 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); 558 } 559 560 static const VMStateDescription vmstate_exynos4210_uart_fifo = { 561 .name = "exynos4210.uart.fifo", 562 .version_id = 1, 563 .minimum_version_id = 1, 564 .fields = (VMStateField[]) { 565 VMSTATE_UINT32(sp, Exynos4210UartFIFO), 566 VMSTATE_UINT32(rp, Exynos4210UartFIFO), 567 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 568 VMSTATE_END_OF_LIST() 569 } 570 }; 571 572 static const VMStateDescription vmstate_exynos4210_uart = { 573 .name = "exynos4210.uart", 574 .version_id = 1, 575 .minimum_version_id = 1, 576 .fields = (VMStateField[]) { 577 VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 578 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 579 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 580 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 581 VMSTATE_END_OF_LIST() 582 } 583 }; 584 585 DeviceState *exynos4210_uart_create(hwaddr addr, 586 int fifo_size, 587 int channel, 588 Chardev *chr, 589 qemu_irq irq) 590 { 591 DeviceState *dev; 592 SysBusDevice *bus; 593 594 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 595 596 qdev_prop_set_chr(dev, "chardev", chr); 597 qdev_prop_set_uint32(dev, "channel", channel); 598 qdev_prop_set_uint32(dev, "rx-size", fifo_size); 599 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 600 601 bus = SYS_BUS_DEVICE(dev); 602 qdev_init_nofail(dev); 603 if (addr != (hwaddr)-1) { 604 sysbus_mmio_map(bus, 0, addr); 605 } 606 sysbus_connect_irq(bus, 0, irq); 607 608 return dev; 609 } 610 611 static void exynos4210_uart_init(Object *obj) 612 { 613 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 614 Exynos4210UartState *s = EXYNOS4210_UART(dev); 615 616 /* memory mapping */ 617 memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 618 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 619 sysbus_init_mmio(dev, &s->iomem); 620 621 sysbus_init_irq(dev, &s->irq); 622 } 623 624 static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 625 { 626 Exynos4210UartState *s = EXYNOS4210_UART(dev); 627 628 qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 629 exynos4210_uart_receive, exynos4210_uart_event, 630 NULL, s, NULL, true); 631 } 632 633 static Property exynos4210_uart_properties[] = { 634 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 635 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 636 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 637 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 638 DEFINE_PROP_END_OF_LIST(), 639 }; 640 641 static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 642 { 643 DeviceClass *dc = DEVICE_CLASS(klass); 644 645 dc->realize = exynos4210_uart_realize; 646 dc->reset = exynos4210_uart_reset; 647 dc->props = exynos4210_uart_properties; 648 dc->vmsd = &vmstate_exynos4210_uart; 649 } 650 651 static const TypeInfo exynos4210_uart_info = { 652 .name = TYPE_EXYNOS4210_UART, 653 .parent = TYPE_SYS_BUS_DEVICE, 654 .instance_size = sizeof(Exynos4210UartState), 655 .instance_init = exynos4210_uart_init, 656 .class_init = exynos4210_uart_class_init, 657 }; 658 659 static void exynos4210_uart_register(void) 660 { 661 type_register_static(&exynos4210_uart_info); 662 } 663 664 type_init(exynos4210_uart_register) 665