1 /* 2 * Exynos4210 UART Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include "chardev/char-fe.h" 30 #include "chardev/char-serial.h" 31 32 #include "hw/arm/exynos4210.h" 33 #include "hw/irq.h" 34 #include "hw/qdev-properties.h" 35 36 #include "trace.h" 37 38 /* 39 * Offsets for UART registers relative to SFR base address 40 * for UARTn 41 * 42 */ 43 #define ULCON 0x0000 /* Line Control */ 44 #define UCON 0x0004 /* Control */ 45 #define UFCON 0x0008 /* FIFO Control */ 46 #define UMCON 0x000C /* Modem Control */ 47 #define UTRSTAT 0x0010 /* Tx/Rx Status */ 48 #define UERSTAT 0x0014 /* UART Error Status */ 49 #define UFSTAT 0x0018 /* FIFO Status */ 50 #define UMSTAT 0x001C /* Modem Status */ 51 #define UTXH 0x0020 /* Transmit Buffer */ 52 #define URXH 0x0024 /* Receive Buffer */ 53 #define UBRDIV 0x0028 /* Baud Rate Divisor */ 54 #define UFRACVAL 0x002C /* Divisor Fractional Value */ 55 #define UINTP 0x0030 /* Interrupt Pending */ 56 #define UINTSP 0x0034 /* Interrupt Source Pending */ 57 #define UINTM 0x0038 /* Interrupt Mask */ 58 59 /* 60 * for indexing register in the uint32_t array 61 * 62 * 'reg' - register offset (see offsets definitions above) 63 * 64 */ 65 #define I_(reg) (reg / sizeof(uint32_t)) 66 67 typedef struct Exynos4210UartReg { 68 const char *name; /* the only reason is the debug output */ 69 hwaddr offset; 70 uint32_t reset_value; 71 } Exynos4210UartReg; 72 73 static const Exynos4210UartReg exynos4210_uart_regs[] = { 74 {"ULCON", ULCON, 0x00000000}, 75 {"UCON", UCON, 0x00003000}, 76 {"UFCON", UFCON, 0x00000000}, 77 {"UMCON", UMCON, 0x00000000}, 78 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 79 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 80 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 81 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 82 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 83 {"URXH", URXH, 0x00000000}, /* RO */ 84 {"UBRDIV", UBRDIV, 0x00000000}, 85 {"UFRACVAL", UFRACVAL, 0x00000000}, 86 {"UINTP", UINTP, 0x00000000}, 87 {"UINTSP", UINTSP, 0x00000000}, 88 {"UINTM", UINTM, 0x00000000}, 89 }; 90 91 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 92 93 /* UART FIFO Control */ 94 #define UFCON_FIFO_ENABLE 0x1 95 #define UFCON_Rx_FIFO_RESET 0x2 96 #define UFCON_Tx_FIFO_RESET 0x4 97 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 98 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 99 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 100 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 101 102 /* Uart FIFO Status */ 103 #define UFSTAT_Rx_FIFO_COUNT 0xff 104 #define UFSTAT_Rx_FIFO_FULL 0x100 105 #define UFSTAT_Rx_FIFO_ERROR 0x200 106 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 107 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 108 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 109 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 110 111 /* UART Interrupt Source Pending */ 112 #define UINTSP_RXD 0x1 /* Receive interrupt */ 113 #define UINTSP_ERROR 0x2 /* Error interrupt */ 114 #define UINTSP_TXD 0x4 /* Transmit interrupt */ 115 #define UINTSP_MODEM 0x8 /* Modem interrupt */ 116 117 /* UART Line Control */ 118 #define ULCON_IR_MODE_SHIFT 6 119 #define ULCON_PARITY_SHIFT 3 120 #define ULCON_STOP_BIT_SHIFT 1 121 122 /* UART Tx/Rx Status */ 123 #define UTRSTAT_Rx_TIMEOUT 0x8 124 #define UTRSTAT_TRANSMITTER_EMPTY 0x4 125 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 126 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 127 128 /* UART Error Status */ 129 #define UERSTAT_OVERRUN 0x1 130 #define UERSTAT_PARITY 0x2 131 #define UERSTAT_FRAME 0x4 132 #define UERSTAT_BREAK 0x8 133 134 typedef struct { 135 uint8_t *data; 136 uint32_t sp, rp; /* store and retrieve pointers */ 137 uint32_t size; 138 } Exynos4210UartFIFO; 139 140 #define TYPE_EXYNOS4210_UART "exynos4210.uart" 141 #define EXYNOS4210_UART(obj) \ 142 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 143 144 typedef struct Exynos4210UartState { 145 SysBusDevice parent_obj; 146 147 MemoryRegion iomem; 148 149 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 150 Exynos4210UartFIFO rx; 151 Exynos4210UartFIFO tx; 152 153 QEMUTimer *fifo_timeout_timer; 154 uint64_t wordtime; /* word time in ns */ 155 156 CharBackend chr; 157 qemu_irq irq; 158 qemu_irq dmairq; 159 160 uint32_t channel; 161 162 } Exynos4210UartState; 163 164 165 /* Used only for tracing */ 166 static const char *exynos4210_uart_regname(hwaddr offset) 167 { 168 169 int i; 170 171 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 172 if (offset == exynos4210_uart_regs[i].offset) { 173 return exynos4210_uart_regs[i].name; 174 } 175 } 176 177 return NULL; 178 } 179 180 181 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 182 { 183 q->data[q->sp] = ch; 184 q->sp = (q->sp + 1) % q->size; 185 } 186 187 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 188 { 189 uint8_t ret = q->data[q->rp]; 190 q->rp = (q->rp + 1) % q->size; 191 return ret; 192 } 193 194 static int fifo_elements_number(const Exynos4210UartFIFO *q) 195 { 196 if (q->sp < q->rp) { 197 return q->size - q->rp + q->sp; 198 } 199 200 return q->sp - q->rp; 201 } 202 203 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 204 { 205 return q->size - fifo_elements_number(q); 206 } 207 208 static void fifo_reset(Exynos4210UartFIFO *q) 209 { 210 g_free(q->data); 211 q->data = NULL; 212 213 q->data = (uint8_t *)g_malloc0(q->size); 214 215 q->sp = 0; 216 q->rp = 0; 217 } 218 219 static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel, 220 uint32_t reg) 221 { 222 uint32_t level; 223 224 switch (channel) { 225 case 0: 226 level = reg * 32; 227 break; 228 case 1: 229 case 4: 230 level = reg * 8; 231 break; 232 case 2: 233 case 3: 234 level = reg * 2; 235 break; 236 default: 237 level = 0; 238 trace_exynos_uart_channel_error(channel); 239 break; 240 } 241 return level; 242 } 243 244 static uint32_t 245 exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 246 { 247 uint32_t reg; 248 249 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 250 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 251 252 return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 253 } 254 255 static uint32_t 256 exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s) 257 { 258 uint32_t reg; 259 260 reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >> 261 UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1; 262 263 return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 264 } 265 266 /* 267 * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity, 268 * mark DMA as busy if DMA is enabled and the receive buffer is empty. 269 */ 270 static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s) 271 { 272 bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02; 273 uint32_t count = fifo_elements_number(&s->rx); 274 275 if (rx_dma_enabled && !count) { 276 qemu_irq_raise(s->dmairq); 277 trace_exynos_uart_dmabusy(s->channel); 278 } else { 279 qemu_irq_lower(s->dmairq); 280 trace_exynos_uart_dmaready(s->channel); 281 } 282 } 283 284 static void exynos4210_uart_update_irq(Exynos4210UartState *s) 285 { 286 /* 287 * The Tx interrupt is always requested if the number of data in the 288 * transmit FIFO is smaller than the trigger level. 289 */ 290 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 291 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 292 UFSTAT_Tx_FIFO_COUNT_SHIFT; 293 294 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 295 s->reg[I_(UINTSP)] |= UINTSP_TXD; 296 } 297 298 /* 299 * Rx interrupt if trigger level is reached or if rx timeout 300 * interrupt is disabled and there is data in the receive buffer 301 */ 302 count = fifo_elements_number(&s->rx); 303 if ((count && !(s->reg[I_(UCON)] & 0x80)) || 304 count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) { 305 exynos4210_uart_update_dmabusy(s); 306 s->reg[I_(UINTSP)] |= UINTSP_RXD; 307 timer_del(s->fifo_timeout_timer); 308 } 309 } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) { 310 exynos4210_uart_update_dmabusy(s); 311 s->reg[I_(UINTSP)] |= UINTSP_RXD; 312 } 313 314 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 315 316 if (s->reg[I_(UINTP)]) { 317 qemu_irq_raise(s->irq); 318 trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); 319 } else { 320 qemu_irq_lower(s->irq); 321 trace_exynos_uart_irq_lowered(s->channel); 322 } 323 } 324 325 static void exynos4210_uart_timeout_int(void *opaque) 326 { 327 Exynos4210UartState *s = opaque; 328 329 trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)], 330 s->reg[I_(UINTSP)]); 331 332 if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) || 333 (s->reg[I_(UCON)] & (1 << 11))) { 334 s->reg[I_(UINTSP)] |= UINTSP_RXD; 335 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT; 336 exynos4210_uart_update_dmabusy(s); 337 exynos4210_uart_update_irq(s); 338 } 339 } 340 341 static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 342 { 343 int speed, parity, data_bits, stop_bits; 344 QEMUSerialSetParams ssp; 345 uint64_t uclk_rate; 346 347 if (s->reg[I_(UBRDIV)] == 0) { 348 return; 349 } 350 351 if (s->reg[I_(ULCON)] & 0x20) { 352 if (s->reg[I_(ULCON)] & 0x28) { 353 parity = 'E'; 354 } else { 355 parity = 'O'; 356 } 357 } else { 358 parity = 'N'; 359 } 360 361 if (s->reg[I_(ULCON)] & 0x4) { 362 stop_bits = 2; 363 } else { 364 stop_bits = 1; 365 } 366 367 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 368 369 uclk_rate = 24000000; 370 371 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 372 (s->reg[I_(UFRACVAL)] & 0x7) + 16); 373 374 ssp.speed = speed; 375 ssp.parity = parity; 376 ssp.data_bits = data_bits; 377 ssp.stop_bits = stop_bits; 378 379 s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed; 380 381 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 382 383 trace_exynos_uart_update_params( 384 s->channel, speed, parity, data_bits, stop_bits, s->wordtime); 385 } 386 387 static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s) 388 { 389 if (s->reg[I_(UCON)] & 0x80) { 390 uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime; 391 392 timer_mod(s->fifo_timeout_timer, 393 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); 394 } else { 395 timer_del(s->fifo_timeout_timer); 396 } 397 } 398 399 static void exynos4210_uart_write(void *opaque, hwaddr offset, 400 uint64_t val, unsigned size) 401 { 402 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 403 uint8_t ch; 404 405 trace_exynos_uart_write(s->channel, offset, 406 exynos4210_uart_regname(offset), val); 407 408 switch (offset) { 409 case ULCON: 410 case UBRDIV: 411 case UFRACVAL: 412 s->reg[I_(offset)] = val; 413 exynos4210_uart_update_parameters(s); 414 break; 415 case UFCON: 416 s->reg[I_(UFCON)] = val; 417 if (val & UFCON_Rx_FIFO_RESET) { 418 fifo_reset(&s->rx); 419 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 420 trace_exynos_uart_rx_fifo_reset(s->channel); 421 } 422 if (val & UFCON_Tx_FIFO_RESET) { 423 fifo_reset(&s->tx); 424 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 425 trace_exynos_uart_tx_fifo_reset(s->channel); 426 } 427 break; 428 429 case UTXH: 430 if (qemu_chr_fe_backend_connected(&s->chr)) { 431 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 432 UTRSTAT_Tx_BUFFER_EMPTY); 433 ch = (uint8_t)val; 434 /* XXX this blocks entire thread. Rewrite to use 435 * qemu_chr_fe_write and background I/O callbacks */ 436 qemu_chr_fe_write_all(&s->chr, &ch, 1); 437 trace_exynos_uart_tx(s->channel, ch); 438 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 439 UTRSTAT_Tx_BUFFER_EMPTY; 440 s->reg[I_(UINTSP)] |= UINTSP_TXD; 441 exynos4210_uart_update_irq(s); 442 } 443 break; 444 445 case UINTP: 446 s->reg[I_(UINTP)] &= ~val; 447 s->reg[I_(UINTSP)] &= ~val; 448 trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]); 449 exynos4210_uart_update_irq(s); 450 break; 451 case UTRSTAT: 452 if (val & UTRSTAT_Rx_TIMEOUT) { 453 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT; 454 } 455 break; 456 case UERSTAT: 457 case UFSTAT: 458 case UMSTAT: 459 case URXH: 460 trace_exynos_uart_ro_write( 461 s->channel, exynos4210_uart_regname(offset), offset); 462 break; 463 case UINTSP: 464 s->reg[I_(UINTSP)] &= ~val; 465 break; 466 case UINTM: 467 s->reg[I_(UINTM)] = val; 468 exynos4210_uart_update_irq(s); 469 break; 470 case UCON: 471 case UMCON: 472 default: 473 s->reg[I_(offset)] = val; 474 break; 475 } 476 } 477 478 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 479 unsigned size) 480 { 481 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 482 uint32_t res; 483 484 switch (offset) { 485 case UERSTAT: /* Read Only */ 486 res = s->reg[I_(UERSTAT)]; 487 s->reg[I_(UERSTAT)] = 0; 488 trace_exynos_uart_read(s->channel, offset, 489 exynos4210_uart_regname(offset), res); 490 return res; 491 case UFSTAT: /* Read Only */ 492 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 493 if (fifo_empty_elements_number(&s->rx) == 0) { 494 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 495 s->reg[I_(UFSTAT)] &= ~0xff; 496 } 497 trace_exynos_uart_read(s->channel, offset, 498 exynos4210_uart_regname(offset), 499 s->reg[I_(UFSTAT)]); 500 return s->reg[I_(UFSTAT)]; 501 case URXH: 502 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 503 if (fifo_elements_number(&s->rx)) { 504 res = fifo_retrieve(&s->rx); 505 trace_exynos_uart_rx(s->channel, res); 506 if (!fifo_elements_number(&s->rx)) { 507 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 508 } else { 509 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 510 } 511 } else { 512 trace_exynos_uart_rx_error(s->channel); 513 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 514 exynos4210_uart_update_irq(s); 515 res = 0; 516 } 517 } else { 518 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 519 res = s->reg[I_(URXH)]; 520 } 521 exynos4210_uart_update_dmabusy(s); 522 trace_exynos_uart_read(s->channel, offset, 523 exynos4210_uart_regname(offset), res); 524 return res; 525 case UTXH: 526 trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset), 527 offset); 528 break; 529 default: 530 trace_exynos_uart_read(s->channel, offset, 531 exynos4210_uart_regname(offset), 532 s->reg[I_(offset)]); 533 return s->reg[I_(offset)]; 534 } 535 536 trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset), 537 0); 538 return 0; 539 } 540 541 static const MemoryRegionOps exynos4210_uart_ops = { 542 .read = exynos4210_uart_read, 543 .write = exynos4210_uart_write, 544 .endianness = DEVICE_NATIVE_ENDIAN, 545 .valid = { 546 .max_access_size = 4, 547 .unaligned = false 548 }, 549 }; 550 551 static int exynos4210_uart_can_receive(void *opaque) 552 { 553 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 554 555 return fifo_empty_elements_number(&s->rx); 556 } 557 558 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 559 { 560 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 561 int i; 562 563 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 564 if (fifo_empty_elements_number(&s->rx) < size) { 565 size = fifo_empty_elements_number(&s->rx); 566 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 567 } 568 for (i = 0; i < size; i++) { 569 fifo_store(&s->rx, buf[i]); 570 } 571 exynos4210_uart_rx_timeout_set(s); 572 } else { 573 s->reg[I_(URXH)] = buf[0]; 574 } 575 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 576 577 exynos4210_uart_update_irq(s); 578 } 579 580 581 static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) 582 { 583 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 584 585 if (event == CHR_EVENT_BREAK) { 586 /* When the RxDn is held in logic 0, then a null byte is pushed into the 587 * fifo */ 588 fifo_store(&s->rx, '\0'); 589 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 590 exynos4210_uart_update_irq(s); 591 } 592 } 593 594 595 static void exynos4210_uart_reset(DeviceState *dev) 596 { 597 Exynos4210UartState *s = EXYNOS4210_UART(dev); 598 int i; 599 600 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 601 s->reg[I_(exynos4210_uart_regs[i].offset)] = 602 exynos4210_uart_regs[i].reset_value; 603 } 604 605 fifo_reset(&s->rx); 606 fifo_reset(&s->tx); 607 608 trace_exynos_uart_rxsize(s->channel, s->rx.size); 609 } 610 611 static int exynos4210_uart_post_load(void *opaque, int version_id) 612 { 613 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 614 615 exynos4210_uart_update_parameters(s); 616 exynos4210_uart_rx_timeout_set(s); 617 618 return 0; 619 } 620 621 static const VMStateDescription vmstate_exynos4210_uart_fifo = { 622 .name = "exynos4210.uart.fifo", 623 .version_id = 1, 624 .minimum_version_id = 1, 625 .post_load = exynos4210_uart_post_load, 626 .fields = (VMStateField[]) { 627 VMSTATE_UINT32(sp, Exynos4210UartFIFO), 628 VMSTATE_UINT32(rp, Exynos4210UartFIFO), 629 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 630 VMSTATE_END_OF_LIST() 631 } 632 }; 633 634 static const VMStateDescription vmstate_exynos4210_uart = { 635 .name = "exynos4210.uart", 636 .version_id = 1, 637 .minimum_version_id = 1, 638 .fields = (VMStateField[]) { 639 VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 640 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 641 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 642 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 643 VMSTATE_END_OF_LIST() 644 } 645 }; 646 647 DeviceState *exynos4210_uart_create(hwaddr addr, 648 int fifo_size, 649 int channel, 650 Chardev *chr, 651 qemu_irq irq) 652 { 653 DeviceState *dev; 654 SysBusDevice *bus; 655 656 dev = qdev_new(TYPE_EXYNOS4210_UART); 657 658 qdev_prop_set_chr(dev, "chardev", chr); 659 qdev_prop_set_uint32(dev, "channel", channel); 660 qdev_prop_set_uint32(dev, "rx-size", fifo_size); 661 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 662 663 bus = SYS_BUS_DEVICE(dev); 664 sysbus_realize_and_unref(bus, &error_fatal); 665 if (addr != (hwaddr)-1) { 666 sysbus_mmio_map(bus, 0, addr); 667 } 668 sysbus_connect_irq(bus, 0, irq); 669 670 return dev; 671 } 672 673 static void exynos4210_uart_init(Object *obj) 674 { 675 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 676 Exynos4210UartState *s = EXYNOS4210_UART(dev); 677 678 s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600; 679 680 /* memory mapping */ 681 memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 682 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 683 sysbus_init_mmio(dev, &s->iomem); 684 685 sysbus_init_irq(dev, &s->irq); 686 sysbus_init_irq(dev, &s->dmairq); 687 } 688 689 static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 690 { 691 Exynos4210UartState *s = EXYNOS4210_UART(dev); 692 693 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 694 exynos4210_uart_timeout_int, s); 695 696 qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 697 exynos4210_uart_receive, exynos4210_uart_event, 698 NULL, s, NULL, true); 699 } 700 701 static Property exynos4210_uart_properties[] = { 702 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 703 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 704 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 705 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 706 DEFINE_PROP_END_OF_LIST(), 707 }; 708 709 static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 710 { 711 DeviceClass *dc = DEVICE_CLASS(klass); 712 713 dc->realize = exynos4210_uart_realize; 714 dc->reset = exynos4210_uart_reset; 715 device_class_set_props(dc, exynos4210_uart_properties); 716 dc->vmsd = &vmstate_exynos4210_uart; 717 } 718 719 static const TypeInfo exynos4210_uart_info = { 720 .name = TYPE_EXYNOS4210_UART, 721 .parent = TYPE_SYS_BUS_DEVICE, 722 .instance_size = sizeof(Exynos4210UartState), 723 .instance_init = exynos4210_uart_init, 724 .class_init = exynos4210_uart_class_init, 725 }; 726 727 static void exynos4210_uart_register(void) 728 { 729 type_register_static(&exynos4210_uart_info); 730 } 731 732 type_init(exynos4210_uart_register) 733