1 /* 2 * QEMU ETRAX System Emulator 3 * 4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "chardev/char-fe.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 31 #define D(x) 32 33 #define RW_TR_CTRL (0x00 / 4) 34 #define RW_TR_DMA_EN (0x04 / 4) 35 #define RW_REC_CTRL (0x08 / 4) 36 #define RW_DOUT (0x1c / 4) 37 #define RS_STAT_DIN (0x20 / 4) 38 #define R_STAT_DIN (0x24 / 4) 39 #define RW_INTR_MASK (0x2c / 4) 40 #define RW_ACK_INTR (0x30 / 4) 41 #define R_INTR (0x34 / 4) 42 #define R_MASKED_INTR (0x38 / 4) 43 #define R_MAX (0x3c / 4) 44 45 #define STAT_DAV 16 46 #define STAT_TR_IDLE 22 47 #define STAT_TR_RDY 24 48 49 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial" 50 #define ETRAX_SERIAL(obj) \ 51 OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL) 52 53 typedef struct ETRAXSerial { 54 SysBusDevice parent_obj; 55 56 MemoryRegion mmio; 57 CharBackend chr; 58 qemu_irq irq; 59 60 int pending_tx; 61 62 uint8_t rx_fifo[16]; 63 unsigned int rx_fifo_pos; 64 unsigned int rx_fifo_len; 65 66 /* Control registers. */ 67 uint32_t regs[R_MAX]; 68 } ETRAXSerial; 69 70 static void ser_update_irq(ETRAXSerial *s) 71 { 72 73 if (s->rx_fifo_len) { 74 s->regs[R_INTR] |= 8; 75 } else { 76 s->regs[R_INTR] &= ~8; 77 } 78 79 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; 80 qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]); 81 } 82 83 static uint64_t 84 ser_read(void *opaque, hwaddr addr, unsigned int size) 85 { 86 ETRAXSerial *s = opaque; 87 uint32_t r = 0; 88 89 addr >>= 2; 90 switch (addr) 91 { 92 case R_STAT_DIN: 93 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; 94 if (s->rx_fifo_len) { 95 r |= 1 << STAT_DAV; 96 } 97 r |= 1 << STAT_TR_RDY; 98 r |= 1 << STAT_TR_IDLE; 99 break; 100 case RS_STAT_DIN: 101 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; 102 if (s->rx_fifo_len) { 103 r |= 1 << STAT_DAV; 104 s->rx_fifo_len--; 105 } 106 r |= 1 << STAT_TR_RDY; 107 r |= 1 << STAT_TR_IDLE; 108 break; 109 default: 110 r = s->regs[addr]; 111 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); 112 break; 113 } 114 return r; 115 } 116 117 static void 118 ser_write(void *opaque, hwaddr addr, 119 uint64_t val64, unsigned int size) 120 { 121 ETRAXSerial *s = opaque; 122 uint32_t value = val64; 123 unsigned char ch = val64; 124 125 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); 126 addr >>= 2; 127 switch (addr) 128 { 129 case RW_DOUT: 130 /* XXX this blocks entire thread. Rewrite to use 131 * qemu_chr_fe_write and background I/O callbacks */ 132 qemu_chr_fe_write_all(&s->chr, &ch, 1); 133 s->regs[R_INTR] |= 3; 134 s->pending_tx = 1; 135 s->regs[addr] = value; 136 break; 137 case RW_ACK_INTR: 138 if (s->pending_tx) { 139 value &= ~1; 140 s->pending_tx = 0; 141 D(qemu_log("fixedup value=%x r_intr=%x\n", 142 value, s->regs[R_INTR])); 143 } 144 s->regs[addr] = value; 145 s->regs[R_INTR] &= ~value; 146 D(printf("r_intr=%x\n", s->regs[R_INTR])); 147 break; 148 default: 149 s->regs[addr] = value; 150 break; 151 } 152 ser_update_irq(s); 153 } 154 155 static const MemoryRegionOps ser_ops = { 156 .read = ser_read, 157 .write = ser_write, 158 .endianness = DEVICE_NATIVE_ENDIAN, 159 .valid = { 160 .min_access_size = 4, 161 .max_access_size = 4 162 } 163 }; 164 165 static Property etraxfs_ser_properties[] = { 166 DEFINE_PROP_CHR("chardev", ETRAXSerial, chr), 167 DEFINE_PROP_END_OF_LIST(), 168 }; 169 170 static void serial_receive(void *opaque, const uint8_t *buf, int size) 171 { 172 ETRAXSerial *s = opaque; 173 int i; 174 175 /* Got a byte. */ 176 if (s->rx_fifo_len >= 16) { 177 D(qemu_log("WARNING: UART dropped char.\n")); 178 return; 179 } 180 181 for (i = 0; i < size; i++) { 182 s->rx_fifo[s->rx_fifo_pos] = buf[i]; 183 s->rx_fifo_pos++; 184 s->rx_fifo_pos &= 15; 185 s->rx_fifo_len++; 186 } 187 188 ser_update_irq(s); 189 } 190 191 static int serial_can_receive(void *opaque) 192 { 193 ETRAXSerial *s = opaque; 194 195 /* Is the receiver enabled? */ 196 if (!(s->regs[RW_REC_CTRL] & (1 << 3))) { 197 return 0; 198 } 199 200 return sizeof(s->rx_fifo) - s->rx_fifo_len; 201 } 202 203 static void serial_event(void *opaque, int event) 204 { 205 206 } 207 208 static void etraxfs_ser_reset(DeviceState *d) 209 { 210 ETRAXSerial *s = ETRAX_SERIAL(d); 211 212 /* transmitter begins ready and idle. */ 213 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY); 214 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); 215 216 s->regs[RW_REC_CTRL] = 0x10000; 217 218 } 219 220 static void etraxfs_ser_init(Object *obj) 221 { 222 ETRAXSerial *s = ETRAX_SERIAL(obj); 223 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 224 225 sysbus_init_irq(dev, &s->irq); 226 memory_region_init_io(&s->mmio, obj, &ser_ops, s, 227 "etraxfs-serial", R_MAX * 4); 228 sysbus_init_mmio(dev, &s->mmio); 229 } 230 231 static void etraxfs_ser_realize(DeviceState *dev, Error **errp) 232 { 233 ETRAXSerial *s = ETRAX_SERIAL(dev); 234 235 qemu_chr_fe_set_handlers(&s->chr, 236 serial_can_receive, serial_receive, 237 serial_event, NULL, s, NULL, true); 238 } 239 240 static void etraxfs_ser_class_init(ObjectClass *klass, void *data) 241 { 242 DeviceClass *dc = DEVICE_CLASS(klass); 243 244 dc->reset = etraxfs_ser_reset; 245 dc->props = etraxfs_ser_properties; 246 dc->realize = etraxfs_ser_realize; 247 } 248 249 static const TypeInfo etraxfs_ser_info = { 250 .name = TYPE_ETRAX_FS_SERIAL, 251 .parent = TYPE_SYS_BUS_DEVICE, 252 .instance_size = sizeof(ETRAXSerial), 253 .instance_init = etraxfs_ser_init, 254 .class_init = etraxfs_ser_class_init, 255 }; 256 257 static void etraxfs_serial_register_types(void) 258 { 259 type_register_static(&etraxfs_ser_info); 260 } 261 262 type_init(etraxfs_serial_register_types) 263